1372401efSJerome Brunet* Amlogic AXG Audio Clock Controllers 2372401efSJerome Brunet 3372401efSJerome BrunetThe Amlogic AXG audio clock controller generates and supplies clock to the 4372401efSJerome Brunetother elements of the audio subsystem, such as fifos, i2s, spdif and pdm 5372401efSJerome Brunetdevices. 6372401efSJerome Brunet 7372401efSJerome BrunetRequired Properties: 8372401efSJerome Brunet 98554926bSJerome Brunet- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D, 10*0ea0a188SJerome Brunet "amlogic,g12a-audio-clkc" for G12A, 11*0ea0a188SJerome Brunet "amlogic,sm1-audio-clkc" for S905X3. 12372401efSJerome Brunet- reg : physical base address of the clock controller and length of 13372401efSJerome Brunet memory mapped region. 14372401efSJerome Brunet- clocks : a list of phandle + clock-specifier pairs for the clocks listed 15372401efSJerome Brunet in clock-names. 16372401efSJerome Brunet- clock-names : must contain the following: 17372401efSJerome Brunet * "pclk" - Main peripheral bus clock 18372401efSJerome Brunet may contain the following: 19372401efSJerome Brunet * "mst_in[0-7]" - 8 input plls to generate clock signals 20372401efSJerome Brunet * "slv_sclk[0-9]" - 10 slave bit clocks provided by external 21372401efSJerome Brunet components. 22372401efSJerome Brunet * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external 23372401efSJerome Brunet components. 24372401efSJerome Brunet- resets : phandle of the internal reset line 25372401efSJerome Brunet- #clock-cells : should be 1. 260688587aSJerome Brunet- #reset-cells : should be 1 on the g12a (and following) soc family 27372401efSJerome Brunet 28372401efSJerome BrunetEach clock is assigned an identifier and client nodes can use this identifier 29372401efSJerome Brunetto specify the clock which they consume. All available clocks are defined as 30372401efSJerome Brunetpreprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be 31372401efSJerome Brunetused in device tree sources. 32372401efSJerome Brunet 33372401efSJerome BrunetExample: 34372401efSJerome Brunet 35372401efSJerome Brunetclkc_audio: clock-controller@0 { 36372401efSJerome Brunet compatible = "amlogic,axg-audio-clkc"; 37372401efSJerome Brunet reg = <0x0 0x0 0x0 0xb4>; 38372401efSJerome Brunet #clock-cells = <1>; 39372401efSJerome Brunet 40372401efSJerome Brunet clocks = <&clkc CLKID_AUDIO>, 41372401efSJerome Brunet <&clkc CLKID_MPLL0>, 42372401efSJerome Brunet <&clkc CLKID_MPLL1>, 43372401efSJerome Brunet <&clkc CLKID_MPLL2>, 44372401efSJerome Brunet <&clkc CLKID_MPLL3>, 45372401efSJerome Brunet <&clkc CLKID_HIFI_PLL>, 46372401efSJerome Brunet <&clkc CLKID_FCLK_DIV3>, 47372401efSJerome Brunet <&clkc CLKID_FCLK_DIV4>, 48372401efSJerome Brunet <&clkc CLKID_GP0_PLL>; 49372401efSJerome Brunet clock-names = "pclk", 50372401efSJerome Brunet "mst_in0", 51372401efSJerome Brunet "mst_in1", 52372401efSJerome Brunet "mst_in2", 53372401efSJerome Brunet "mst_in3", 54372401efSJerome Brunet "mst_in4", 55372401efSJerome Brunet "mst_in5", 56372401efSJerome Brunet "mst_in6", 57372401efSJerome Brunet "mst_in7"; 58372401efSJerome Brunet resets = <&reset RESET_AUDIO>; 59372401efSJerome Brunet}; 60