1*f95cad74SMaxime Ripard# SPDX-License-Identifier: GPL-2.0 2*f95cad74SMaxime Ripard%YAML 1.2 3*f95cad74SMaxime Ripard--- 4*f95cad74SMaxime Ripard$id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml# 5*f95cad74SMaxime Ripard$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f95cad74SMaxime Ripard 7*f95cad74SMaxime Ripardtitle: Allwinner A10 Bus Gates Clock Device Tree Bindings 8*f95cad74SMaxime Ripard 9*f95cad74SMaxime Ripardmaintainers: 10*f95cad74SMaxime Ripard - Chen-Yu Tsai <wens@csie.org> 11*f95cad74SMaxime Ripard - Maxime Ripard <mripard@kernel.org> 12*f95cad74SMaxime Ripard 13*f95cad74SMaxime Riparddeprecated: true 14*f95cad74SMaxime Ripard 15*f95cad74SMaxime Ripardproperties: 16*f95cad74SMaxime Ripard "#clock-cells": 17*f95cad74SMaxime Ripard const: 1 18*f95cad74SMaxime Ripard description: > 19*f95cad74SMaxime Ripard This additional argument passed to that clock is the offset of 20*f95cad74SMaxime Ripard the bit controlling this particular gate in the register. 21*f95cad74SMaxime Ripard 22*f95cad74SMaxime Ripard compatible: 23*f95cad74SMaxime Ripard const: allwinner,sun8i-h3-bus-gates-clk 24*f95cad74SMaxime Ripard 25*f95cad74SMaxime Ripard reg: 26*f95cad74SMaxime Ripard maxItems: 1 27*f95cad74SMaxime Ripard 28*f95cad74SMaxime Ripard clocks: 29*f95cad74SMaxime Ripard maxItems: 4 30*f95cad74SMaxime Ripard 31*f95cad74SMaxime Ripard clock-names: 32*f95cad74SMaxime Ripard maxItems: 4 33*f95cad74SMaxime Ripard description: > 34*f95cad74SMaxime Ripard The parent order must match the hardware programming order. 35*f95cad74SMaxime Ripard 36*f95cad74SMaxime Ripard clock-indices: 37*f95cad74SMaxime Ripard minItems: 1 38*f95cad74SMaxime Ripard maxItems: 64 39*f95cad74SMaxime Ripard 40*f95cad74SMaxime Ripard clock-output-names: 41*f95cad74SMaxime Ripard minItems: 1 42*f95cad74SMaxime Ripard maxItems: 64 43*f95cad74SMaxime Ripard 44*f95cad74SMaxime Ripardrequired: 45*f95cad74SMaxime Ripard - "#clock-cells" 46*f95cad74SMaxime Ripard - compatible 47*f95cad74SMaxime Ripard - reg 48*f95cad74SMaxime Ripard - clocks 49*f95cad74SMaxime Ripard - clock-indices 50*f95cad74SMaxime Ripard - clock-names 51*f95cad74SMaxime Ripard - clock-output-names 52*f95cad74SMaxime Ripard 53*f95cad74SMaxime RipardadditionalProperties: false 54*f95cad74SMaxime Ripard 55*f95cad74SMaxime Ripardexamples: 56*f95cad74SMaxime Ripard - | 57*f95cad74SMaxime Ripard clk@1c20060 { 58*f95cad74SMaxime Ripard #clock-cells = <1>; 59*f95cad74SMaxime Ripard compatible = "allwinner,sun8i-h3-bus-gates-clk"; 60*f95cad74SMaxime Ripard reg = <0x01c20060 0x14>; 61*f95cad74SMaxime Ripard clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; 62*f95cad74SMaxime Ripard clock-names = "ahb1", "ahb2", "apb1", "apb2"; 63*f95cad74SMaxime Ripard clock-indices = <5>, <6>, <8>, 64*f95cad74SMaxime Ripard <9>, <10>, <13>, 65*f95cad74SMaxime Ripard <14>, <17>, <18>, 66*f95cad74SMaxime Ripard <19>, <20>, 67*f95cad74SMaxime Ripard <21>, <23>, 68*f95cad74SMaxime Ripard <24>, <25>, 69*f95cad74SMaxime Ripard <26>, <27>, 70*f95cad74SMaxime Ripard <28>, <29>, 71*f95cad74SMaxime Ripard <30>, <31>, <32>, 72*f95cad74SMaxime Ripard <35>, <36>, <37>, 73*f95cad74SMaxime Ripard <40>, <41>, <43>, 74*f95cad74SMaxime Ripard <44>, <52>, <53>, 75*f95cad74SMaxime Ripard <54>, <64>, 76*f95cad74SMaxime Ripard <65>, <69>, <72>, 77*f95cad74SMaxime Ripard <76>, <77>, <78>, 78*f95cad74SMaxime Ripard <96>, <97>, <98>, 79*f95cad74SMaxime Ripard <112>, <113>, 80*f95cad74SMaxime Ripard <114>, <115>, 81*f95cad74SMaxime Ripard <116>, <128>, <135>; 82*f95cad74SMaxime Ripard clock-output-names = "bus_ce", "bus_dma", "bus_mmc0", 83*f95cad74SMaxime Ripard "bus_mmc1", "bus_mmc2", "bus_nand", 84*f95cad74SMaxime Ripard "bus_sdram", "bus_gmac", "bus_ts", 85*f95cad74SMaxime Ripard "bus_hstimer", "bus_spi0", 86*f95cad74SMaxime Ripard "bus_spi1", "bus_otg", 87*f95cad74SMaxime Ripard "bus_otg_ehci0", "bus_ehci1", 88*f95cad74SMaxime Ripard "bus_ehci2", "bus_ehci3", 89*f95cad74SMaxime Ripard "bus_otg_ohci0", "bus_ohci1", 90*f95cad74SMaxime Ripard "bus_ohci2", "bus_ohci3", "bus_ve", 91*f95cad74SMaxime Ripard "bus_lcd0", "bus_lcd1", "bus_deint", 92*f95cad74SMaxime Ripard "bus_csi", "bus_tve", "bus_hdmi", 93*f95cad74SMaxime Ripard "bus_de", "bus_gpu", "bus_msgbox", 94*f95cad74SMaxime Ripard "bus_spinlock", "bus_codec", 95*f95cad74SMaxime Ripard "bus_spdif", "bus_pio", "bus_ths", 96*f95cad74SMaxime Ripard "bus_i2s0", "bus_i2s1", "bus_i2s2", 97*f95cad74SMaxime Ripard "bus_i2c0", "bus_i2c1", "bus_i2c2", 98*f95cad74SMaxime Ripard "bus_uart0", "bus_uart1", 99*f95cad74SMaxime Ripard "bus_uart2", "bus_uart3", 100*f95cad74SMaxime Ripard "bus_scr", "bus_ephy", "bus_dbg"; 101*f95cad74SMaxime Ripard }; 102*f95cad74SMaxime Ripard 103*f95cad74SMaxime Ripard... 104