1f95cad74SMaxime Ripard# SPDX-License-Identifier: GPL-2.0 2f95cad74SMaxime Ripard%YAML 1.2 3f95cad74SMaxime Ripard--- 4f95cad74SMaxime Ripard$id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml# 5f95cad74SMaxime Ripard$schema: http://devicetree.org/meta-schemas/core.yaml# 6f95cad74SMaxime Ripard 7*dd3cb467SAndrew Lunntitle: Allwinner A10 Bus Gates Clock 8f95cad74SMaxime Ripard 9f95cad74SMaxime Ripardmaintainers: 10f95cad74SMaxime Ripard - Chen-Yu Tsai <wens@csie.org> 11f95cad74SMaxime Ripard - Maxime Ripard <mripard@kernel.org> 12f95cad74SMaxime Ripard 13f95cad74SMaxime Riparddeprecated: true 14f95cad74SMaxime Ripard 15f95cad74SMaxime Ripardproperties: 16f95cad74SMaxime Ripard "#clock-cells": 17f95cad74SMaxime Ripard const: 1 18f95cad74SMaxime Ripard description: > 19f95cad74SMaxime Ripard This additional argument passed to that clock is the offset of 20f95cad74SMaxime Ripard the bit controlling this particular gate in the register. 21f95cad74SMaxime Ripard 22f95cad74SMaxime Ripard compatible: 23f95cad74SMaxime Ripard const: allwinner,sun8i-h3-bus-gates-clk 24f95cad74SMaxime Ripard 25f95cad74SMaxime Ripard reg: 26f95cad74SMaxime Ripard maxItems: 1 27f95cad74SMaxime Ripard 28f95cad74SMaxime Ripard clocks: 29f95cad74SMaxime Ripard maxItems: 4 30f95cad74SMaxime Ripard 31f95cad74SMaxime Ripard clock-names: 32f95cad74SMaxime Ripard maxItems: 4 33f95cad74SMaxime Ripard description: > 34f95cad74SMaxime Ripard The parent order must match the hardware programming order. 35f95cad74SMaxime Ripard 36f95cad74SMaxime Ripard clock-indices: 37f95cad74SMaxime Ripard minItems: 1 38f95cad74SMaxime Ripard maxItems: 64 39f95cad74SMaxime Ripard 40f95cad74SMaxime Ripard clock-output-names: 41f95cad74SMaxime Ripard minItems: 1 42f95cad74SMaxime Ripard maxItems: 64 43f95cad74SMaxime Ripard 44f95cad74SMaxime Ripardrequired: 45f95cad74SMaxime Ripard - "#clock-cells" 46f95cad74SMaxime Ripard - compatible 47f95cad74SMaxime Ripard - reg 48f95cad74SMaxime Ripard - clocks 49f95cad74SMaxime Ripard - clock-indices 50f95cad74SMaxime Ripard - clock-names 51f95cad74SMaxime Ripard - clock-output-names 52f95cad74SMaxime Ripard 53f95cad74SMaxime RipardadditionalProperties: false 54f95cad74SMaxime Ripard 55f95cad74SMaxime Ripardexamples: 56f95cad74SMaxime Ripard - | 57f95cad74SMaxime Ripard clk@1c20060 { 58f95cad74SMaxime Ripard #clock-cells = <1>; 59f95cad74SMaxime Ripard compatible = "allwinner,sun8i-h3-bus-gates-clk"; 60f95cad74SMaxime Ripard reg = <0x01c20060 0x14>; 61f95cad74SMaxime Ripard clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; 62f95cad74SMaxime Ripard clock-names = "ahb1", "ahb2", "apb1", "apb2"; 63f95cad74SMaxime Ripard clock-indices = <5>, <6>, <8>, 64f95cad74SMaxime Ripard <9>, <10>, <13>, 65f95cad74SMaxime Ripard <14>, <17>, <18>, 66f95cad74SMaxime Ripard <19>, <20>, 67f95cad74SMaxime Ripard <21>, <23>, 68f95cad74SMaxime Ripard <24>, <25>, 69f95cad74SMaxime Ripard <26>, <27>, 70f95cad74SMaxime Ripard <28>, <29>, 71f95cad74SMaxime Ripard <30>, <31>, <32>, 72f95cad74SMaxime Ripard <35>, <36>, <37>, 73f95cad74SMaxime Ripard <40>, <41>, <43>, 74f95cad74SMaxime Ripard <44>, <52>, <53>, 75f95cad74SMaxime Ripard <54>, <64>, 76f95cad74SMaxime Ripard <65>, <69>, <72>, 77f95cad74SMaxime Ripard <76>, <77>, <78>, 78f95cad74SMaxime Ripard <96>, <97>, <98>, 79f95cad74SMaxime Ripard <112>, <113>, 80f95cad74SMaxime Ripard <114>, <115>, 81f95cad74SMaxime Ripard <116>, <128>, <135>; 82f95cad74SMaxime Ripard clock-output-names = "bus_ce", "bus_dma", "bus_mmc0", 83f95cad74SMaxime Ripard "bus_mmc1", "bus_mmc2", "bus_nand", 84f95cad74SMaxime Ripard "bus_sdram", "bus_gmac", "bus_ts", 85f95cad74SMaxime Ripard "bus_hstimer", "bus_spi0", 86f95cad74SMaxime Ripard "bus_spi1", "bus_otg", 87f95cad74SMaxime Ripard "bus_otg_ehci0", "bus_ehci1", 88f95cad74SMaxime Ripard "bus_ehci2", "bus_ehci3", 89f95cad74SMaxime Ripard "bus_otg_ohci0", "bus_ohci1", 90f95cad74SMaxime Ripard "bus_ohci2", "bus_ohci3", "bus_ve", 91f95cad74SMaxime Ripard "bus_lcd0", "bus_lcd1", "bus_deint", 92f95cad74SMaxime Ripard "bus_csi", "bus_tve", "bus_hdmi", 93f95cad74SMaxime Ripard "bus_de", "bus_gpu", "bus_msgbox", 94f95cad74SMaxime Ripard "bus_spinlock", "bus_codec", 95f95cad74SMaxime Ripard "bus_spdif", "bus_pio", "bus_ths", 96f95cad74SMaxime Ripard "bus_i2s0", "bus_i2s1", "bus_i2s2", 97f95cad74SMaxime Ripard "bus_i2c0", "bus_i2c1", "bus_i2c2", 98f95cad74SMaxime Ripard "bus_uart0", "bus_uart1", 99f95cad74SMaxime Ripard "bus_uart2", "bus_uart3", 100f95cad74SMaxime Ripard "bus_scr", "bus_ephy", "bus_dbg"; 101f95cad74SMaxime Ripard }; 102f95cad74SMaxime Ripard 103f95cad74SMaxime Ripard... 104