1*f95cad74SMaxime Ripard# SPDX-License-Identifier: GPL-2.0 2*f95cad74SMaxime Ripard%YAML 1.2 3*f95cad74SMaxime Ripard--- 4*f95cad74SMaxime Ripard$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml# 5*f95cad74SMaxime Ripard$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f95cad74SMaxime Ripard 7*f95cad74SMaxime Ripardtitle: Allwinner A10 DRAM PLL Device Tree Bindings 8*f95cad74SMaxime Ripard 9*f95cad74SMaxime Ripardmaintainers: 10*f95cad74SMaxime Ripard - Chen-Yu Tsai <wens@csie.org> 11*f95cad74SMaxime Ripard - Maxime Ripard <mripard@kernel.org> 12*f95cad74SMaxime Ripard 13*f95cad74SMaxime Riparddeprecated: true 14*f95cad74SMaxime Ripard 15*f95cad74SMaxime Ripardproperties: 16*f95cad74SMaxime Ripard "#clock-cells": 17*f95cad74SMaxime Ripard const: 1 18*f95cad74SMaxime Ripard description: > 19*f95cad74SMaxime Ripard The first output is the DRAM clock output, the second is meant 20*f95cad74SMaxime Ripard for peripherals on the SoC. 21*f95cad74SMaxime Ripard 22*f95cad74SMaxime Ripard compatible: 23*f95cad74SMaxime Ripard const: allwinner,sun4i-a10-pll5-clk 24*f95cad74SMaxime Ripard 25*f95cad74SMaxime Ripard reg: 26*f95cad74SMaxime Ripard maxItems: 1 27*f95cad74SMaxime Ripard 28*f95cad74SMaxime Ripard clocks: 29*f95cad74SMaxime Ripard maxItems: 1 30*f95cad74SMaxime Ripard 31*f95cad74SMaxime Ripard clock-output-names: 32*f95cad74SMaxime Ripard maxItems: 2 33*f95cad74SMaxime Ripard 34*f95cad74SMaxime Ripardrequired: 35*f95cad74SMaxime Ripard - "#clock-cells" 36*f95cad74SMaxime Ripard - compatible 37*f95cad74SMaxime Ripard - reg 38*f95cad74SMaxime Ripard - clocks 39*f95cad74SMaxime Ripard - clock-output-names 40*f95cad74SMaxime Ripard 41*f95cad74SMaxime RipardadditionalProperties: false 42*f95cad74SMaxime Ripard 43*f95cad74SMaxime Ripardexamples: 44*f95cad74SMaxime Ripard - | 45*f95cad74SMaxime Ripard clk@1c20020 { 46*f95cad74SMaxime Ripard #clock-cells = <1>; 47*f95cad74SMaxime Ripard compatible = "allwinner,sun4i-a10-pll5-clk"; 48*f95cad74SMaxime Ripard reg = <0x01c20020 0x4>; 49*f95cad74SMaxime Ripard clocks = <&osc24M>; 50*f95cad74SMaxime Ripard clock-output-names = "pll5_ddr", "pll5_other"; 51*f95cad74SMaxime Ripard }; 52*f95cad74SMaxime Ripard 53*f95cad74SMaxime Ripard... 54