1*f95cad74SMaxime Ripard# SPDX-License-Identifier: GPL-2.0 2*f95cad74SMaxime Ripard%YAML 1.2 3*f95cad74SMaxime Ripard--- 4*f95cad74SMaxime Ripard$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml# 5*f95cad74SMaxime Ripard$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f95cad74SMaxime Ripard 7*f95cad74SMaxime Ripardtitle: Allwinner A10 Bus Gates Clock Device Tree Bindings 8*f95cad74SMaxime Ripard 9*f95cad74SMaxime Ripardmaintainers: 10*f95cad74SMaxime Ripard - Chen-Yu Tsai <wens@csie.org> 11*f95cad74SMaxime Ripard - Maxime Ripard <mripard@kernel.org> 12*f95cad74SMaxime Ripard 13*f95cad74SMaxime Riparddeprecated: true 14*f95cad74SMaxime Ripard 15*f95cad74SMaxime Ripardproperties: 16*f95cad74SMaxime Ripard "#clock-cells": 17*f95cad74SMaxime Ripard const: 1 18*f95cad74SMaxime Ripard description: > 19*f95cad74SMaxime Ripard This additional argument passed to that clock is the offset of 20*f95cad74SMaxime Ripard the bit controlling this particular gate in the register. 21*f95cad74SMaxime Ripard 22*f95cad74SMaxime Ripard compatible: 23*f95cad74SMaxime Ripard oneOf: 24*f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-gates-clk 25*f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-axi-gates-clk 26*f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-ahb-gates-clk 27*f95cad74SMaxime Ripard - const: allwinner,sun5i-a10s-ahb-gates-clk 28*f95cad74SMaxime Ripard - const: allwinner,sun5i-a13-ahb-gates-clk 29*f95cad74SMaxime Ripard - const: allwinner,sun7i-a20-ahb-gates-clk 30*f95cad74SMaxime Ripard - const: allwinner,sun6i-a31-ahb1-gates-clk 31*f95cad74SMaxime Ripard - const: allwinner,sun8i-a23-ahb1-gates-clk 32*f95cad74SMaxime Ripard - const: allwinner,sun9i-a80-ahb0-gates-clk 33*f95cad74SMaxime Ripard - const: allwinner,sun9i-a80-ahb1-gates-clk 34*f95cad74SMaxime Ripard - const: allwinner,sun9i-a80-ahb2-gates-clk 35*f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-apb0-gates-clk 36*f95cad74SMaxime Ripard - const: allwinner,sun5i-a10s-apb0-gates-clk 37*f95cad74SMaxime Ripard - const: allwinner,sun5i-a13-apb0-gates-clk 38*f95cad74SMaxime Ripard - const: allwinner,sun7i-a20-apb0-gates-clk 39*f95cad74SMaxime Ripard - const: allwinner,sun9i-a80-apb0-gates-clk 40*f95cad74SMaxime Ripard - const: allwinner,sun8i-a83t-apb0-gates-clk 41*f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-apb1-gates-clk 42*f95cad74SMaxime Ripard - const: allwinner,sun5i-a13-apb1-gates-clk 43*f95cad74SMaxime Ripard - const: allwinner,sun5i-a10s-apb1-gates-clk 44*f95cad74SMaxime Ripard - const: allwinner,sun6i-a31-apb1-gates-clk 45*f95cad74SMaxime Ripard - const: allwinner,sun7i-a20-apb1-gates-clk 46*f95cad74SMaxime Ripard - const: allwinner,sun8i-a23-apb1-gates-clk 47*f95cad74SMaxime Ripard - const: allwinner,sun9i-a80-apb1-gates-clk 48*f95cad74SMaxime Ripard - const: allwinner,sun6i-a31-apb2-gates-clk 49*f95cad74SMaxime Ripard - const: allwinner,sun8i-a23-apb2-gates-clk 50*f95cad74SMaxime Ripard - const: allwinner,sun8i-a83t-bus-gates-clk 51*f95cad74SMaxime Ripard - const: allwinner,sun9i-a80-apbs-gates-clk 52*f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-dram-gates-clk 53*f95cad74SMaxime Ripard 54*f95cad74SMaxime Ripard - items: 55*f95cad74SMaxime Ripard - const: allwinner,sun5i-a13-dram-gates-clk 56*f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-gates-clk 57*f95cad74SMaxime Ripard 58*f95cad74SMaxime Ripard - items: 59*f95cad74SMaxime Ripard - const: allwinner,sun8i-h3-apb0-gates-clk 60*f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-gates-clk 61*f95cad74SMaxime Ripard 62*f95cad74SMaxime Ripard reg: 63*f95cad74SMaxime Ripard maxItems: 1 64*f95cad74SMaxime Ripard 65*f95cad74SMaxime Ripard clocks: 66*f95cad74SMaxime Ripard maxItems: 1 67*f95cad74SMaxime Ripard 68*f95cad74SMaxime Ripard clock-indices: 69*f95cad74SMaxime Ripard minItems: 1 70*f95cad74SMaxime Ripard maxItems: 64 71*f95cad74SMaxime Ripard 72*f95cad74SMaxime Ripard clock-output-names: 73*f95cad74SMaxime Ripard minItems: 1 74*f95cad74SMaxime Ripard maxItems: 64 75*f95cad74SMaxime Ripard 76*f95cad74SMaxime Ripardrequired: 77*f95cad74SMaxime Ripard - "#clock-cells" 78*f95cad74SMaxime Ripard - compatible 79*f95cad74SMaxime Ripard - reg 80*f95cad74SMaxime Ripard - clocks 81*f95cad74SMaxime Ripard - clock-indices 82*f95cad74SMaxime Ripard - clock-output-names 83*f95cad74SMaxime Ripard 84*f95cad74SMaxime RipardadditionalProperties: false 85*f95cad74SMaxime Ripard 86*f95cad74SMaxime Ripardexamples: 87*f95cad74SMaxime Ripard - | 88*f95cad74SMaxime Ripard clk@1c2005c { 89*f95cad74SMaxime Ripard #clock-cells = <1>; 90*f95cad74SMaxime Ripard compatible = "allwinner,sun4i-a10-axi-gates-clk"; 91*f95cad74SMaxime Ripard reg = <0x01c2005c 0x4>; 92*f95cad74SMaxime Ripard clocks = <&axi>; 93*f95cad74SMaxime Ripard clock-indices = <0>; 94*f95cad74SMaxime Ripard clock-output-names = "axi_dram"; 95*f95cad74SMaxime Ripard }; 96*f95cad74SMaxime Ripard 97*f95cad74SMaxime Ripard - | 98*f95cad74SMaxime Ripard clk@1c20060 { 99*f95cad74SMaxime Ripard #clock-cells = <1>; 100*f95cad74SMaxime Ripard compatible = "allwinner,sun4i-a10-ahb-gates-clk"; 101*f95cad74SMaxime Ripard reg = <0x01c20060 0x8>; 102*f95cad74SMaxime Ripard clocks = <&ahb>; 103*f95cad74SMaxime Ripard clock-indices = <0>, <1>, 104*f95cad74SMaxime Ripard <2>, <3>, 105*f95cad74SMaxime Ripard <4>, <5>, <6>, 106*f95cad74SMaxime Ripard <7>, <8>, <9>, 107*f95cad74SMaxime Ripard <10>, <11>, <12>, 108*f95cad74SMaxime Ripard <13>, <14>, <16>, 109*f95cad74SMaxime Ripard <17>, <18>, <20>, 110*f95cad74SMaxime Ripard <21>, <22>, <23>, 111*f95cad74SMaxime Ripard <24>, <25>, <26>, 112*f95cad74SMaxime Ripard <32>, <33>, <34>, 113*f95cad74SMaxime Ripard <35>, <36>, <37>, 114*f95cad74SMaxime Ripard <40>, <41>, <43>, 115*f95cad74SMaxime Ripard <44>, <45>, 116*f95cad74SMaxime Ripard <46>, <47>, 117*f95cad74SMaxime Ripard <50>, <52>; 118*f95cad74SMaxime Ripard clock-output-names = "ahb_usb0", "ahb_ehci0", 119*f95cad74SMaxime Ripard "ahb_ohci0", "ahb_ehci1", 120*f95cad74SMaxime Ripard "ahb_ohci1", "ahb_ss", "ahb_dma", 121*f95cad74SMaxime Ripard "ahb_bist", "ahb_mmc0", "ahb_mmc1", 122*f95cad74SMaxime Ripard "ahb_mmc2", "ahb_mmc3", "ahb_ms", 123*f95cad74SMaxime Ripard "ahb_nand", "ahb_sdram", "ahb_ace", 124*f95cad74SMaxime Ripard "ahb_emac", "ahb_ts", "ahb_spi0", 125*f95cad74SMaxime Ripard "ahb_spi1", "ahb_spi2", "ahb_spi3", 126*f95cad74SMaxime Ripard "ahb_pata", "ahb_sata", "ahb_gps", 127*f95cad74SMaxime Ripard "ahb_ve", "ahb_tvd", "ahb_tve0", 128*f95cad74SMaxime Ripard "ahb_tve1", "ahb_lcd0", "ahb_lcd1", 129*f95cad74SMaxime Ripard "ahb_csi0", "ahb_csi1", "ahb_hdmi", 130*f95cad74SMaxime Ripard "ahb_de_be0", "ahb_de_be1", 131*f95cad74SMaxime Ripard "ahb_de_fe0", "ahb_de_fe1", 132*f95cad74SMaxime Ripard "ahb_mp", "ahb_mali400"; 133*f95cad74SMaxime Ripard }; 134*f95cad74SMaxime Ripard 135*f95cad74SMaxime Ripard 136*f95cad74SMaxime Ripard - | 137*f95cad74SMaxime Ripard clk@1c20068 { 138*f95cad74SMaxime Ripard #clock-cells = <1>; 139*f95cad74SMaxime Ripard compatible = "allwinner,sun4i-a10-apb0-gates-clk"; 140*f95cad74SMaxime Ripard reg = <0x01c20068 0x4>; 141*f95cad74SMaxime Ripard clocks = <&apb0>; 142*f95cad74SMaxime Ripard clock-indices = <0>, <1>, 143*f95cad74SMaxime Ripard <2>, <3>, 144*f95cad74SMaxime Ripard <5>, <6>, 145*f95cad74SMaxime Ripard <7>, <10>; 146*f95cad74SMaxime Ripard clock-output-names = "apb0_codec", "apb0_spdif", 147*f95cad74SMaxime Ripard "apb0_ac97", "apb0_iis", 148*f95cad74SMaxime Ripard "apb0_pio", "apb0_ir0", 149*f95cad74SMaxime Ripard "apb0_ir1", "apb0_keypad"; 150*f95cad74SMaxime Ripard }; 151*f95cad74SMaxime Ripard 152*f95cad74SMaxime Ripard... 153