1f95cad74SMaxime Ripard# SPDX-License-Identifier: GPL-2.0 2f95cad74SMaxime Ripard%YAML 1.2 3f95cad74SMaxime Ripard--- 4f95cad74SMaxime Ripard$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml# 5f95cad74SMaxime Ripard$schema: http://devicetree.org/meta-schemas/core.yaml# 6f95cad74SMaxime Ripard 7*dd3cb467SAndrew Lunntitle: Allwinner A10 Bus Gates Clock 8f95cad74SMaxime Ripard 9f95cad74SMaxime Ripardmaintainers: 10f95cad74SMaxime Ripard - Chen-Yu Tsai <wens@csie.org> 11f95cad74SMaxime Ripard - Maxime Ripard <mripard@kernel.org> 12f95cad74SMaxime Ripard 13f95cad74SMaxime Riparddeprecated: true 14f95cad74SMaxime Ripard 15f95cad74SMaxime Ripardproperties: 16f95cad74SMaxime Ripard "#clock-cells": 17f95cad74SMaxime Ripard const: 1 18f95cad74SMaxime Ripard description: > 19f95cad74SMaxime Ripard This additional argument passed to that clock is the offset of 20f95cad74SMaxime Ripard the bit controlling this particular gate in the register. 21f95cad74SMaxime Ripard 22f95cad74SMaxime Ripard compatible: 23f95cad74SMaxime Ripard oneOf: 24f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-gates-clk 25f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-axi-gates-clk 26f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-ahb-gates-clk 27f95cad74SMaxime Ripard - const: allwinner,sun5i-a10s-ahb-gates-clk 28f95cad74SMaxime Ripard - const: allwinner,sun5i-a13-ahb-gates-clk 29f95cad74SMaxime Ripard - const: allwinner,sun7i-a20-ahb-gates-clk 30f95cad74SMaxime Ripard - const: allwinner,sun6i-a31-ahb1-gates-clk 31f95cad74SMaxime Ripard - const: allwinner,sun8i-a23-ahb1-gates-clk 32f95cad74SMaxime Ripard - const: allwinner,sun9i-a80-ahb0-gates-clk 33f95cad74SMaxime Ripard - const: allwinner,sun9i-a80-ahb1-gates-clk 34f95cad74SMaxime Ripard - const: allwinner,sun9i-a80-ahb2-gates-clk 35f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-apb0-gates-clk 36f95cad74SMaxime Ripard - const: allwinner,sun5i-a10s-apb0-gates-clk 37f95cad74SMaxime Ripard - const: allwinner,sun5i-a13-apb0-gates-clk 38f95cad74SMaxime Ripard - const: allwinner,sun7i-a20-apb0-gates-clk 39f95cad74SMaxime Ripard - const: allwinner,sun9i-a80-apb0-gates-clk 40f95cad74SMaxime Ripard - const: allwinner,sun8i-a83t-apb0-gates-clk 41f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-apb1-gates-clk 42f95cad74SMaxime Ripard - const: allwinner,sun5i-a13-apb1-gates-clk 43f95cad74SMaxime Ripard - const: allwinner,sun5i-a10s-apb1-gates-clk 44f95cad74SMaxime Ripard - const: allwinner,sun6i-a31-apb1-gates-clk 45f95cad74SMaxime Ripard - const: allwinner,sun7i-a20-apb1-gates-clk 46f95cad74SMaxime Ripard - const: allwinner,sun8i-a23-apb1-gates-clk 47f95cad74SMaxime Ripard - const: allwinner,sun9i-a80-apb1-gates-clk 48f95cad74SMaxime Ripard - const: allwinner,sun6i-a31-apb2-gates-clk 49f95cad74SMaxime Ripard - const: allwinner,sun8i-a23-apb2-gates-clk 50f95cad74SMaxime Ripard - const: allwinner,sun8i-a83t-bus-gates-clk 51f95cad74SMaxime Ripard - const: allwinner,sun9i-a80-apbs-gates-clk 52f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-dram-gates-clk 53f95cad74SMaxime Ripard 54f95cad74SMaxime Ripard - items: 55f95cad74SMaxime Ripard - const: allwinner,sun5i-a13-dram-gates-clk 56f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-gates-clk 57f95cad74SMaxime Ripard 58f95cad74SMaxime Ripard - items: 59f95cad74SMaxime Ripard - const: allwinner,sun8i-h3-apb0-gates-clk 60f95cad74SMaxime Ripard - const: allwinner,sun4i-a10-gates-clk 61f95cad74SMaxime Ripard 62f95cad74SMaxime Ripard reg: 63f95cad74SMaxime Ripard maxItems: 1 64f95cad74SMaxime Ripard 65f95cad74SMaxime Ripard clocks: 66f95cad74SMaxime Ripard maxItems: 1 67f95cad74SMaxime Ripard 68f95cad74SMaxime Ripard clock-indices: 69f95cad74SMaxime Ripard minItems: 1 70f95cad74SMaxime Ripard maxItems: 64 71f95cad74SMaxime Ripard 72f95cad74SMaxime Ripard clock-output-names: 73f95cad74SMaxime Ripard minItems: 1 74f95cad74SMaxime Ripard maxItems: 64 75f95cad74SMaxime Ripard 76f95cad74SMaxime Ripardrequired: 77f95cad74SMaxime Ripard - "#clock-cells" 78f95cad74SMaxime Ripard - compatible 79f95cad74SMaxime Ripard - reg 80f95cad74SMaxime Ripard - clocks 81f95cad74SMaxime Ripard - clock-indices 82f95cad74SMaxime Ripard - clock-output-names 83f95cad74SMaxime Ripard 84f95cad74SMaxime RipardadditionalProperties: false 85f95cad74SMaxime Ripard 86f95cad74SMaxime Ripardexamples: 87f95cad74SMaxime Ripard - | 88f95cad74SMaxime Ripard clk@1c2005c { 89f95cad74SMaxime Ripard #clock-cells = <1>; 90f95cad74SMaxime Ripard compatible = "allwinner,sun4i-a10-axi-gates-clk"; 91f95cad74SMaxime Ripard reg = <0x01c2005c 0x4>; 92f95cad74SMaxime Ripard clocks = <&axi>; 93f95cad74SMaxime Ripard clock-indices = <0>; 94f95cad74SMaxime Ripard clock-output-names = "axi_dram"; 95f95cad74SMaxime Ripard }; 96f95cad74SMaxime Ripard 97f95cad74SMaxime Ripard - | 98f95cad74SMaxime Ripard clk@1c20060 { 99f95cad74SMaxime Ripard #clock-cells = <1>; 100f95cad74SMaxime Ripard compatible = "allwinner,sun4i-a10-ahb-gates-clk"; 101f95cad74SMaxime Ripard reg = <0x01c20060 0x8>; 102f95cad74SMaxime Ripard clocks = <&ahb>; 103f95cad74SMaxime Ripard clock-indices = <0>, <1>, 104f95cad74SMaxime Ripard <2>, <3>, 105f95cad74SMaxime Ripard <4>, <5>, <6>, 106f95cad74SMaxime Ripard <7>, <8>, <9>, 107f95cad74SMaxime Ripard <10>, <11>, <12>, 108f95cad74SMaxime Ripard <13>, <14>, <16>, 109f95cad74SMaxime Ripard <17>, <18>, <20>, 110f95cad74SMaxime Ripard <21>, <22>, <23>, 111f95cad74SMaxime Ripard <24>, <25>, <26>, 112f95cad74SMaxime Ripard <32>, <33>, <34>, 113f95cad74SMaxime Ripard <35>, <36>, <37>, 114f95cad74SMaxime Ripard <40>, <41>, <43>, 115f95cad74SMaxime Ripard <44>, <45>, 116f95cad74SMaxime Ripard <46>, <47>, 117f95cad74SMaxime Ripard <50>, <52>; 118f95cad74SMaxime Ripard clock-output-names = "ahb_usb0", "ahb_ehci0", 119f95cad74SMaxime Ripard "ahb_ohci0", "ahb_ehci1", 120f95cad74SMaxime Ripard "ahb_ohci1", "ahb_ss", "ahb_dma", 121f95cad74SMaxime Ripard "ahb_bist", "ahb_mmc0", "ahb_mmc1", 122f95cad74SMaxime Ripard "ahb_mmc2", "ahb_mmc3", "ahb_ms", 123f95cad74SMaxime Ripard "ahb_nand", "ahb_sdram", "ahb_ace", 124f95cad74SMaxime Ripard "ahb_emac", "ahb_ts", "ahb_spi0", 125f95cad74SMaxime Ripard "ahb_spi1", "ahb_spi2", "ahb_spi3", 126f95cad74SMaxime Ripard "ahb_pata", "ahb_sata", "ahb_gps", 127f95cad74SMaxime Ripard "ahb_ve", "ahb_tvd", "ahb_tve0", 128f95cad74SMaxime Ripard "ahb_tve1", "ahb_lcd0", "ahb_lcd1", 129f95cad74SMaxime Ripard "ahb_csi0", "ahb_csi1", "ahb_hdmi", 130f95cad74SMaxime Ripard "ahb_de_be0", "ahb_de_be1", 131f95cad74SMaxime Ripard "ahb_de_fe0", "ahb_de_fe1", 132f95cad74SMaxime Ripard "ahb_mp", "ahb_mali400"; 133f95cad74SMaxime Ripard }; 134f95cad74SMaxime Ripard 135f95cad74SMaxime Ripard 136f95cad74SMaxime Ripard - | 137f95cad74SMaxime Ripard clk@1c20068 { 138f95cad74SMaxime Ripard #clock-cells = <1>; 139f95cad74SMaxime Ripard compatible = "allwinner,sun4i-a10-apb0-gates-clk"; 140f95cad74SMaxime Ripard reg = <0x01c20068 0x4>; 141f95cad74SMaxime Ripard clocks = <&apb0>; 142f95cad74SMaxime Ripard clock-indices = <0>, <1>, 143f95cad74SMaxime Ripard <2>, <3>, 144f95cad74SMaxime Ripard <5>, <6>, 145f95cad74SMaxime Ripard <7>, <10>; 146f95cad74SMaxime Ripard clock-output-names = "apb0_codec", "apb0_spdif", 147f95cad74SMaxime Ripard "apb0_ac97", "apb0_iis", 148f95cad74SMaxime Ripard "apb0_pio", "apb0_ir0", 149f95cad74SMaxime Ripard "apb0_ir1", "apb0_keypad"; 150f95cad74SMaxime Ripard }; 151f95cad74SMaxime Ripard 152f95cad74SMaxime Ripard... 153