1 *3e7bf468SLad Prabhakar# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 *3e7bf468SLad Prabhakar# Copyright (C) 2023 Renesas Electronics Corp. 3 *3e7bf468SLad Prabhakar%YAML 1.2 4 *3e7bf468SLad Prabhakar--- 5 *3e7bf468SLad Prabhakar$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# 6 *3e7bf468SLad Prabhakar$schema: http://devicetree.org/meta-schemas/core.yaml# 7 *3e7bf468SLad Prabhakar 8 *3e7bf468SLad Prabhakartitle: Andestech AX45MP L2 Cache Controller 9 *3e7bf468SLad Prabhakar 10 *3e7bf468SLad Prabhakarmaintainers: 11 *3e7bf468SLad Prabhakar - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 12 *3e7bf468SLad Prabhakar 13 *3e7bf468SLad Prabhakardescription: 14 *3e7bf468SLad Prabhakar A level-2 cache (L2C) is used to improve the system performance by providing 15 *3e7bf468SLad Prabhakar a large amount of cache line entries and reasonable access delays. The L2C 16 *3e7bf468SLad Prabhakar is shared between cores, and a non-inclusive non-exclusive policy is used. 17 *3e7bf468SLad Prabhakar 18 *3e7bf468SLad Prabhakarselect: 19 *3e7bf468SLad Prabhakar properties: 20 *3e7bf468SLad Prabhakar compatible: 21 *3e7bf468SLad Prabhakar contains: 22 *3e7bf468SLad Prabhakar enum: 23 *3e7bf468SLad Prabhakar - andestech,ax45mp-cache 24 *3e7bf468SLad Prabhakar 25 *3e7bf468SLad Prabhakar required: 26 *3e7bf468SLad Prabhakar - compatible 27 *3e7bf468SLad Prabhakar 28 *3e7bf468SLad Prabhakarproperties: 29 *3e7bf468SLad Prabhakar compatible: 30 *3e7bf468SLad Prabhakar items: 31 *3e7bf468SLad Prabhakar - const: andestech,ax45mp-cache 32 *3e7bf468SLad Prabhakar - const: cache 33 *3e7bf468SLad Prabhakar 34 *3e7bf468SLad Prabhakar reg: 35 *3e7bf468SLad Prabhakar maxItems: 1 36 *3e7bf468SLad Prabhakar 37 *3e7bf468SLad Prabhakar interrupts: 38 *3e7bf468SLad Prabhakar maxItems: 1 39 *3e7bf468SLad Prabhakar 40 *3e7bf468SLad Prabhakar cache-line-size: 41 *3e7bf468SLad Prabhakar const: 64 42 *3e7bf468SLad Prabhakar 43 *3e7bf468SLad Prabhakar cache-level: 44 *3e7bf468SLad Prabhakar const: 2 45 *3e7bf468SLad Prabhakar 46 *3e7bf468SLad Prabhakar cache-sets: 47 *3e7bf468SLad Prabhakar const: 1024 48 *3e7bf468SLad Prabhakar 49 *3e7bf468SLad Prabhakar cache-size: 50 *3e7bf468SLad Prabhakar enum: [131072, 262144, 524288, 1048576, 2097152] 51 *3e7bf468SLad Prabhakar 52 *3e7bf468SLad Prabhakar cache-unified: true 53 *3e7bf468SLad Prabhakar 54 *3e7bf468SLad Prabhakar next-level-cache: true 55 *3e7bf468SLad Prabhakar 56 *3e7bf468SLad PrabhakaradditionalProperties: false 57 *3e7bf468SLad Prabhakar 58 *3e7bf468SLad Prabhakarrequired: 59 *3e7bf468SLad Prabhakar - compatible 60 *3e7bf468SLad Prabhakar - reg 61 *3e7bf468SLad Prabhakar - interrupts 62 *3e7bf468SLad Prabhakar - cache-line-size 63 *3e7bf468SLad Prabhakar - cache-level 64 *3e7bf468SLad Prabhakar - cache-sets 65 *3e7bf468SLad Prabhakar - cache-size 66 *3e7bf468SLad Prabhakar - cache-unified 67 *3e7bf468SLad Prabhakar 68 *3e7bf468SLad Prabhakarexamples: 69 *3e7bf468SLad Prabhakar - | 70 *3e7bf468SLad Prabhakar #include <dt-bindings/interrupt-controller/irq.h> 71 *3e7bf468SLad Prabhakar 72 *3e7bf468SLad Prabhakar cache-controller@2010000 { 73 *3e7bf468SLad Prabhakar compatible = "andestech,ax45mp-cache", "cache"; 74 *3e7bf468SLad Prabhakar reg = <0x13400000 0x100000>; 75 *3e7bf468SLad Prabhakar interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; 76 *3e7bf468SLad Prabhakar cache-line-size = <64>; 77 *3e7bf468SLad Prabhakar cache-level = <2>; 78 *3e7bf468SLad Prabhakar cache-sets = <1024>; 79 *3e7bf468SLad Prabhakar cache-size = <262144>; 80 *3e7bf468SLad Prabhakar cache-unified; 81 *3e7bf468SLad Prabhakar }; 82