1*808ecf4aSSean WangMediaTek SSUSBSYS controller 2*808ecf4aSSean Wang============================ 3*808ecf4aSSean Wang 4*808ecf4aSSean WangThe MediaTek SSUSBSYS controller provides various clocks to the system. 5*808ecf4aSSean Wang 6*808ecf4aSSean WangRequired Properties: 7*808ecf4aSSean Wang 8*808ecf4aSSean Wang- compatible: Should be: 9*808ecf4aSSean Wang - "mediatek,mt7622-ssusbsys", "syscon" 10*808ecf4aSSean Wang- #clock-cells: Must be 1 11*808ecf4aSSean Wang 12*808ecf4aSSean WangThe SSUSBSYS controller uses the common clk binding from 13*808ecf4aSSean WangDocumentation/devicetree/bindings/clock/clock-bindings.txt 14*808ecf4aSSean WangThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 15*808ecf4aSSean Wang 16*808ecf4aSSean WangExample: 17*808ecf4aSSean Wang 18*808ecf4aSSean Wangssusbsys: ssusbsys@1a000000 { 19*808ecf4aSSean Wang compatible = "mediatek,mt7622-ssusbsys", "syscon"; 20*808ecf4aSSean Wang reg = <0 0x1a000000 0 0x1000>; 21*808ecf4aSSean Wang #clock-cells = <1>; 22*808ecf4aSSean Wang}; 23