1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs bindings 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through 14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 15 defining properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: | 45 Usage and definition depend on ARM architecture version and 46 configuration: 47 48 On uniprocessor ARM architectures previous to v7 49 this property is required and must be set to 0. 50 51 On ARM 11 MPcore based systems this property is 52 required and matches the CPUID[11:0] register bits. 53 54 Bits [11:0] in the reg cell must be set to 55 bits [11:0] in CPU ID register. 56 57 All other bits in the reg cell must be set to 0. 58 59 On 32-bit ARM v7 or later systems this property is 60 required and matches the CPU MPIDR[23:0] register 61 bits. 62 63 Bits [23:0] in the reg cell must be set to 64 bits [23:0] in MPIDR. 65 66 All other bits in the reg cell must be set to 0. 67 68 On ARM v8 64-bit systems this property is required 69 and matches the MPIDR_EL1 register affinity bits. 70 71 * If cpus node's #address-cells property is set to 2 72 73 The first reg cell bits [7:0] must be set to 74 bits [39:32] of MPIDR_EL1. 75 76 The second reg cell bits [23:0] must be set to 77 bits [23:0] of MPIDR_EL1. 78 79 * If cpus node's #address-cells property is set to 1 80 81 The reg cell bits [23:0] must be set to bits [23:0] 82 of MPIDR_EL1. 83 84 All other bits in the reg cells must be set to 0. 85 86 compatible: 87 enum: 88 - apple,icestorm 89 - apple,firestorm 90 - arm,arm710t 91 - arm,arm720t 92 - arm,arm740t 93 - arm,arm7ej-s 94 - arm,arm7tdmi 95 - arm,arm7tdmi-s 96 - arm,arm9es 97 - arm,arm9ej-s 98 - arm,arm920t 99 - arm,arm922t 100 - arm,arm925 101 - arm,arm926e-s 102 - arm,arm926ej-s 103 - arm,arm940t 104 - arm,arm946e-s 105 - arm,arm966e-s 106 - arm,arm968e-s 107 - arm,arm9tdmi 108 - arm,arm1020e 109 - arm,arm1020t 110 - arm,arm1022e 111 - arm,arm1026ej-s 112 - arm,arm1136j-s 113 - arm,arm1136jf-s 114 - arm,arm1156t2-s 115 - arm,arm1156t2f-s 116 - arm,arm1176jzf 117 - arm,arm1176jz-s 118 - arm,arm1176jzf-s 119 - arm,arm11mpcore 120 - arm,armv8 # Only for s/w models 121 - arm,cortex-a5 122 - arm,cortex-a7 123 - arm,cortex-a8 124 - arm,cortex-a9 125 - arm,cortex-a12 126 - arm,cortex-a15 127 - arm,cortex-a17 128 - arm,cortex-a32 129 - arm,cortex-a34 130 - arm,cortex-a35 131 - arm,cortex-a53 132 - arm,cortex-a55 133 - arm,cortex-a57 134 - arm,cortex-a65 135 - arm,cortex-a72 136 - arm,cortex-a73 137 - arm,cortex-a75 138 - arm,cortex-a76 139 - arm,cortex-a77 140 - arm,cortex-m0 141 - arm,cortex-m0+ 142 - arm,cortex-m1 143 - arm,cortex-m3 144 - arm,cortex-m4 145 - arm,cortex-r4 146 - arm,cortex-r5 147 - arm,cortex-r7 148 - arm,neoverse-e1 149 - arm,neoverse-n1 150 - brcm,brahma-b15 151 - brcm,brahma-b53 152 - brcm,vulcan 153 - cavium,thunder 154 - cavium,thunder2 155 - faraday,fa526 156 - intel,sa110 157 - intel,sa1100 158 - marvell,feroceon 159 - marvell,mohawk 160 - marvell,pj4a 161 - marvell,pj4b 162 - marvell,sheeva-v5 163 - marvell,sheeva-v7 164 - nvidia,tegra132-denver 165 - nvidia,tegra186-denver 166 - nvidia,tegra194-carmel 167 - qcom,krait 168 - qcom,kryo 169 - qcom,kryo260 170 - qcom,kryo280 171 - qcom,kryo385 172 - qcom,kryo468 173 - qcom,kryo485 174 - qcom,kryo685 175 - qcom,scorpion 176 177 enable-method: 178 $ref: '/schemas/types.yaml#/definitions/string' 179 oneOf: 180 # On ARM v8 64-bit this property is required 181 - enum: 182 - psci 183 - spin-table 184 # On ARM 32-bit systems this property is optional 185 - enum: 186 - actions,s500-smp 187 - allwinner,sun6i-a31 188 - allwinner,sun8i-a23 189 - allwinner,sun9i-a80-smp 190 - allwinner,sun8i-a83t-smp 191 - amlogic,meson8-smp 192 - amlogic,meson8b-smp 193 - arm,realview-smp 194 - aspeed,ast2600-smp 195 - brcm,bcm11351-cpu-method 196 - brcm,bcm23550 197 - brcm,bcm2836-smp 198 - brcm,bcm63138 199 - brcm,bcm-nsp-smp 200 - brcm,brahma-b15 201 - marvell,armada-375-smp 202 - marvell,armada-380-smp 203 - marvell,armada-390-smp 204 - marvell,armada-xp-smp 205 - marvell,98dx3236-smp 206 - marvell,mmp3-smp 207 - mediatek,mt6589-smp 208 - mediatek,mt81xx-tz-smp 209 - qcom,gcc-msm8660 210 - qcom,kpss-acc-v1 211 - qcom,kpss-acc-v2 212 - renesas,apmu 213 - renesas,r9a06g032-smp 214 - rockchip,rk3036-smp 215 - rockchip,rk3066-smp 216 - socionext,milbeaut-m10v-smp 217 - ste,dbx500-smp 218 - ti,am3352 219 - ti,am4372 220 221 cpu-release-addr: 222 $ref: '/schemas/types.yaml#/definitions/uint64' 223 224 description: 225 Required for systems that have an "enable-method" 226 property value of "spin-table". 227 On ARM v8 64-bit systems must be a two cell 228 property identifying a 64-bit zero-initialised 229 memory location. 230 231 cpu-idle-states: 232 $ref: '/schemas/types.yaml#/definitions/phandle-array' 233 description: | 234 List of phandles to idle state nodes supported 235 by this cpu (see ./idle-states.yaml). 236 237 capacity-dmips-mhz: 238 description: 239 u32 value representing CPU capacity (see ./cpu-capacity.txt) in 240 DMIPS/MHz, relative to highest capacity-dmips-mhz 241 in the system. 242 243 dynamic-power-coefficient: 244 $ref: '/schemas/types.yaml#/definitions/uint32' 245 description: 246 A u32 value that represents the running time dynamic 247 power coefficient in units of uW/MHz/V^2. The 248 coefficient can either be calculated from power 249 measurements or derived by analysis. 250 251 The dynamic power consumption of the CPU is 252 proportional to the square of the Voltage (V) and 253 the clock frequency (f). The coefficient is used to 254 calculate the dynamic power as below - 255 256 Pdyn = dynamic-power-coefficient * V^2 * f 257 258 where voltage is in V, frequency is in MHz. 259 260 power-domains: 261 $ref: '/schemas/types.yaml#/definitions/phandle-array' 262 description: 263 List of phandles and PM domain specifiers, as defined by bindings of the 264 PM domain provider (see also ../power_domain.txt). 265 266 power-domain-names: 267 $ref: '/schemas/types.yaml#/definitions/string-array' 268 description: 269 A list of power domain name strings sorted in the same order as the 270 power-domains property. 271 272 For PSCI based platforms, the name corresponding to the index of the PSCI 273 PM domain provider, must be "psci". 274 275 qcom,saw: 276 $ref: '/schemas/types.yaml#/definitions/phandle' 277 description: | 278 Specifies the SAW* node associated with this CPU. 279 280 Required for systems that have an "enable-method" property 281 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 282 283 * arm/msm/qcom,saw2.txt 284 285 qcom,acc: 286 $ref: '/schemas/types.yaml#/definitions/phandle' 287 description: | 288 Specifies the ACC* node associated with this CPU. 289 290 Required for systems that have an "enable-method" property 291 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 292 293 * arm/msm/qcom,kpss-acc.txt 294 295 rockchip,pmu: 296 $ref: '/schemas/types.yaml#/definitions/phandle' 297 description: | 298 Specifies the syscon node controlling the cpu core power domains. 299 300 Optional for systems that have an "enable-method" 301 property value of "rockchip,rk3066-smp" 302 While optional, it is the preferred way to get access to 303 the cpu-core power-domains. 304 305 secondary-boot-reg: 306 $ref: '/schemas/types.yaml#/definitions/uint32' 307 description: | 308 Required for systems that have an "enable-method" property value of 309 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 310 311 This includes the following SoCs: | 312 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 313 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 314 315 The secondary-boot-reg property is a u32 value that specifies the 316 physical address of the register used to request the ROM holding pen 317 code release a secondary CPU. The value written to the register is 318 formed by encoding the target CPU id into the low bits of the 319 physical start address it should jump to. 320 321if: 322 # If the enable-method property contains one of those values 323 properties: 324 enable-method: 325 contains: 326 enum: 327 - brcm,bcm11351-cpu-method 328 - brcm,bcm23550 329 - brcm,bcm-nsp-smp 330 # and if enable-method is present 331 required: 332 - enable-method 333 334then: 335 required: 336 - secondary-boot-reg 337 338required: 339 - device_type 340 - reg 341 - compatible 342 343dependencies: 344 rockchip,pmu: [enable-method] 345 346additionalProperties: true 347 348examples: 349 - | 350 cpus { 351 #size-cells = <0>; 352 #address-cells = <1>; 353 354 cpu@0 { 355 device_type = "cpu"; 356 compatible = "arm,cortex-a15"; 357 reg = <0x0>; 358 }; 359 360 cpu@1 { 361 device_type = "cpu"; 362 compatible = "arm,cortex-a15"; 363 reg = <0x1>; 364 }; 365 366 cpu@100 { 367 device_type = "cpu"; 368 compatible = "arm,cortex-a7"; 369 reg = <0x100>; 370 }; 371 372 cpu@101 { 373 device_type = "cpu"; 374 compatible = "arm,cortex-a7"; 375 reg = <0x101>; 376 }; 377 }; 378 379 - | 380 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 381 cpus { 382 #size-cells = <0>; 383 #address-cells = <1>; 384 385 cpu@0 { 386 device_type = "cpu"; 387 compatible = "arm,cortex-a8"; 388 reg = <0x0>; 389 }; 390 }; 391 392 - | 393 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 394 cpus { 395 #size-cells = <0>; 396 #address-cells = <1>; 397 398 cpu@0 { 399 device_type = "cpu"; 400 compatible = "arm,arm926ej-s"; 401 reg = <0x0>; 402 }; 403 }; 404 405 - | 406 // Example 4 (ARM Cortex-A57 64-bit system): 407 cpus { 408 #size-cells = <0>; 409 #address-cells = <2>; 410 411 cpu@0 { 412 device_type = "cpu"; 413 compatible = "arm,cortex-a57"; 414 reg = <0x0 0x0>; 415 enable-method = "spin-table"; 416 cpu-release-addr = <0 0x20000000>; 417 }; 418 419 cpu@1 { 420 device_type = "cpu"; 421 compatible = "arm,cortex-a57"; 422 reg = <0x0 0x1>; 423 enable-method = "spin-table"; 424 cpu-release-addr = <0 0x20000000>; 425 }; 426 427 cpu@100 { 428 device_type = "cpu"; 429 compatible = "arm,cortex-a57"; 430 reg = <0x0 0x100>; 431 enable-method = "spin-table"; 432 cpu-release-addr = <0 0x20000000>; 433 }; 434 435 cpu@101 { 436 device_type = "cpu"; 437 compatible = "arm,cortex-a57"; 438 reg = <0x0 0x101>; 439 enable-method = "spin-table"; 440 cpu-release-addr = <0 0x20000000>; 441 }; 442 443 cpu@10000 { 444 device_type = "cpu"; 445 compatible = "arm,cortex-a57"; 446 reg = <0x0 0x10000>; 447 enable-method = "spin-table"; 448 cpu-release-addr = <0 0x20000000>; 449 }; 450 451 cpu@10001 { 452 device_type = "cpu"; 453 compatible = "arm,cortex-a57"; 454 reg = <0x0 0x10001>; 455 enable-method = "spin-table"; 456 cpu-release-addr = <0 0x20000000>; 457 }; 458 459 cpu@10100 { 460 device_type = "cpu"; 461 compatible = "arm,cortex-a57"; 462 reg = <0x0 0x10100>; 463 enable-method = "spin-table"; 464 cpu-release-addr = <0 0x20000000>; 465 }; 466 467 cpu@10101 { 468 device_type = "cpu"; 469 compatible = "arm,cortex-a57"; 470 reg = <0x0 0x10101>; 471 enable-method = "spin-table"; 472 cpu-release-addr = <0 0x20000000>; 473 }; 474 475 cpu@100000000 { 476 device_type = "cpu"; 477 compatible = "arm,cortex-a57"; 478 reg = <0x1 0x0>; 479 enable-method = "spin-table"; 480 cpu-release-addr = <0 0x20000000>; 481 }; 482 483 cpu@100000001 { 484 device_type = "cpu"; 485 compatible = "arm,cortex-a57"; 486 reg = <0x1 0x1>; 487 enable-method = "spin-table"; 488 cpu-release-addr = <0 0x20000000>; 489 }; 490 491 cpu@100000100 { 492 device_type = "cpu"; 493 compatible = "arm,cortex-a57"; 494 reg = <0x1 0x100>; 495 enable-method = "spin-table"; 496 cpu-release-addr = <0 0x20000000>; 497 }; 498 499 cpu@100000101 { 500 device_type = "cpu"; 501 compatible = "arm,cortex-a57"; 502 reg = <0x1 0x101>; 503 enable-method = "spin-table"; 504 cpu-release-addr = <0 0x20000000>; 505 }; 506 507 cpu@100010000 { 508 device_type = "cpu"; 509 compatible = "arm,cortex-a57"; 510 reg = <0x1 0x10000>; 511 enable-method = "spin-table"; 512 cpu-release-addr = <0 0x20000000>; 513 }; 514 515 cpu@100010001 { 516 device_type = "cpu"; 517 compatible = "arm,cortex-a57"; 518 reg = <0x1 0x10001>; 519 enable-method = "spin-table"; 520 cpu-release-addr = <0 0x20000000>; 521 }; 522 523 cpu@100010100 { 524 device_type = "cpu"; 525 compatible = "arm,cortex-a57"; 526 reg = <0x1 0x10100>; 527 enable-method = "spin-table"; 528 cpu-release-addr = <0 0x20000000>; 529 }; 530 531 cpu@100010101 { 532 device_type = "cpu"; 533 compatible = "arm,cortex-a57"; 534 reg = <0x1 0x10101>; 535 enable-method = "spin-table"; 536 cpu-release-addr = <0 0x20000000>; 537 }; 538 }; 539... 540