160f9e37aSTsahee Zidenberg======================================================== 260f9e37aSTsahee ZidenbergSecondary CPU enable-method "al,alpine-smp" binding 360f9e37aSTsahee Zidenberg======================================================== 460f9e37aSTsahee Zidenberg 560f9e37aSTsahee ZidenbergThis document describes the "al,alpine-smp" method for 660f9e37aSTsahee Zidenbergenabling secondary CPUs. To apply to all CPUs, a single 760f9e37aSTsahee Zidenberg"al,alpine-smp" enable method should be defined in the 860f9e37aSTsahee Zidenberg"cpus" node. 960f9e37aSTsahee Zidenberg 1060f9e37aSTsahee ZidenbergEnable method name: "al,alpine-smp" 1160f9e37aSTsahee ZidenbergCompatible machines: "al,alpine" 1260f9e37aSTsahee ZidenbergCompatible CPUs: "arm,cortex-a15" 1360f9e37aSTsahee ZidenbergRelated properties: (none) 1460f9e37aSTsahee Zidenberg 1560f9e37aSTsahee ZidenbergNote: 1660f9e37aSTsahee ZidenbergThis enable method requires valid nodes compatible with 17*7ac48a81SRob Herring"al,alpine-cpu-resume" and "al,alpine-nb-service". 18*7ac48a81SRob Herring 19*7ac48a81SRob Herring 20*7ac48a81SRob Herring* Alpine CPU resume registers 21*7ac48a81SRob Herring 22*7ac48a81SRob HerringThe CPU resume register are used to define required resume address after 23*7ac48a81SRob Herringreset. 24*7ac48a81SRob Herring 25*7ac48a81SRob HerringProperties: 26*7ac48a81SRob Herring- compatible : Should contain "al,alpine-cpu-resume". 27*7ac48a81SRob Herring- reg : Offset and length of the register set for the device 28*7ac48a81SRob Herring 29*7ac48a81SRob Herring 30*7ac48a81SRob Herring* Alpine System-Fabric Service Registers 31*7ac48a81SRob Herring 32*7ac48a81SRob HerringThe System-Fabric Service Registers allow various operation on CPU and 33*7ac48a81SRob Herringsystem fabric, like powering CPUs off. 34*7ac48a81SRob Herring 35*7ac48a81SRob HerringProperties: 36*7ac48a81SRob Herring- compatible : Should contain "al,alpine-sysfabric-service" and "syscon". 37*7ac48a81SRob Herring- reg : Offset and length of the register set for the device 38*7ac48a81SRob Herring 3960f9e37aSTsahee Zidenberg 4060f9e37aSTsahee ZidenbergExample: 4160f9e37aSTsahee Zidenberg 4260f9e37aSTsahee Zidenbergcpus { 4360f9e37aSTsahee Zidenberg #address-cells = <1>; 4460f9e37aSTsahee Zidenberg #size-cells = <0>; 4560f9e37aSTsahee Zidenberg enable-method = "al,alpine-smp"; 4660f9e37aSTsahee Zidenberg 4760f9e37aSTsahee Zidenberg cpu@0 { 4860f9e37aSTsahee Zidenberg compatible = "arm,cortex-a15"; 4960f9e37aSTsahee Zidenberg device_type = "cpu"; 5060f9e37aSTsahee Zidenberg reg = <0>; 5160f9e37aSTsahee Zidenberg }; 5260f9e37aSTsahee Zidenberg 5360f9e37aSTsahee Zidenberg cpu@1 { 5460f9e37aSTsahee Zidenberg compatible = "arm,cortex-a15"; 5560f9e37aSTsahee Zidenberg device_type = "cpu"; 5660f9e37aSTsahee Zidenberg reg = <1>; 5760f9e37aSTsahee Zidenberg }; 5860f9e37aSTsahee Zidenberg 5960f9e37aSTsahee Zidenberg cpu@2 { 6060f9e37aSTsahee Zidenberg compatible = "arm,cortex-a15"; 6160f9e37aSTsahee Zidenberg device_type = "cpu"; 6260f9e37aSTsahee Zidenberg reg = <2>; 6360f9e37aSTsahee Zidenberg }; 6460f9e37aSTsahee Zidenberg 6560f9e37aSTsahee Zidenberg cpu@3 { 6660f9e37aSTsahee Zidenberg compatible = "arm,cortex-a15"; 6760f9e37aSTsahee Zidenberg device_type = "cpu"; 6860f9e37aSTsahee Zidenberg reg = <3>; 6960f9e37aSTsahee Zidenberg }; 7060f9e37aSTsahee Zidenberg}; 7160f9e37aSTsahee Zidenberg 72*7ac48a81SRob Herringcpu_resume { 73*7ac48a81SRob Herring compatible = "al,alpine-cpu-resume"; 74*7ac48a81SRob Herring reg = <0xfbff5ed0 0x30>; 75*7ac48a81SRob Herring}; 76*7ac48a81SRob Herring 77*7ac48a81SRob Herringnb_service { 78*7ac48a81SRob Herring compatible = "al,alpine-sysfabric-service", "syscon"; 79*7ac48a81SRob Herring reg = <0xfb070000 0x10000>; 80*7ac48a81SRob Herring}; 81