xref: /openbmc/linux/Documentation/arch/arm/memory.rst (revision 2612e3bbc0386368a850140a6c9b990cd496a5ec)
1*e790a4ceSJonathan Corbet=================================
2*e790a4ceSJonathan CorbetKernel Memory Layout on ARM Linux
3*e790a4ceSJonathan Corbet=================================
4*e790a4ceSJonathan Corbet
5*e790a4ceSJonathan Corbet		Russell King <rmk@arm.linux.org.uk>
6*e790a4ceSJonathan Corbet
7*e790a4ceSJonathan Corbet		     November 17, 2005 (2.6.15)
8*e790a4ceSJonathan Corbet
9*e790a4ceSJonathan CorbetThis document describes the virtual memory layout which the Linux
10*e790a4ceSJonathan Corbetkernel uses for ARM processors.  It indicates which regions are
11*e790a4ceSJonathan Corbetfree for platforms to use, and which are used by generic code.
12*e790a4ceSJonathan Corbet
13*e790a4ceSJonathan CorbetThe ARM CPU is capable of addressing a maximum of 4GB virtual memory
14*e790a4ceSJonathan Corbetspace, and this must be shared between user space processes, the
15*e790a4ceSJonathan Corbetkernel, and hardware devices.
16*e790a4ceSJonathan Corbet
17*e790a4ceSJonathan CorbetAs the ARM architecture matures, it becomes necessary to reserve
18*e790a4ceSJonathan Corbetcertain regions of VM space for use for new facilities; therefore
19*e790a4ceSJonathan Corbetthis document may reserve more VM space over time.
20*e790a4ceSJonathan Corbet
21*e790a4ceSJonathan Corbet=============== =============== ===============================================
22*e790a4ceSJonathan CorbetStart		End		Use
23*e790a4ceSJonathan Corbet=============== =============== ===============================================
24*e790a4ceSJonathan Corbetffff8000	ffffffff	copy_user_page / clear_user_page use.
25*e790a4ceSJonathan Corbet				For SA11xx and Xscale, this is used to
26*e790a4ceSJonathan Corbet				setup a minicache mapping.
27*e790a4ceSJonathan Corbet
28*e790a4ceSJonathan Corbetffff4000	ffffffff	cache aliasing on ARMv6 and later CPUs.
29*e790a4ceSJonathan Corbet
30*e790a4ceSJonathan Corbetffff1000	ffff7fff	Reserved.
31*e790a4ceSJonathan Corbet				Platforms must not use this address range.
32*e790a4ceSJonathan Corbet
33*e790a4ceSJonathan Corbetffff0000	ffff0fff	CPU vector page.
34*e790a4ceSJonathan Corbet				The CPU vectors are mapped here if the
35*e790a4ceSJonathan Corbet				CPU supports vector relocation (control
36*e790a4ceSJonathan Corbet				register V bit.)
37*e790a4ceSJonathan Corbet
38*e790a4ceSJonathan Corbetfffe0000	fffeffff	XScale cache flush area.  This is used
39*e790a4ceSJonathan Corbet				in proc-xscale.S to flush the whole data
40*e790a4ceSJonathan Corbet				cache. (XScale does not have TCM.)
41*e790a4ceSJonathan Corbet
42*e790a4ceSJonathan Corbetfffe8000	fffeffff	DTCM mapping area for platforms with
43*e790a4ceSJonathan Corbet				DTCM mounted inside the CPU.
44*e790a4ceSJonathan Corbet
45*e790a4ceSJonathan Corbetfffe0000	fffe7fff	ITCM mapping area for platforms with
46*e790a4ceSJonathan Corbet				ITCM mounted inside the CPU.
47*e790a4ceSJonathan Corbet
48*e790a4ceSJonathan Corbetffc80000	ffefffff	Fixmap mapping region.  Addresses provided
49*e790a4ceSJonathan Corbet				by fix_to_virt() will be located here.
50*e790a4ceSJonathan Corbet
51*e790a4ceSJonathan Corbetffc00000	ffc7ffff	Guard region
52*e790a4ceSJonathan Corbet
53*e790a4ceSJonathan Corbetff800000	ffbfffff	Permanent, fixed read-only mapping of the
54*e790a4ceSJonathan Corbet				firmware provided DT blob
55*e790a4ceSJonathan Corbet
56*e790a4ceSJonathan Corbetfee00000	feffffff	Mapping of PCI I/O space. This is a static
57*e790a4ceSJonathan Corbet				mapping within the vmalloc space.
58*e790a4ceSJonathan Corbet
59*e790a4ceSJonathan CorbetVMALLOC_START	VMALLOC_END-1	vmalloc() / ioremap() space.
60*e790a4ceSJonathan Corbet				Memory returned by vmalloc/ioremap will
61*e790a4ceSJonathan Corbet				be dynamically placed in this region.
62*e790a4ceSJonathan Corbet				Machine specific static mappings are also
63*e790a4ceSJonathan Corbet				located here through iotable_init().
64*e790a4ceSJonathan Corbet				VMALLOC_START is based upon the value
65*e790a4ceSJonathan Corbet				of the high_memory variable, and VMALLOC_END
66*e790a4ceSJonathan Corbet				is equal to 0xff800000.
67*e790a4ceSJonathan Corbet
68*e790a4ceSJonathan CorbetPAGE_OFFSET	high_memory-1	Kernel direct-mapped RAM region.
69*e790a4ceSJonathan Corbet				This maps the platforms RAM, and typically
70*e790a4ceSJonathan Corbet				maps all platform RAM in a 1:1 relationship.
71*e790a4ceSJonathan Corbet
72*e790a4ceSJonathan CorbetPKMAP_BASE	PAGE_OFFSET-1	Permanent kernel mappings
73*e790a4ceSJonathan Corbet				One way of mapping HIGHMEM pages into kernel
74*e790a4ceSJonathan Corbet				space.
75*e790a4ceSJonathan Corbet
76*e790a4ceSJonathan CorbetMODULES_VADDR	MODULES_END-1	Kernel module space
77*e790a4ceSJonathan Corbet				Kernel modules inserted via insmod are
78*e790a4ceSJonathan Corbet				placed here using dynamic mappings.
79*e790a4ceSJonathan Corbet
80*e790a4ceSJonathan CorbetTASK_SIZE	MODULES_VADDR-1	KASAn shadow memory when KASan is in use.
81*e790a4ceSJonathan Corbet				The range from MODULES_VADDR to the top
82*e790a4ceSJonathan Corbet				of the memory is shadowed here with 1 bit
83*e790a4ceSJonathan Corbet				per byte of memory.
84*e790a4ceSJonathan Corbet
85*e790a4ceSJonathan Corbet00001000	TASK_SIZE-1	User space mappings
86*e790a4ceSJonathan Corbet				Per-thread mappings are placed here via
87*e790a4ceSJonathan Corbet				the mmap() system call.
88*e790a4ceSJonathan Corbet
89*e790a4ceSJonathan Corbet00000000	00000fff	CPU vector page / null pointer trap
90*e790a4ceSJonathan Corbet				CPUs which do not support vector remapping
91*e790a4ceSJonathan Corbet				place their vector page here.  NULL pointer
92*e790a4ceSJonathan Corbet				dereferences by both the kernel and user
93*e790a4ceSJonathan Corbet				space are also caught via this mapping.
94*e790a4ceSJonathan Corbet=============== =============== ===============================================
95*e790a4ceSJonathan Corbet
96*e790a4ceSJonathan CorbetPlease note that mappings which collide with the above areas may result
97*e790a4ceSJonathan Corbetin a non-bootable kernel, or may cause the kernel to (eventually) panic
98*e790a4ceSJonathan Corbetat run time.
99*e790a4ceSJonathan Corbet
100*e790a4ceSJonathan CorbetSince future CPUs may impact the kernel mapping layout, user programs
101*e790a4ceSJonathan Corbetmust not access any memory which is not mapped inside their 0x0001000
102*e790a4ceSJonathan Corbetto TASK_SIZE address range.  If they wish to access these areas, they
103*e790a4ceSJonathan Corbetmust set up their own mappings using open() and mmap().
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