1*59809fe8SMauro Carvalho Chehab================================================ 2*59809fe8SMauro Carvalho ChehabAPM X-Gene SoC Performance Monitoring Unit (PMU) 3*59809fe8SMauro Carvalho Chehab================================================ 4*59809fe8SMauro Carvalho Chehab 5*59809fe8SMauro Carvalho ChehabX-Gene SoC PMU consists of various independent system device PMUs such as 6*59809fe8SMauro Carvalho ChehabL3 cache(s), I/O bridge(s), memory controller bridge(s) and memory 7*59809fe8SMauro Carvalho Chehabcontroller(s). These PMU devices are loosely architected to follow the 8*59809fe8SMauro Carvalho Chehabsame model as the PMU for ARM cores. The PMUs share the same top level 9*59809fe8SMauro Carvalho Chehabinterrupt and status CSR region. 10*59809fe8SMauro Carvalho Chehab 11*59809fe8SMauro Carvalho ChehabPMU (perf) driver 12*59809fe8SMauro Carvalho Chehab----------------- 13*59809fe8SMauro Carvalho Chehab 14*59809fe8SMauro Carvalho ChehabThe xgene-pmu driver registers several perf PMU drivers. Each of the perf 15*59809fe8SMauro Carvalho Chehabdriver provides description of its available events and configuration options 16*59809fe8SMauro Carvalho Chehabin sysfs, see /sys/devices/<l3cX/iobX/mcbX/mcX>/. 17*59809fe8SMauro Carvalho Chehab 18*59809fe8SMauro Carvalho ChehabThe "format" directory describes format of the config (event ID), 19*59809fe8SMauro Carvalho Chehabconfig1 (agent ID) fields of the perf_event_attr structure. The "events" 20*59809fe8SMauro Carvalho Chehabdirectory provides configuration templates for all supported event types that 21*59809fe8SMauro Carvalho Chehabcan be used with perf tool. For example, "l3c0/bank-fifo-full/" is an 22*59809fe8SMauro Carvalho Chehabequivalent of "l3c0/config=0x0b/". 23*59809fe8SMauro Carvalho Chehab 24*59809fe8SMauro Carvalho ChehabMost of the SoC PMU has a specific list of agent ID used for monitoring 25*59809fe8SMauro Carvalho Chehabperformance of a specific datapath. For example, agents of a L3 cache can be 26*59809fe8SMauro Carvalho Chehaba specific CPU or an I/O bridge. Each PMU has a set of 2 registers capable of 27*59809fe8SMauro Carvalho Chehabmasking the agents from which the request come from. If the bit with 28*59809fe8SMauro Carvalho Chehabthe bit number corresponding to the agent is set, the event is counted only if 29*59809fe8SMauro Carvalho Chehabit is caused by a request from that agent. Each agent ID bit is inversely mapped 30*59809fe8SMauro Carvalho Chehabto a corresponding bit in "config1" field. By default, the event will be 31*59809fe8SMauro Carvalho Chehabcounted for all agent requests (config1 = 0x0). For all the supported agents of 32*59809fe8SMauro Carvalho Chehabeach PMU, please refer to APM X-Gene User Manual. 33*59809fe8SMauro Carvalho Chehab 34*59809fe8SMauro Carvalho ChehabEach perf driver also provides a "cpumask" sysfs attribute, which contains a 35*59809fe8SMauro Carvalho Chehabsingle CPU ID of the processor which will be used to handle all the PMU events. 36*59809fe8SMauro Carvalho Chehab 37*59809fe8SMauro Carvalho ChehabExample for perf tool use:: 38*59809fe8SMauro Carvalho Chehab 39*59809fe8SMauro Carvalho Chehab / # perf list | grep -e l3c -e iob -e mcb -e mc 40*59809fe8SMauro Carvalho Chehab l3c0/ackq-full/ [Kernel PMU event] 41*59809fe8SMauro Carvalho Chehab <...> 42*59809fe8SMauro Carvalho Chehab mcb1/mcb-csw-stall/ [Kernel PMU event] 43*59809fe8SMauro Carvalho Chehab 44*59809fe8SMauro Carvalho Chehab / # perf stat -a -e l3c0/read-miss/,mcb1/csw-write-request/ sleep 1 45*59809fe8SMauro Carvalho Chehab 46*59809fe8SMauro Carvalho Chehab / # perf stat -a -e l3c0/read-miss,config1=0xfffffffffffffffe/ sleep 1 47*59809fe8SMauro Carvalho Chehab 48*59809fe8SMauro Carvalho ChehabThe driver does not support sampling, therefore "perf record" will 49*59809fe8SMauro Carvalho Chehabnot work. Per-task (without "-a") perf sessions are not supported. 50