1# EEPROM address size detection modes 2 3This document introduces and discusses the different modes to detect how many 4address byte(s) needed for a given EEPROM device. 5 6## MODE-1 7 8The existing upstream function isDevice16Bit() bases on sending 1-byte write 9operation (with a STOP condition) and 8 subsequent 1-byte read operations with 10SINGLE byte address. 11 12### This MODE-1 expects the following logic 13 14- If the device requires 1 address byte, it EXPECTS that the data will be read 15 from a single location so 8 bytes read will be the same. 16- If the device requires 2 address bytes, it EXPECTS that the data will be read 17 from 8 DIFFERENT LOCATIONS and at least one byte read is different than 7 18 other reads. 19 20### Issue and potential issue with this MODE-1 21 22- If any "2 address bytes" EEPROM from any vendor has the same data in all 23 memory locations (0-7) the existing upstream function read, this device will 24 be identified as "1 address byte" device. 25 26- ONSEMI EEPROM (a 2 address bytes device) return the same data from the same 27 single byte address read --> therefore, existing function wrongly identifies 28 it as 1 byte address device. 29 30## MODE-2 31 32The proposal MODE-2 changes to isDevice16Bit() sends 8 instructions of 2-bytes 33write operation (WITHOUT a STOP condition ie. prohibited STOP) followed by a 341-byte read operation. The proposed solution fully complies with IIC standard 35and should be applicable to any IIC EEPROM manufacturer. 36 37```text 38`| Start | SlaveAddr + W | 0x00 | 0x00 | STOP PROHIBITED HERE | Start | SlaveAddr + R | data byte | Stop | 39`|-------|---------------|------|------|----------------------|-------| --------------|-----------|------| 40`| Start | SlaveAddr + W | 0x00 | 0x01 | STOP PROHIBITED HERE | Start | SlaveAddr + R | data byte | Stop | 41`| Start | SlaveAddr + W | 0x00 | 0x02 | STOP PROHIBITED HERE | Start | SlaveAddr + R | data byte | Stop | 42`| Start | SlaveAddr + W | 0x00 | 0x03 | STOP PROHIBITED HERE | Start | SlaveAddr + R | data byte | Stop | 43`| Start | SlaveAddr + W | 0x00 | 0x04 | STOP PROHIBITED HERE | Start | SlaveAddr + R | data byte | Stop | 44`| Start | SlaveAddr + W | 0x00 | 0x05 | STOP PROHIBITED HERE | Start | SlaveAddr + R | data byte | Stop | 45`| Start | SlaveAddr + W | 0x00 | 0x06 | STOP PROHIBITED HERE | Start | SlaveAddr + R | data byte | Stop | 46`| Start | SlaveAddr + W | 0x00 | 0x07 | STOP PROHIBITED HERE | Start | SlaveAddr + R | data byte | Stop | 47``` 48 49- If the device requires a single data byte, then it will always load address 50 0x00, the subsequent read byte will be the same for all 8 instructions. The 51 second byte on the write would be interpreted as data byte, thus not modifying 52 the address pointer. 53 54- If two address bytes are required, then the device will interpret both bytes 55 as addresses, thus reading from different addresses every time, similar with 56 what the existing function is using now. 57 58### Notes & reasons 59 60There is no STOP condition after the second (potential) address byte. A START 61condition must be sent after the second byte. If STOP condition is sent, then 62the 1-byte address devices will start internal write cycle, altering the EEPROM 63content which is not good. 64 65This proposal MODE-2 suffers the same 1st issue as MODE-1 ie. what if the EEPROM 66has the same data at all those addresses. However, this proposal MODE-2 67addresses the 2nd issue of MODE-1 which expects that the data will be read from 688 DIFFERENT LOCATIONS if the device requires 2 address bytes. This expectation 69is the ambiguity (not standard defined) in the IIC specification. 70 71In [IIC specification:](https://www.nxp.com/docs/en/user-guide/UM10204.pdf) 72 73- Section 3.1.10, Note 2 -> 74 `All decisions on auto-increment or decrement of previously accessed memory locations, etc., are taken by the designer of the device.` 75 76 Based on this note, the designer of every EEPROM has the "freedom" to use 77 whatever architecture considers appropriate and suitable to process everyone 78 of the two address bytes. There are no restrictions on this. 79 80 Based on this, the others EEPROM (not ONSEMI EEPROM) auto-increment - observed 81 with one address byte sent instead of two - is a manufacturer-specific 82 behavior, and not standard defined. 83 84- Section 3.1.10, Note 1 -> 85 `Combined formats can be used, for example, to control a serial memory. The internal memory location must be written during the first data byte. After the START condition and slave address is repeated, data can be transferred.` 86 87 This proposal MODE-2 implements this note. The memory location referred herein 88 is the address pointer, as being the first data byte in IIC communication. 89 Based on this note, EEPROM must update this pointer immediately following this 90 first address byte. 91