1*560e6af7SHarshit Aghera /* 2*560e6af7SHarshit Aghera * SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & 3*560e6af7SHarshit Aghera * AFFILIATES. All rights reserved. 4*560e6af7SHarshit Aghera * SPDX-License-Identifier: Apache-2.0 5*560e6af7SHarshit Aghera */ 6*560e6af7SHarshit Aghera 7*560e6af7SHarshit Aghera #pragma once 8*560e6af7SHarshit Aghera 9*560e6af7SHarshit Aghera #include <cstdint> 10*560e6af7SHarshit Aghera #include <span> 11*560e6af7SHarshit Aghera 12*560e6af7SHarshit Aghera namespace ocp 13*560e6af7SHarshit Aghera { 14*560e6af7SHarshit Aghera namespace accelerator_management 15*560e6af7SHarshit Aghera { 16*560e6af7SHarshit Aghera 17*560e6af7SHarshit Aghera constexpr uint8_t messageType = 0x7E; 18*560e6af7SHarshit Aghera 19*560e6af7SHarshit Aghera constexpr uint8_t ocpType = 8; 20*560e6af7SHarshit Aghera constexpr uint8_t ocpVersion = 9; 21*560e6af7SHarshit Aghera constexpr uint8_t ocpTypeBitOffset = 4; 22*560e6af7SHarshit Aghera constexpr uint8_t ocpTypeBitMask = 0b11110000; 23*560e6af7SHarshit Aghera constexpr uint8_t ocpVersionBitMask = 0b00001111; 24*560e6af7SHarshit Aghera constexpr uint8_t instanceIdBitMask = 0b00011111; 25*560e6af7SHarshit Aghera constexpr uint8_t instanceIdReservedBitMask = 0b00100000; 26*560e6af7SHarshit Aghera constexpr uint8_t datagramBitMask = 0b01000000; 27*560e6af7SHarshit Aghera constexpr uint8_t requestBitMask = 0b10000000; 28*560e6af7SHarshit Aghera 29*560e6af7SHarshit Aghera constexpr uint8_t instanceMin = 0; 30*560e6af7SHarshit Aghera constexpr uint8_t instanceMax = 31; 31*560e6af7SHarshit Aghera 32*560e6af7SHarshit Aghera enum class CompletionCode : uint8_t 33*560e6af7SHarshit Aghera { 34*560e6af7SHarshit Aghera SUCCESS = 0x00, 35*560e6af7SHarshit Aghera ERROR = 0x01, 36*560e6af7SHarshit Aghera ERR_INVALID_DATA = 0x02, 37*560e6af7SHarshit Aghera ERR_INVALID_DATA_LENGTH = 0x03, 38*560e6af7SHarshit Aghera ERR_NOT_READY = 0x04, 39*560e6af7SHarshit Aghera ERR_UNSUPPORTED_COMMAND_CODE = 0x05, 40*560e6af7SHarshit Aghera ERR_UNSUPPORTED_MSG_TYPE = 0x06, 41*560e6af7SHarshit Aghera ERR_BUS_ACCESS = 0x7f, 42*560e6af7SHarshit Aghera ERR_NULL = 0x80, 43*560e6af7SHarshit Aghera }; 44*560e6af7SHarshit Aghera 45*560e6af7SHarshit Aghera enum class ReasonCode : uint16_t 46*560e6af7SHarshit Aghera { 47*560e6af7SHarshit Aghera REASON_NONE = 0x00, 48*560e6af7SHarshit Aghera }; 49*560e6af7SHarshit Aghera 50*560e6af7SHarshit Aghera enum class MessageType : uint8_t 51*560e6af7SHarshit Aghera { 52*560e6af7SHarshit Aghera RESPONSE = 0, //!< OCP MCTP VDM response message 53*560e6af7SHarshit Aghera REQUEST = 2, //!< OCP MCTP VDM request message 54*560e6af7SHarshit Aghera }; 55*560e6af7SHarshit Aghera 56*560e6af7SHarshit Aghera struct BindingPciVid 57*560e6af7SHarshit Aghera { 58*560e6af7SHarshit Aghera uint16_t pci_vendor_id; //!< PCI defined vendor ID 59*560e6af7SHarshit Aghera uint8_t instance_id; //!< Instance ID 60*560e6af7SHarshit Aghera uint8_t ocp_version; //!< OCP version 61*560e6af7SHarshit Aghera uint8_t ocp_accelerator_management_msg_type; //!< Message Type 62*560e6af7SHarshit Aghera } __attribute__((packed)); 63*560e6af7SHarshit Aghera 64*560e6af7SHarshit Aghera struct Message 65*560e6af7SHarshit Aghera { 66*560e6af7SHarshit Aghera BindingPciVid hdr; //!< OCP MCTP VDM message header 67*560e6af7SHarshit Aghera } __attribute__((packed)); 68*560e6af7SHarshit Aghera 69*560e6af7SHarshit Aghera struct BindingPciVidInfo 70*560e6af7SHarshit Aghera { 71*560e6af7SHarshit Aghera uint8_t ocp_accelerator_management_msg_type; 72*560e6af7SHarshit Aghera uint8_t instance_id; 73*560e6af7SHarshit Aghera uint8_t msg_type; 74*560e6af7SHarshit Aghera }; 75*560e6af7SHarshit Aghera 76*560e6af7SHarshit Aghera struct CommonRequest 77*560e6af7SHarshit Aghera { 78*560e6af7SHarshit Aghera Message msgHdr; 79*560e6af7SHarshit Aghera uint8_t command; 80*560e6af7SHarshit Aghera uint8_t data_size; 81*560e6af7SHarshit Aghera } __attribute__((packed)); 82*560e6af7SHarshit Aghera 83*560e6af7SHarshit Aghera struct CommonResponse 84*560e6af7SHarshit Aghera { 85*560e6af7SHarshit Aghera Message msgHdr; 86*560e6af7SHarshit Aghera uint8_t command; 87*560e6af7SHarshit Aghera uint8_t completion_code; 88*560e6af7SHarshit Aghera uint16_t reserved; 89*560e6af7SHarshit Aghera uint16_t data_size; 90*560e6af7SHarshit Aghera } __attribute__((packed)); 91*560e6af7SHarshit Aghera 92*560e6af7SHarshit Aghera struct CommonNonSuccessResponse 93*560e6af7SHarshit Aghera { 94*560e6af7SHarshit Aghera Message msgHdr; 95*560e6af7SHarshit Aghera uint8_t command; 96*560e6af7SHarshit Aghera uint8_t completion_code; 97*560e6af7SHarshit Aghera uint16_t reason_code; 98*560e6af7SHarshit Aghera } __attribute__((packed)); 99*560e6af7SHarshit Aghera 100*560e6af7SHarshit Aghera int packHeader(uint16_t pciVendorId, const BindingPciVidInfo& hdr, 101*560e6af7SHarshit Aghera BindingPciVid& msg); 102*560e6af7SHarshit Aghera 103*560e6af7SHarshit Aghera int decodeReasonCodeAndCC(std::span<const uint8_t> buf, CompletionCode& cc, 104*560e6af7SHarshit Aghera uint16_t& reasonCode); 105*560e6af7SHarshit Aghera 106*560e6af7SHarshit Aghera } // namespace accelerator_management 107*560e6af7SHarshit Aghera } // namespace ocp 108