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Searched refs:uncore (Results 1 – 25 of 149) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_uncore.c42 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) in fw_domains_get() argument
44 uncore->fw_get_funcs->force_wake_get(uncore, fw_domains); in fw_domains_get()
53 i915->uncore.debug = &i915->mmio_debug; in intel_uncore_mmio_debug_init_early()
56 static void mmio_debug_suspend(struct intel_uncore *uncore) in mmio_debug_suspend() argument
58 if (!uncore->debug) in mmio_debug_suspend()
61 spin_lock(&uncore->debug->lock); in mmio_debug_suspend()
64 if (!uncore->debug->suspend_count++) { in mmio_debug_suspend()
65 uncore->debug->saved_mmio_check = uncore->debug->unclaimed_mmio_check; in mmio_debug_suspend()
66 uncore->debug->unclaimed_mmio_check = 0; in mmio_debug_suspend()
69 spin_unlock(&uncore->debug->lock); in mmio_debug_suspend()
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H A Dvlv_suspend.c111 struct intel_uncore *uncore = &i915->uncore; in vlv_save_gunit_s0ix_state() local
118 s->wr_watermark = intel_uncore_read(uncore, GEN7_WR_WATERMARK); in vlv_save_gunit_s0ix_state()
119 s->gfx_prio_ctrl = intel_uncore_read(uncore, GEN7_GFX_PRIO_CTRL); in vlv_save_gunit_s0ix_state()
120 s->arb_mode = intel_uncore_read(uncore, ARB_MODE); in vlv_save_gunit_s0ix_state()
121 s->gfx_pend_tlb0 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB0); in vlv_save_gunit_s0ix_state()
122 s->gfx_pend_tlb1 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB1); in vlv_save_gunit_s0ix_state()
125 s->lra_limits[i] = intel_uncore_read(uncore, GEN7_LRA_LIMITS(i)); in vlv_save_gunit_s0ix_state()
127 s->media_max_req_count = intel_uncore_read(uncore, GEN7_MEDIA_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
128 s->gfx_max_req_count = intel_uncore_read(uncore, GEN7_GFX_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
130 s->render_hwsp = intel_uncore_read(uncore, RENDER_HWS_PGA_GEN7); in vlv_save_gunit_s0ix_state()
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H A Dintel_clock_gating.c58 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE); in gen9_init_clock_gating()
62 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP); in gen9_init_clock_gating()
65 intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM); in gen9_init_clock_gating()
71 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE); in gen9_init_clock_gating()
79 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); in bxt_init_clock_gating()
85 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); in bxt_init_clock_gating()
91 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, in bxt_init_clock_gating()
92 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | in bxt_init_clock_gating()
101 intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950)); in bxt_init_clock_gating()
107 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); in bxt_init_clock_gating()
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H A Dintel_uncore.h92 void (*force_wake_get)(struct intel_uncore *uncore,
97 enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore,
99 enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore,
102 u8 (*mmio_readb)(struct intel_uncore *uncore,
104 u16 (*mmio_readw)(struct intel_uncore *uncore,
106 u32 (*mmio_readl)(struct intel_uncore *uncore,
108 u64 (*mmio_readq)(struct intel_uncore *uncore,
111 void (*mmio_writeb)(struct intel_uncore *uncore,
113 void (*mmio_writew)(struct intel_uncore *uncore,
115 void (*mmio_writel)(struct intel_uncore *uncore,
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H A Di915_irq.c81 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, in gen3_irq_reset() argument
84 intel_uncore_write(uncore, imr, 0xffffffff); in gen3_irq_reset()
85 intel_uncore_posting_read(uncore, imr); in gen3_irq_reset()
87 intel_uncore_write(uncore, ier, 0); in gen3_irq_reset()
90 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset()
91 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset()
92 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset()
93 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset()
96 static void gen2_irq_reset(struct intel_uncore *uncore) in gen2_irq_reset() argument
98 intel_uncore_write16(uncore, GEN2_IMR, 0xffff); in gen2_irq_reset()
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H A Dintel_pcode.c55 static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox, in __snb_pcode_rw() argument
60 lockdep_assert_held(&uncore->i915->sb_lock); in __snb_pcode_rw()
68 if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) in __snb_pcode_rw()
71 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val); in __snb_pcode_rw()
72 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0); in __snb_pcode_rw()
73 intel_uncore_write_fw(uncore, in __snb_pcode_rw()
76 if (__intel_wait_for_register_fw(uncore, in __snb_pcode_rw()
85 *val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA); in __snb_pcode_rw()
87 *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1); in __snb_pcode_rw()
89 if (GRAPHICS_VER(uncore->i915) > 6) in __snb_pcode_rw()
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H A Di915_hwmon.c48 struct intel_uncore *uncore; member
72 struct intel_uncore *uncore = ddat->uncore; in hwm_locked_with_pm_intel_uncore_rmw() local
75 with_intel_runtime_pm(uncore->rpm, wakeref) { in hwm_locked_with_pm_intel_uncore_rmw()
78 intel_uncore_rmw(uncore, reg, clear, set); in hwm_locked_with_pm_intel_uncore_rmw()
93 struct intel_uncore *uncore = ddat->uncore; in hwm_field_read_and_scale() local
97 with_intel_runtime_pm(uncore->rpm, wakeref) in hwm_field_read_and_scale()
98 reg_value = intel_uncore_read(uncore, rgadr); in hwm_field_read_and_scale()
128 struct intel_uncore *uncore = ddat->uncore; in hwm_energy() local
140 with_intel_runtime_pm(uncore->rpm, wakeref) { in hwm_energy()
143 reg_val = intel_uncore_read(uncore, rgaddr); in hwm_energy()
[all …]
H A Di915_irq.h43 void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg);
45 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
48 void gen3_irq_init(struct intel_uncore *uncore,
53 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \ argument
56 gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
60 #define GEN3_IRQ_RESET(uncore, type) \ argument
61 gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
63 #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \ argument
66 gen3_irq_init((uncore), \
72 #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \ argument
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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_rc6.c48 return rc6_to_gt(rc)->uncore; in rc6_to_uncore()
59 struct intel_uncore *uncore = gt->uncore; in gen11_rc6_enable() local
70 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); in gen11_rc6_enable()
71 intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); in gen11_rc6_enable()
73 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen11_rc6_enable()
74 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen11_rc6_enable()
76 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen11_rc6_enable()
78 intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA); in gen11_rc6_enable()
80 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); in gen11_rc6_enable()
82 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ in gen11_rc6_enable()
[all …]
H A Dintel_gt_clock_utils.c13 static u32 read_reference_ts_freq(struct intel_uncore *uncore) in read_reference_ts_freq() argument
15 u32 ts_override = intel_uncore_read(uncore, GEN9_TIMESTAMP_OVERRIDE); in read_reference_ts_freq()
30 static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore, in gen11_get_crystal_clock_freq() argument
56 static u32 gen11_read_clock_frequency(struct intel_uncore *uncore) in gen11_read_clock_frequency() argument
58 u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); in gen11_read_clock_frequency()
71 freq = read_reference_ts_freq(uncore); in gen11_read_clock_frequency()
73 u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0); in gen11_read_clock_frequency()
75 freq = gen11_get_crystal_clock_freq(uncore, c0); in gen11_read_clock_frequency()
89 static u32 gen9_read_clock_frequency(struct intel_uncore *uncore) in gen9_read_clock_frequency() argument
91 u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); in gen9_read_clock_frequency()
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H A Dintel_gt_irq.c34 void __iomem * const regs = intel_uncore_regs(gt->uncore); in gen11_gt_engine_identity()
151 void __iomem * const regs = intel_uncore_regs(gt->uncore); in gen11_gt_bank_handler()
186 void __iomem * const regs = intel_uncore_regs(gt->uncore); in gen11_gt_reset_one_iir()
215 struct intel_uncore *uncore = gt->uncore; in gen11_gt_irq_reset() local
218 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0); in gen11_gt_irq_reset()
219 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); in gen11_gt_irq_reset()
221 intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0); in gen11_gt_irq_reset()
223 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0); in gen11_gt_irq_reset()
226 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); in gen11_gt_irq_reset()
227 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0); in gen11_gt_irq_reset()
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H A Dintel_gtt.c406 struct intel_uncore *uncore = gt->uncore; in gtt_write_workarounds() local
415 intel_uncore_write(uncore, in gtt_write_workarounds()
419 intel_uncore_write(uncore, in gtt_write_workarounds()
423 intel_uncore_write(uncore, in gtt_write_workarounds()
427 intel_uncore_write(uncore, in gtt_write_workarounds()
444 intel_uncore_rmw(uncore, in gtt_write_workarounds()
462 intel_uncore_write(uncore, in gtt_write_workarounds()
466 intel_uncore_read(uncore, in gtt_write_workarounds()
471 static void xelpmp_setup_private_ppat(struct intel_uncore *uncore) in xelpmp_setup_private_ppat() argument
473 intel_uncore_write(uncore, XELPMP_PAT_INDEX(0), in xelpmp_setup_private_ppat()
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H A Dintel_gt_pm_debugfs.c32 intel_uncore_forcewake_user_get(gt->uncore); in intel_gt_pm_debugfs_forcewake_user_open()
38 intel_uncore_forcewake_user_put(gt->uncore); in intel_gt_pm_debugfs_forcewake_user_release()
70 struct intel_uncore *uncore = gt->uncore; in fw_domains_show() local
75 uncore->user_forcewake_count); in fw_domains_show()
77 for_each_fw_domain(fw_domain, uncore, tmp) in fw_domains_show()
89 struct intel_uncore *uncore = gt->uncore; in vlv_drpc() local
92 mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT); in vlv_drpc()
93 pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS); in vlv_drpc()
94 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); in vlv_drpc()
115 struct intel_uncore *uncore = gt->uncore; in gen6_drpc() local
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H A Dintel_rps.c48 return rps_to_gt(rps)->uncore; in rps_to_uncore()
70 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) in set() argument
72 intel_uncore_write_fw(uncore, reg, val); in set()
207 intel_uncore_write(gt->uncore, in rps_enable_interrupts()
240 intel_uncore_write(gt->uncore, in rps_disable_interrupts()
278 struct intel_uncore *uncore = rps_to_uncore(rps); in gen5_rps_init() local
298 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); in gen5_rps_init()
316 struct intel_uncore *uncore = in __ips_chipset_val() local
335 total = intel_uncore_read(uncore, DMIEC); in __ips_chipset_val()
336 total += intel_uncore_read(uncore, DDREC); in __ips_chipset_val()
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H A Dintel_sa_media.c16 struct intel_uncore *uncore; in intel_sa_mediagt_setup() local
18 uncore = drmm_kzalloc(&i915->drm, sizeof(*uncore), GFP_KERNEL); in intel_sa_mediagt_setup()
19 if (!uncore) in intel_sa_mediagt_setup()
22 uncore->gsi_offset = gsi_offset; in intel_sa_mediagt_setup()
26 intel_uncore_init_early(uncore, gt); in intel_sa_mediagt_setup()
32 uncore->regs = intel_uncore_regs(&i915->uncore); in intel_sa_mediagt_setup()
33 if (drm_WARN_ON(&i915->drm, uncore->regs == NULL)) in intel_sa_mediagt_setup()
36 gt->uncore = uncore; in intel_sa_mediagt_setup()
H A Dintel_gt_mcr.c157 (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
171 intel_uncore_read(gt->uncore, in intel_gt_mcr_init()
175 intel_uncore_read(gt->uncore, XEHP_FUSE4)); in intel_gt_mcr_init()
205 ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
249 struct intel_uncore *uncore = gt->uncore; in rw_with_mcr_steering_fw() local
254 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70)) { in rw_with_mcr_steering_fw()
262 intel_uncore_write_fw(uncore, MTL_MCR_SELECTOR, in rw_with_mcr_steering_fw()
266 } else if (GRAPHICS_VER(uncore->i915) >= 11) { in rw_with_mcr_steering_fw()
285 mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); in rw_with_mcr_steering_fw()
290 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); in rw_with_mcr_steering_fw()
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H A Dintel_gt.c68 gt->uncore = &i915->uncore; in intel_root_gt_init_early()
138 struct intel_uncore *uncore = gt->uncore; in init_unused_ring() local
140 intel_uncore_write(uncore, RING_CTL(base), 0); in init_unused_ring()
141 intel_uncore_write(uncore, RING_HEAD(base), 0); in init_unused_ring()
142 intel_uncore_write(uncore, RING_TAIL(base), 0); in init_unused_ring()
143 intel_uncore_write(uncore, RING_START(base), 0); in init_unused_ring()
168 struct intel_uncore *uncore = gt->uncore; in intel_gt_init_hw() local
174 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); in intel_gt_init_hw()
177 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf)); in intel_gt_init_hw()
180 intel_uncore_write(uncore, in intel_gt_init_hw()
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H A Dintel_ggtt_fencing.c56 return fence->ggtt->vm.gt->uncore; in fence_to_uncore()
92 struct intel_uncore *uncore = fence_to_uncore(fence); in i965_write_fence_reg() local
104 intel_uncore_write_fw(uncore, fence_reg_lo, 0); in i965_write_fence_reg()
105 intel_uncore_posting_read_fw(uncore, fence_reg_lo); in i965_write_fence_reg()
107 intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val)); in i965_write_fence_reg()
108 intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val)); in i965_write_fence_reg()
109 intel_uncore_posting_read_fw(uncore, fence_reg_lo); in i965_write_fence_reg()
139 struct intel_uncore *uncore = fence_to_uncore(fence); in i915_write_fence_reg() local
142 intel_uncore_write_fw(uncore, reg, val); in i915_write_fence_reg()
143 intel_uncore_posting_read_fw(uncore, reg); in i915_write_fence_reg()
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H A Dintel_gt_pm_irq.c16 struct intel_uncore *uncore = gt->uncore; in write_pm_imr() local
29 intel_uncore_write(uncore, reg, mask); in write_pm_imr()
64 struct intel_uncore *uncore = gt->uncore; in gen6_gt_pm_reset_iir() local
69 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
70 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
71 intel_uncore_posting_read(uncore, reg); in gen6_gt_pm_reset_iir()
77 struct intel_uncore *uncore = gt->uncore; in write_pm_ier() local
90 intel_uncore_write(uncore, reg, mask); in write_pm_ier()
/openbmc/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_fw.c22 struct intel_uncore *uncore = gt->uncore; in guc_prepare_xfer() local
29 if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50)) in guc_prepare_xfer()
34 intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags); in guc_prepare_xfer()
36 if (IS_GEN9_LP(uncore->i915)) in guc_prepare_xfer()
37 intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); in guc_prepare_xfer()
39 intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); in guc_prepare_xfer()
41 if (GRAPHICS_VER(uncore->i915) == 9) { in guc_prepare_xfer()
43 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, 0, in guc_prepare_xfer()
47 intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF); in guc_prepare_xfer()
52 struct intel_uncore *uncore) in guc_xfer_rsa_mmio() argument
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_irq.c54 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); in ilk_update_display_irq()
55 intel_uncore_posting_read(&dev_priv->uncore, DEIMR); in ilk_update_display_irq()
88 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
95 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val); in bdw_update_port_irq()
96 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
126 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in bdw_update_pipe_irq()
127 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
153 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR); in ibx_display_interrupt_update()
165 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr); in ibx_display_interrupt_update()
166 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR); in ibx_display_interrupt_update()
[all …]
H A Dintel_de.h16 return intel_uncore_read(&i915->uncore, reg); in intel_de_read()
22 return intel_uncore_read8(&i915->uncore, reg); in intel_de_read8()
29 return intel_uncore_read64_2x32(&i915->uncore, lower_reg, upper_reg); in intel_de_read64_2x32()
35 intel_uncore_posting_read(&i915->uncore, reg); in intel_de_posting_read()
41 intel_uncore_write(&i915->uncore, reg, val); in intel_de_write()
47 return intel_uncore_rmw(&i915->uncore, reg, clear, set); in intel_de_rmw()
54 return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout); in intel_de_wait_for_register()
61 return intel_wait_for_register_fw(&i915->uncore, reg, mask, value, timeout); in intel_de_wait_for_register_fw()
70 return __intel_wait_for_register(&i915->uncore, reg, mask, value, in __intel_de_wait_for_register()
101 val = intel_uncore_read_fw(&i915->uncore, reg); in intel_de_read_fw()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/selftests/
H A Dintel_uncore.c165 struct intel_uncore *uncore = gt->uncore; in live_forcewake_ops() local
201 wakeref = intel_runtime_pm_get(uncore->rpm); in live_forcewake_ops()
203 for_each_fw_domain(domain, uncore, tmp) { in live_forcewake_ops()
213 u32 __iomem *reg = intel_uncore_regs(uncore) + engine->mmio_base + r->offset; in live_forcewake_ops()
220 fw_domains = intel_uncore_forcewake_for_reg(uncore, mmio, in live_forcewake_ops()
225 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { in live_forcewake_ops()
235 intel_uncore_forcewake_get(uncore, fw_domains); in live_forcewake_ops()
237 intel_uncore_forcewake_put(uncore, fw_domains); in live_forcewake_ops()
240 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { in live_forcewake_ops()
272 intel_runtime_pm_put(uncore->rpm, wakeref); in live_forcewake_ops()
[all …]
/openbmc/linux/drivers/platform/x86/intel/uncore-frequency/
H A DMakefile6 obj-$(CONFIG_INTEL_UNCORE_FREQ_CONTROL) += intel-uncore-frequency.o
7 intel-uncore-frequency-y := uncore-frequency.o
8 obj-$(CONFIG_INTEL_UNCORE_FREQ_CONTROL) += intel-uncore-frequency-common.o
9 intel-uncore-frequency-common-y := uncore-frequency-common.o
10 obj-$(CONFIG_INTEL_UNCORE_FREQ_CONTROL_TPMI) += intel-uncore-frequency-tpmi.o
11 intel-uncore-frequency-tpmi-y := uncore-frequency-tpmi.o
/openbmc/linux/arch/x86/events/amd/
H A Duncore.c129 struct amd_uncore *uncore = event_to_amd_uncore(event); in amd_uncore_add() local
133 if (hwc->idx != -1 && uncore->events[hwc->idx] == event) in amd_uncore_add()
136 for (i = 0; i < uncore->num_counters; i++) { in amd_uncore_add()
137 if (uncore->events[i] == event) { in amd_uncore_add()
145 for (i = 0; i < uncore->num_counters; i++) { in amd_uncore_add()
146 if (cmpxchg(&uncore->events[i], NULL, event) == NULL) { in amd_uncore_add()
156 hwc->config_base = uncore->msr_base + (2 * hwc->idx); in amd_uncore_add()
157 hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx); in amd_uncore_add()
158 hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx; in amd_uncore_add()
180 struct amd_uncore *uncore = event_to_amd_uncore(event); in amd_uncore_del() local
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