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Searched refs:sdr_base (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/arch/powerpc/platforms/4xx/
H A Dpci.c641 unsigned int sdr_base; member
671 val = mfdcri(SDR0, port->sdr_base + sdr_offset); in ppc4xx_pciex_wait_on_sdr()
855 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in ppc440spe_pciex_init_port_hw()
856 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); in ppc440spe_pciex_init_port_hw()
858 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); in ppc440spe_pciex_init_port_hw()
859 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
860 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
861 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
862 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
864 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1, in ppc440spe_pciex_init_port_hw()
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/openbmc/linux/arch/arm/mach-socfpga/
H A Dcore.h33 u32 socfpga_sdram_self_refresh(u32 sdr_base);
H A Dpm.c25 static u32 (*socfpga_sdram_self_refresh_in_ocram)(u32 sdr_base);