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Searched refs:patched_crtc_timing (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.c163 struct dc_crtc_timing patched_crtc_timing; in optc1_program_timing() local
180 patched_crtc_timing = *dc_crtc_timing; in optc1_program_timing()
181 apply_front_porch_workaround(&patched_crtc_timing); in optc1_program_timing()
182 optc1->orginal_patched_timing = patched_crtc_timing; in optc1_program_timing()
188 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); in optc1_program_timing()
193 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); in optc1_program_timing()
196 asic_blank_start = patched_crtc_timing.h_total - in optc1_program_timing()
197 patched_crtc_timing.h_front_porch; in optc1_program_timing()
201 patched_crtc_timing.h_border_right - in optc1_program_timing()
202 patched_crtc_timing.h_addressable - in optc1_program_timing()
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H A Ddcn10_hw_sequencer.c3699 struct dc_crtc_timing patched_crtc_timing; in dcn10_get_vupdate_offset_from_vsync() local
3704 patched_crtc_timing = *dc_crtc_timing; in dcn10_get_vupdate_offset_from_vsync()
3705 apply_front_porch_workaround(&patched_crtc_timing); in dcn10_get_vupdate_offset_from_vsync()
3707 interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1; in dcn10_get_vupdate_offset_from_vsync()
3709 vesa_sync_start = patched_crtc_timing.v_addressable + in dcn10_get_vupdate_offset_from_vsync()
3710 patched_crtc_timing.v_border_bottom + in dcn10_get_vupdate_offset_from_vsync()
3711 patched_crtc_timing.v_front_porch; in dcn10_get_vupdate_offset_from_vsync()
3713 asic_blank_end = (patched_crtc_timing.v_total - in dcn10_get_vupdate_offset_from_vsync()
3715 patched_crtc_timing.v_border_top) in dcn10_get_vupdate_offset_from_vsync()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.c286 struct dc_crtc_timing patched_crtc_timing; in dce110_timing_generator_program_timing_generator() local
303 patched_crtc_timing = *dc_crtc_timing; in dce110_timing_generator_program_timing_generator()
305 dce110_timing_generator_apply_front_porch_workaround(tg, &patched_crtc_timing); in dce110_timing_generator_program_timing_generator()
309 bp_params.h_total = patched_crtc_timing.h_total; in dce110_timing_generator_program_timing_generator()
311 patched_crtc_timing.h_addressable; in dce110_timing_generator_program_timing_generator()
312 bp_params.v_total = patched_crtc_timing.v_total; in dce110_timing_generator_program_timing_generator()
313 bp_params.v_addressable = patched_crtc_timing.v_addressable; in dce110_timing_generator_program_timing_generator()
316 bp_params.h_sync_width = patched_crtc_timing.h_sync_width; in dce110_timing_generator_program_timing_generator()
318 bp_params.v_sync_width = patched_crtc_timing.v_sync_width; in dce110_timing_generator_program_timing_generator()
322 patched_crtc_timing.h_border_left; in dce110_timing_generator_program_timing_generator()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1104 struct dc_crtc_timing patched_crtc_timing; in dcn20_adjust_freesync_v_startup() local
1109 patched_crtc_timing = *dc_crtc_timing; in dcn20_adjust_freesync_v_startup()
1111 if (patched_crtc_timing.flags.INTERLACE == 1) { in dcn20_adjust_freesync_v_startup()
1112 if (patched_crtc_timing.v_front_porch < 2) in dcn20_adjust_freesync_v_startup()
1113 patched_crtc_timing.v_front_porch = 2; in dcn20_adjust_freesync_v_startup()
1115 if (patched_crtc_timing.v_front_porch < 1) in dcn20_adjust_freesync_v_startup()
1116 patched_crtc_timing.v_front_porch = 1; in dcn20_adjust_freesync_v_startup()
1120 asic_blank_start = patched_crtc_timing.v_total - in dcn20_adjust_freesync_v_startup()
1121 patched_crtc_timing.v_front_porch; in dcn20_adjust_freesync_v_startup()
1125 patched_crtc_timing.v_border_bottom - in dcn20_adjust_freesync_v_startup()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1317 struct dc_crtc_timing patched_crtc_timing; in dcn20_adjust_freesync_v_startup() local
1322 patched_crtc_timing = *dc_crtc_timing; in dcn20_adjust_freesync_v_startup()
1324 if (patched_crtc_timing.flags.INTERLACE == 1) { in dcn20_adjust_freesync_v_startup()
1325 if (patched_crtc_timing.v_front_porch < 2) in dcn20_adjust_freesync_v_startup()
1326 patched_crtc_timing.v_front_porch = 2; in dcn20_adjust_freesync_v_startup()
1328 if (patched_crtc_timing.v_front_porch < 1) in dcn20_adjust_freesync_v_startup()
1329 patched_crtc_timing.v_front_porch = 1; in dcn20_adjust_freesync_v_startup()
1333 asic_blank_start = patched_crtc_timing.v_total - in dcn20_adjust_freesync_v_startup()
1334 patched_crtc_timing.v_front_porch; in dcn20_adjust_freesync_v_startup()
1338 patched_crtc_timing.v_border_bottom - in dcn20_adjust_freesync_v_startup()
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