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Searched refs:mvpp2_write (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/net/
H A Dmvpp2.c1283 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) in mvpp2_write() function
1416 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1418 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); in mvpp2_prs_hw_write()
1421 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1423 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1437 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1448 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1459 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); in mvpp2_prs_hw_inv()
1460 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD), in mvpp2_prs_hw_inv()
1892 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val); in mvpp2_prs_hw_port_init()
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/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_cls.c333 mvpp2_write(priv, MVPP2_CTRS_IDX, index); in mvpp2_cls_flow_hits()
342 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, index); in mvpp2_cls_flow_read()
352 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index); in mvpp2_cls_flow_write()
353 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]); in mvpp2_cls_flow_write()
354 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]); in mvpp2_cls_flow_write()
355 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]); in mvpp2_cls_flow_write()
360 mvpp2_write(priv, MVPP2_CTRS_IDX, index); in mvpp2_cls_lookup_hits()
371 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); in mvpp2_cls_lookup_read()
384 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); in mvpp2_cls_lookup_write()
385 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data); in mvpp2_cls_lookup_write()
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H A Dmvpp2_main.c74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) in mvpp2_write() function
420 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), in mvpp2_bm_pool_create()
422 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); in mvpp2_bm_pool_create()
439 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_create()
458 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); in mvpp2_bm_pool_bufsize_set()
567 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_destroy()
614 mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val); in mvpp23_bm_set_8pool_mode()
633 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(pool_id), val); in mvpp2_bm_pool_cleanup()
684 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); in mvpp2_bm_init()
686 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); in mvpp2_bm_init()
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H A Dmvpp2_prs.c33 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
35 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]); in mvpp2_prs_hw_write()
38 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
40 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam[i]); in mvpp2_prs_hw_write()
58 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_init_from_hw()
69 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_init_from_hw()
80 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); in mvpp2_prs_hw_inv()
81 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD), in mvpp2_prs_hw_inv()
1111 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val); in mvpp2_prs_hw_port_init()
1117 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); in mvpp2_prs_hw_port_init()
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H A Dmvpp2.h1527 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data);