Home
last modified time | relevance | path

Searched refs:clock_data (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/clk/stm32/
H A Dclk-stm32-core.c260 return stm32_mux_get_parent(mux->base, mux->clock_data, mux->mux_id); in clk_stm32_mux_get_parent()
270 stm32_mux_set_parent(mux->base, mux->clock_data, mux->mux_id, index); in clk_stm32_mux_set_parent()
290 stm32_gate_endisable(gate->base, gate->clock_data, gate->gate_id, enable); in clk_stm32_gate_endisable()
311 return stm32_gate_is_enabled(gate->base, gate->clock_data, gate->gate_id); in clk_stm32_gate_is_enabled()
321 stm32_gate_disable_unused(gate->base, gate->clock_data, gate->gate_id); in clk_stm32_gate_disable_unused()
345 ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate); in clk_stm32_divider_set_rate()
361 divider = &div->clock_data->dividers[div->div_id]; in clk_stm32_divider_round_rate()
388 return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate); in clk_stm32_divider_recalc_rate()
409 ret = stm32_divider_set_rate(composite->base, composite->clock_data, in clk_stm32_composite_set_rate()
425 return stm32_divider_get_rate(composite->base, composite->clock_data, in clk_stm32_composite_recalc_rate()
[all …]
H A Dclk-stm32-core.h72 struct clk_stm32_clock_data *clock_data; member
97 struct clk_stm32_clock_data *clock_data; member
107 struct clk_stm32_clock_data *clock_data; member
117 struct clk_stm32_clock_data *clock_data; member
129 struct clk_stm32_clock_data *clock_data; member
H A Dclk-stm32mp13.c1517 .clock_data = &stm32mp13_clock_data,
/openbmc/linux/drivers/clk/microchip/
H A Dclk-mpfs.c358 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); in mpfs_reset_read() local
360 return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); in mpfs_reset_read()
366 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); in mpfs_reset_write() local
368 writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); in mpfs_reset_write()
/openbmc/linux/kernel/time/
H A Dsched_clock.c38 struct clock_data { struct
61 static struct clock_data cd ____cacheline_aligned = { argument
/openbmc/linux/drivers/clk/bcm/
H A Dclk-bcm2835.c1436 const struct bcm2835_clock_data *clock_data = data; in bcm2835_register_clock() local
1447 for (i = 0; i < clock_data->num_mux_parents; i++) { in bcm2835_register_clock()
1448 parents[i] = clock_data->parents[i]; in bcm2835_register_clock()
1459 init.num_parents = clock_data->num_mux_parents; in bcm2835_register_clock()
1460 init.name = clock_data->name; in bcm2835_register_clock()
1461 init.flags = clock_data->flags | CLK_IGNORE_UNUSED; in bcm2835_register_clock()
1467 if (clock_data->set_rate_parent) in bcm2835_register_clock()
1470 if (clock_data->is_vpu_clock) { in bcm2835_register_clock()
1479 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE)) in bcm2835_register_clock()
1488 clock->data = clock_data; in bcm2835_register_clock()
/openbmc/linux/arch/arm/mach-omap1/
H A DMakefile9 obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
/openbmc/linux/drivers/media/platform/qcom/venus/
H A Dcore.h330 struct clock_data { struct
446 struct clock_data clk_data;
/openbmc/qemu/scripts/
H A Dreplay-dump.py241 clock_data = read_qword(dumpfile)
242 print_event(eid, name, "0x%x" % (clock_data))
/openbmc/linux/tools/perf/util/
H A Dheader.c3446 FEAT_OPR(CLOCK_DATA, clock_data, false),
/openbmc/linux/
H A Dopengrok1.0.log[all...]