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/openbmc/linux/Documentation/riscv/
H A Dvector.rst4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
14 status for the use of Vector in userspace. The intended usage guideline for
26 Sets the Vector enablement status of the calling thread, where the control
37 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_ON`: Allow Vector to be run for the
40 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_OFF`: Disallow Vector. Executing Vector
54 Vector enablement status for the calling thread. The calling thread is
55 not able to turn off Vector once it has been enabled. The prctl() call
62 Vector enablement setting for the calling thread at the next execve()
75 * EINVAL: Vector not supported, invalid enablement status for current or
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/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/selinux/recipes-devtool/android-tools/android-tools/debian/system/core/
H A DVector-cast.patch6 --- a/system/core/libutils/include/utils/Vector.h
7 +++ b/system/core/libutils/include/utils/Vector.h
11 const Vector<TYPE>& Vector<TYPE>::operator = (const Vector<TYPE>& rhs) const {
/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/selinux/recipes-devtool/android-tools/android-tools/debian/
H A DVector-cast.patch6 --- a/system/core/libutils/include/utils/Vector.h
7 +++ b/system/core/libutils/include/utils/Vector.h
11 const Vector<TYPE>& Vector<TYPE>::operator = (const Vector<TYPE>& rhs) const {
/openbmc/linux/tools/testing/selftests/arm64/fp/
H A DREADME28 Vector length: 512 bits
31 Vector length: 512 bits
34 Vector length: 512 bits
37 Vector length: 512 bits
40 Vector length: 512 bits
43 Vector length: 512 bits
46 Vector length: 512 bits
49 Vector length: 512 bits
52 Vector length: 512 bits
88 2) Run the sve-stress on *each* guest with the Vector-Length set to 32:
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/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dext.idef212 "Vector shift right and shuffle", \
218 …Vv32)", "Vd32."#DEST"=vavg(Vu32."#SRC",Vv32."#SRC")", "Vector Average "DESCR, …
219 …Vv32):rnd", "Vd32."#DEST"=vavg(Vu32."#SRC",Vv32."#SRC"):rnd", "Vector Average % Round"DE…
220 …,Vv32)", "Vd32."#DEST"=vnavg(Vu32."#SRC",Vv32."#SRC")", "Vector Negative Average "…
223 …32,Vv32)", "Vd32."#DEST"=vavg(Vu32."#SRC",Vv32."#SRC")", "Vector Average "DESCR, …
224 …32,Vv32):rnd", "Vd32."#DEST"=vavg(Vu32."#SRC",Vv32."#SRC"):rnd", "Vector Average % Round"DE…
276 MMVEC_LD(vL32b, "Aligned Vector Load", ATTRIBS(ATTR_VMEM,A_LOAD,A_CVI_VA),)
277 MMVEC_LDC(vL32b, "Aligned Vector Load Cur", ATTRIBS(ATTR_VMEM,A_LOAD,A_CVI_NEW,A_CVI_VA),)
278 MMVEC_LDT(vL32b, "Aligned Vector Load Tmp", ATTRIBS(ATTR_VMEM,A_LOAD,A_CVI_TMP),)
280 MMVEC_COND_EACH_EA(vL32b,"Conditional Aligned Vector Load",ATTRIBS(ATTR_VMEM,A_LOAD,A_CVI_VA),,"Vd3…
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/openbmc/linux/arch/x86/crypto/
H A DKconfig67 - AVX (Advanced Vector Extensions)
78 - AVX2 (Advanced Vector Extensions 2)
93 - AVX (Advanced Vector Extensions)
111 - AVX (Advanced Vector Extensions)
174 - AVX (Advanced Vector Extensions)
187 - AVX2 (Advanced Vector Extensions 2)
204 - AVX (Advanced Vector Extensions)
226 - AVX2 (Advanced Vector Extensions 2)
285 - AVX (Advanced Vector Extensions)
302 - AVX (Advanced Vector Extensions)
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/openbmc/qemu/target/hexagon/imported/
H A Dshift.idef199 ATTRIBS(), "Vector align bytes",
209 ATTRIBS(), "Vector splice bytes",
217 ATTRIBS(), "Vector splat halfwords from register",
227 ATTRIBS(), "Vector splat bytes from register",
236 ATTRIBS(), "Vector splat bytes from register",
517 /* Half Vector Immediate Shifts */
520 "Vector Arithmetic Shift Right by Immediate",
530 "Vector Logical Shift Right by Immediate",
539 "Vector Arithmetic Shift Left by Immediate",
547 /* Half Vector Register Shifts */
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H A Dmpy.idef207 Q6INSN(M2_vmpy2s_s0,"Rdd32=vmpyh(Rs32,Rt32):sat",ATTRIBS(),"Vector Multiply",vmac_sema(0))
208 Q6INSN(M2_vmpy2s_s1,"Rdd32=vmpyh(Rs32,Rt32):<<1:sat",ATTRIBS(),"Vector Multiply",vmac_sema(1))
216 Q6INSN(M2_vmac2s_s0,"Rxx32+=vmpyh(Rs32,Rt32):sat",ATTRIBS(),"Vector Multiply",vmac_sema(0))
217 Q6INSN(M2_vmac2s_s1,"Rxx32+=vmpyh(Rs32,Rt32):<<1:sat",ATTRIBS(),"Vector Multiply",vmac_sema(1))
224 Q6INSN(M2_vmpy2su_s0,"Rdd32=vmpyhsu(Rs32,Rt32):sat",ATTRIBS(),"Vector Multiply",vmac_sema(0))
225 Q6INSN(M2_vmpy2su_s1,"Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat",ATTRIBS(),"Vector Multiply",vmac_sema(1))
233 Q6INSN(M2_vmac2su_s0,"Rxx32+=vmpyhsu(Rs32,Rt32):sat",ATTRIBS(),"Vector Multiply",vmac_sema(0))
234 Q6INSN(M2_vmac2su_s1,"Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat",ATTRIBS(),"Vector Multiply",vmac_sema(1))
243 Q6INSN(M2_vmpy2s_s0pack,"Rd32=vmpyh(Rs32,Rt32):rnd:sat",ATTRIBS(A_ARCHV2),"Vector Multiply",vmac_se…
244 Q6INSN(M2_vmpy2s_s1pack,"Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat",ATTRIBS(A_ARCHV2),"Vector Multiply",vma…
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/openbmc/openbmc/poky/meta/conf/machine/include/arm/
H A Dfeature-arm-neon.inc10 TUNEVALID[vfpv3d16] = "Enable Vector Floating Point Version 3 with 16 registers (vfpv3-d16) unit."
13 TUNEVALID[vfpv3] = "Enable Vector Floating Point Version 3 with 32 registers (vfpv3) unit."
16 TUNEVALID[vfpv4] = "Enable Vector Floating Point Version 4 (vfpv4) unit."
20 TUNEVALID[vfpv4d16] = "Enable Vector Floating Point Version 4 with 16 registers (vfpv4-d16) unit."
23 TUNEVALID[vfpv5spd16] = "Enable Vector Floating Point Version 5, Single Precision. with 16 register…
H A Dfeature-arm-sve.inc1 # Scalable Vector Extension (SVE) for Armv8-A and R
H A Dfeature-arm-vfp.inc5 TUNEVALID[vfp] = "Enable Vector Floating Point (vfp) unit."
/openbmc/qemu/target/ppc/
H A Dinsn32.decode663 ## Vector Exclusive-OR-based Instructions
667 ## Vector Load/Store Instructions
684 ## Vector Integer Instructions
715 ## Vector Integer Logical Instructions
726 ## Vector Integer Average Instructions
735 ## Vector Integer Absolute Difference Instructions
741 ## Vector Bit Manipulation Instruction
755 ## Vector Permute and Formatting Instruction
798 ## Vector Integer Shift Instruction
832 ## Vector Integer Arithmetic Instructions
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/openbmc/linux/arch/sh/kernel/cpu/sh2/
H A Dex.S13 ! convert Exception Vector to Exception Number
36 ! Exception Vector Base
/openbmc/linux/arch/sh/kernel/cpu/sh2a/
H A Dex.S13 ! convert Exception Vector to Exception Number
57 ! Exception Vector Base
/openbmc/qemu/docs/system/arm/
H A Demulation.rst133 - FEAT_SVE (Scalable Vector Extension)
134 - FEAT_SVE_AES (Scalable Vector AES instructions)
135 - FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions)
136 - FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions)
137 - FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions)
138 - FEAT_SVE_SM4 (Scalable Vector SM4 instructions)
139 - FEAT_SVE2 (Scalable Vector Extension version 2)
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc116 * Vector register should aligned with the passed-in LMUL (EMUL).
240 * Vector unit-stride, strided, unit-stride segment, strided segment
248 * 4. Vector register numbers accessed by the segment load or store
260 * Vector unit-stride, strided, unit-stride segment, strided segment
277 * Vector indexed, indexed segment store check function.
286 * 5. Vector register numbers accessed by the segment load or store
311 * Vector indexed, indexed segment load check function.
697 * Vector load/store instructions have the EEW encoded
1169 *** Vector Integer Arithmetic Instructions
1468 /* Vector Widening Integer Add/Subtract */
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/openbmc/linux/drivers/net/can/softing/
H A DKconfig7 from Vector Gmbh.
25 from Vector Gmbh.
/openbmc/qemu/target/riscv/
H A Dinsn32.decode362 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
363 # Vector unit-stride load/store insns.
373 # Vector unit-stride mask load/store insns.
377 # Vector strided insns.
387 # Vector ordered-indexed and unordered-indexed load insns.
393 # Vector ordered-indexed and unordered-indexed store insns.
399 # Vector unit-stride fault-only-first load insns.
405 # Vector whole register insns
695 # Vector ordered and unordered reduction sum
700 # Vector widening ordered and unordered float reduction sum
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/openbmc/linux/arch/arc/kernel/
H A Dentry-arcv2.S24 ;############################ Vector Table #################################
30 VECTOR res_service ; Reset Vector
121 ; Instruction fetch or Data access, under a single Exception Vector
/openbmc/phosphor-inventory-manager/
H A Dpimgen.py234 class Vector(MethodCall): class
241 super(Vector, self).__init__(**kw)
479 filters = Vector(
495 events = Vector(
505 actions = Vector(templates=[action_type], args=action_args)
/openbmc/u-boot/doc/imx/habv4/guides/
H A Dmx6_mx7_spl_secure_boot.txt36 The U-Boot also append an Image Vector Table (IVT) in the final U-Boot proper
42 ^ | Image Vector Table |
72 v | Image Vector Table |
/openbmc/u-boot/arch/x86/cpu/
H A Du-boot-spl.lds60 * Reset Vector at the end of the Flash ROM
H A Du-boot.lds112 * Reset Vector at the end of the Flash ROM
/openbmc/qemu/docs/specs/
H A Dsev-guest-firmware.rst32 `OVMF Reset Vector file`_.
124 .. _OVMF Reset Vector file:
/openbmc/linux/Documentation/arch/x86/
H A Dintel-hfi.rst47 Local Vector Table of a CPU's local APIC, there exists a register for the
62 thermal entry in the Local APIC's Local Vector Table.

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