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Searched refs:SDIV (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/board/samsung/smdkc100/
H A Dlowlevel_init.S91 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
94 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
97 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
/openbmc/u-boot/board/samsung/goni/
H A Dlowlevel_init.S257 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
260 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
263 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
266 ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
/openbmc/u-boot/board/samsung/odroid/
H A Dodroid.c127 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1); in board_clock_init()
128 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); in board_clock_init()
211 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); in board_clock_init()
H A Dsetup.h11 #define SDIV(x) ((x) & 0x7) macro
/openbmc/linux/drivers/clk/renesas/
H A Drzg2l-cpg.c48 #define SDIV(val) FIELD_GET(GENMASK(2, 0), val) macro
708 16 + SDIV(val2)); in rzg2l_cpg_pll_clk_recalc_rate()
/openbmc/linux/arch/arm64/net/
H A Dbpf_jit.h237 #define A64_SDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, SDIV)
/openbmc/qemu/target/arm/tcg/
H A Da32.decode512 SDIV .... 0111 0001 .... 1111 .... 0001 .... @rdmn
H A Dt32.decode327 SDIV 1111 1011 1001 .... 1111 .... 1111 .... @rndm
/openbmc/qemu/target/sparc/
H A Dinsns.decode233 SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc
H A Dtranslate.c3750 TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL, gen_op_sdivcc) in TRANS()
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.c.inc2286 tcg_out_insn(s, 3508, SDIV, ext, a0, a1, a2);
2295 tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP0, a1, a2);