1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Nuvoton NPCM7xx I2C Controller driver 4 * 5 * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/debugfs.h> 10 #include <linux/errno.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/irq.h> 15 #include <linux/jiffies.h> 16 #include <linux/kernel.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 23 enum i2c_mode { 24 I2C_MASTER, 25 I2C_SLAVE, 26 }; 27 28 /* 29 * External I2C Interface driver xfer indication values, which indicate status 30 * of the bus. 31 */ 32 enum i2c_state_ind { 33 I2C_NO_STATUS_IND = 0, 34 I2C_SLAVE_RCV_IND, 35 I2C_SLAVE_XMIT_IND, 36 I2C_SLAVE_XMIT_MISSING_DATA_IND, 37 I2C_SLAVE_RESTART_IND, 38 I2C_SLAVE_DONE_IND, 39 I2C_MASTER_DONE_IND, 40 I2C_NACK_IND, 41 I2C_BUS_ERR_IND, 42 I2C_WAKE_UP_IND, 43 I2C_BLOCK_BYTES_ERR_IND, 44 I2C_SLAVE_RCV_MISSING_DATA_IND, 45 }; 46 47 /* 48 * Operation type values (used to define the operation currently running) 49 * module is interrupt driven, on each interrupt the current operation is 50 * checked to see if the module is currently reading or writing. 51 */ 52 enum i2c_oper { 53 I2C_NO_OPER = 0, 54 I2C_WRITE_OPER, 55 I2C_READ_OPER, 56 }; 57 58 /* I2C Bank (module had 2 banks of registers) */ 59 enum i2c_bank { 60 I2C_BANK_0 = 0, 61 I2C_BANK_1, 62 }; 63 64 /* Internal I2C states values (for the I2C module state machine). */ 65 enum i2c_state { 66 I2C_DISABLE = 0, 67 I2C_IDLE, 68 I2C_MASTER_START, 69 I2C_SLAVE_MATCH, 70 I2C_OPER_STARTED, 71 I2C_STOP_PENDING, 72 }; 73 74 #if IS_ENABLED(CONFIG_I2C_SLAVE) 75 /* Module supports setting multiple own slave addresses */ 76 enum i2c_addr { 77 I2C_SLAVE_ADDR1 = 0, 78 I2C_SLAVE_ADDR2, 79 I2C_SLAVE_ADDR3, 80 I2C_SLAVE_ADDR4, 81 I2C_SLAVE_ADDR5, 82 I2C_SLAVE_ADDR6, 83 I2C_SLAVE_ADDR7, 84 I2C_SLAVE_ADDR8, 85 I2C_SLAVE_ADDR9, 86 I2C_SLAVE_ADDR10, 87 I2C_GC_ADDR, 88 I2C_ARP_ADDR, 89 }; 90 #endif 91 92 /* init register and default value required to enable module */ 93 #define NPCM_I2CSEGCTL 0xE4 94 95 /* Common regs */ 96 #define NPCM_I2CSDA 0x00 97 #define NPCM_I2CST 0x02 98 #define NPCM_I2CCST 0x04 99 #define NPCM_I2CCTL1 0x06 100 #define NPCM_I2CADDR1 0x08 101 #define NPCM_I2CCTL2 0x0A 102 #define NPCM_I2CADDR2 0x0C 103 #define NPCM_I2CCTL3 0x0E 104 #define NPCM_I2CCST2 0x18 105 #define NPCM_I2CCST3 0x19 106 #define I2C_VER 0x1F 107 108 /* BANK 0 regs */ 109 #define NPCM_I2CADDR3 0x10 110 #define NPCM_I2CADDR7 0x11 111 #define NPCM_I2CADDR4 0x12 112 #define NPCM_I2CADDR8 0x13 113 #define NPCM_I2CADDR5 0x14 114 #define NPCM_I2CADDR9 0x15 115 #define NPCM_I2CADDR6 0x16 116 #define NPCM_I2CADDR10 0x17 117 #define NPCM_I2CCTL4 0x1A 118 #define NPCM_I2CCTL5 0x1B 119 #define NPCM_I2CSCLLT 0x1C /* SCL Low Time */ 120 #define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */ 121 #define NPCM_I2CSCLHT 0x1E /* SCL High Time */ 122 123 /* BANK 1 regs */ 124 #define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */ 125 #define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */ 126 #define NPCM_I2CT_OUT 0x14 /* Bus T.O. */ 127 #define NPCM_I2CPEC 0x16 /* PEC Data */ 128 #define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */ 129 #define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */ 130 #define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */ 131 132 #if IS_ENABLED(CONFIG_I2C_SLAVE) 133 /* 134 * npcm_i2caddr array: 135 * The module supports having multiple own slave addresses. 136 * Since the addr regs are sprinkled all over the address space, 137 * use this array to get the address or each register. 138 */ 139 #define I2C_NUM_OWN_ADDR 10 140 #define I2C_NUM_OWN_ADDR_SUPPORTED 2 141 142 static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { 143 NPCM_I2CADDR1, NPCM_I2CADDR2, NPCM_I2CADDR3, NPCM_I2CADDR4, 144 NPCM_I2CADDR5, NPCM_I2CADDR6, NPCM_I2CADDR7, NPCM_I2CADDR8, 145 NPCM_I2CADDR9, NPCM_I2CADDR10, 146 }; 147 #endif 148 149 /* NPCM_I2CST reg fields */ 150 #define NPCM_I2CST_XMIT BIT(0) /* Transmit mode */ 151 #define NPCM_I2CST_MASTER BIT(1) /* Master mode */ 152 #define NPCM_I2CST_NMATCH BIT(2) /* New match */ 153 #define NPCM_I2CST_STASTR BIT(3) /* Stall after start */ 154 #define NPCM_I2CST_NEGACK BIT(4) /* Negative ACK */ 155 #define NPCM_I2CST_BER BIT(5) /* Bus error */ 156 #define NPCM_I2CST_SDAST BIT(6) /* SDA status */ 157 #define NPCM_I2CST_SLVSTP BIT(7) /* Slave stop */ 158 159 /* NPCM_I2CCST reg fields */ 160 #define NPCM_I2CCST_BUSY BIT(0) /* Busy */ 161 #define NPCM_I2CCST_BB BIT(1) /* Bus busy */ 162 #define NPCM_I2CCST_MATCH BIT(2) /* Address match */ 163 #define NPCM_I2CCST_GCMATCH BIT(3) /* Global call match */ 164 #define NPCM_I2CCST_TSDA BIT(4) /* Test SDA line */ 165 #define NPCM_I2CCST_TGSCL BIT(5) /* Toggle SCL line */ 166 #define NPCM_I2CCST_MATCHAF BIT(6) /* Match address field */ 167 #define NPCM_I2CCST_ARPMATCH BIT(7) /* ARP address match */ 168 169 /* NPCM_I2CCTL1 reg fields */ 170 #define NPCM_I2CCTL1_START BIT(0) /* Generate start condition */ 171 #define NPCM_I2CCTL1_STOP BIT(1) /* Generate stop condition */ 172 #define NPCM_I2CCTL1_INTEN BIT(2) /* Interrupt enable */ 173 #define NPCM_I2CCTL1_EOBINTE BIT(3) 174 #define NPCM_I2CCTL1_ACK BIT(4) 175 #define NPCM_I2CCTL1_GCMEN BIT(5) /* Global call match enable */ 176 #define NPCM_I2CCTL1_NMINTE BIT(6) /* New match interrupt enable */ 177 #define NPCM_I2CCTL1_STASTRE BIT(7) /* Stall after start enable */ 178 179 /* RW1S fields (inside a RW reg): */ 180 #define NPCM_I2CCTL1_RWS \ 181 (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK) 182 183 /* npcm_i2caddr reg fields */ 184 #define NPCM_I2CADDR_A GENMASK(6, 0) /* Address */ 185 #define NPCM_I2CADDR_SAEN BIT(7) /* Slave address enable */ 186 187 /* NPCM_I2CCTL2 reg fields */ 188 #define I2CCTL2_ENABLE BIT(0) /* Module enable */ 189 #define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1) /* Bits 0:6 of frequency divisor */ 190 191 /* NPCM_I2CCTL3 reg fields */ 192 #define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0) /* Bits 7:8 of frequency divisor */ 193 #define I2CCTL3_ARPMEN BIT(2) /* ARP match enable */ 194 #define I2CCTL3_IDL_START BIT(3) 195 #define I2CCTL3_400K_MODE BIT(4) 196 #define I2CCTL3_BNK_SEL BIT(5) 197 #define I2CCTL3_SDA_LVL BIT(6) 198 #define I2CCTL3_SCL_LVL BIT(7) 199 200 /* NPCM_I2CCST2 reg fields */ 201 #define NPCM_I2CCST2_MATCHA1F BIT(0) 202 #define NPCM_I2CCST2_MATCHA2F BIT(1) 203 #define NPCM_I2CCST2_MATCHA3F BIT(2) 204 #define NPCM_I2CCST2_MATCHA4F BIT(3) 205 #define NPCM_I2CCST2_MATCHA5F BIT(4) 206 #define NPCM_I2CCST2_MATCHA6F BIT(5) 207 #define NPCM_I2CCST2_MATCHA7F BIT(5) 208 #define NPCM_I2CCST2_INTSTS BIT(7) 209 210 /* NPCM_I2CCST3 reg fields */ 211 #define NPCM_I2CCST3_MATCHA8F BIT(0) 212 #define NPCM_I2CCST3_MATCHA9F BIT(1) 213 #define NPCM_I2CCST3_MATCHA10F BIT(2) 214 #define NPCM_I2CCST3_EO_BUSY BIT(7) 215 216 /* NPCM_I2CCTL4 reg fields */ 217 #define I2CCTL4_HLDT GENMASK(5, 0) 218 #define I2CCTL4_LVL_WE BIT(7) 219 220 /* NPCM_I2CCTL5 reg fields */ 221 #define I2CCTL5_DBNCT GENMASK(3, 0) 222 223 /* NPCM_I2CFIF_CTS reg fields */ 224 #define NPCM_I2CFIF_CTS_RXF_TXE BIT(1) 225 #define NPCM_I2CFIF_CTS_RFTE_IE BIT(3) 226 #define NPCM_I2CFIF_CTS_CLR_FIFO BIT(6) 227 #define NPCM_I2CFIF_CTS_SLVRSTR BIT(7) 228 229 /* NPCM_I2CTXF_CTL reg field */ 230 #define NPCM_I2CTXF_CTL_THR_TXIE BIT(6) 231 232 /* NPCM_I2CT_OUT reg fields */ 233 #define NPCM_I2CT_OUT_TO_CKDIV GENMASK(5, 0) 234 #define NPCM_I2CT_OUT_T_OUTIE BIT(6) 235 #define NPCM_I2CT_OUT_T_OUTST BIT(7) 236 237 /* NPCM_I2CTXF_STS reg fields */ 238 #define NPCM_I2CTXF_STS_TX_THST BIT(6) 239 240 /* NPCM_I2CRXF_STS reg fields */ 241 #define NPCM_I2CRXF_STS_RX_THST BIT(6) 242 243 /* NPCM_I2CFIF_CTL reg fields */ 244 #define NPCM_I2CFIF_CTL_FIFO_EN BIT(4) 245 246 /* NPCM_I2CRXF_CTL reg fields */ 247 #define NPCM_I2CRXF_CTL_THR_RXIE BIT(6) 248 249 #define MAX_I2C_HW_FIFO_SIZE 32 250 251 /* I2C_VER reg fields */ 252 #define I2C_VER_VERSION GENMASK(6, 0) 253 #define I2C_VER_FIFO_EN BIT(7) 254 255 /* stall/stuck timeout in us */ 256 #define DEFAULT_STALL_COUNT 25 257 258 /* SCLFRQ field position */ 259 #define SCLFRQ_0_TO_6 GENMASK(6, 0) 260 #define SCLFRQ_7_TO_8 GENMASK(8, 7) 261 262 /* supported clk settings. values in Hz. */ 263 #define I2C_FREQ_MIN_HZ 10000 264 #define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ 265 266 struct smb_timing_t { 267 u32 core_clk; 268 u8 hldt; 269 u8 dbcnt; 270 u16 sclfrq; 271 u8 scllt; 272 u8 sclht; 273 bool fast_mode; 274 }; 275 276 static struct smb_timing_t smb_timing_100khz[] = { 277 { 278 .core_clk = 100000000, .hldt = 0x2A, .dbcnt = 0x4, 279 .sclfrq = 0xFB, .scllt = 0x0, .sclht = 0x0, 280 .fast_mode = false, 281 }, 282 { 283 .core_clk = 62500000, .hldt = 0x2A, .dbcnt = 0x1, 284 .sclfrq = 0x9D, .scllt = 0x0, .sclht = 0x0, 285 .fast_mode = false, 286 }, 287 { 288 .core_clk = 50000000, .hldt = 0x2A, .dbcnt = 0x1, 289 .sclfrq = 0x7E, .scllt = 0x0, .sclht = 0x0, 290 .fast_mode = false, 291 }, 292 { 293 .core_clk = 48000000, .hldt = 0x2A, .dbcnt = 0x1, 294 .sclfrq = 0x79, .scllt = 0x0, .sclht = 0x0, 295 .fast_mode = false, 296 }, 297 { 298 .core_clk = 40000000, .hldt = 0x2A, .dbcnt = 0x1, 299 .sclfrq = 0x65, .scllt = 0x0, .sclht = 0x0, 300 .fast_mode = false, 301 }, 302 { 303 .core_clk = 30000000, .hldt = 0x2A, .dbcnt = 0x1, 304 .sclfrq = 0x4C, .scllt = 0x0, .sclht = 0x0, 305 .fast_mode = false, 306 }, 307 { 308 .core_clk = 29000000, .hldt = 0x2A, .dbcnt = 0x1, 309 .sclfrq = 0x49, .scllt = 0x0, .sclht = 0x0, 310 .fast_mode = false, 311 }, 312 { 313 .core_clk = 26000000, .hldt = 0x2A, .dbcnt = 0x1, 314 .sclfrq = 0x42, .scllt = 0x0, .sclht = 0x0, 315 .fast_mode = false, 316 }, 317 { 318 .core_clk = 25000000, .hldt = 0x2A, .dbcnt = 0x1, 319 .sclfrq = 0x3F, .scllt = 0x0, .sclht = 0x0, 320 .fast_mode = false, 321 }, 322 { 323 .core_clk = 24000000, .hldt = 0x2A, .dbcnt = 0x1, 324 .sclfrq = 0x3D, .scllt = 0x0, .sclht = 0x0, 325 .fast_mode = false, 326 }, 327 { 328 .core_clk = 20000000, .hldt = 0x2A, .dbcnt = 0x1, 329 .sclfrq = 0x33, .scllt = 0x0, .sclht = 0x0, 330 .fast_mode = false, 331 }, 332 { 333 .core_clk = 16180000, .hldt = 0x2A, .dbcnt = 0x1, 334 .sclfrq = 0x29, .scllt = 0x0, .sclht = 0x0, 335 .fast_mode = false, 336 }, 337 { 338 .core_clk = 15000000, .hldt = 0x23, .dbcnt = 0x1, 339 .sclfrq = 0x26, .scllt = 0x0, .sclht = 0x0, 340 .fast_mode = false, 341 }, 342 { 343 .core_clk = 13000000, .hldt = 0x1D, .dbcnt = 0x1, 344 .sclfrq = 0x21, .scllt = 0x0, .sclht = 0x0, 345 .fast_mode = false, 346 }, 347 { 348 .core_clk = 12000000, .hldt = 0x1B, .dbcnt = 0x1, 349 .sclfrq = 0x1F, .scllt = 0x0, .sclht = 0x0, 350 .fast_mode = false, 351 }, 352 { 353 .core_clk = 10000000, .hldt = 0x18, .dbcnt = 0x1, 354 .sclfrq = 0x1A, .scllt = 0x0, .sclht = 0x0, 355 .fast_mode = false, 356 }, 357 { 358 .core_clk = 9000000, .hldt = 0x16, .dbcnt = 0x1, 359 .sclfrq = 0x17, .scllt = 0x0, .sclht = 0x0, 360 .fast_mode = false, 361 }, 362 { 363 .core_clk = 8090000, .hldt = 0x14, .dbcnt = 0x1, 364 .sclfrq = 0x15, .scllt = 0x0, .sclht = 0x0, 365 .fast_mode = false, 366 }, 367 { 368 .core_clk = 7500000, .hldt = 0x7, .dbcnt = 0x1, 369 .sclfrq = 0x13, .scllt = 0x0, .sclht = 0x0, 370 .fast_mode = false, 371 }, 372 { 373 .core_clk = 6500000, .hldt = 0xE, .dbcnt = 0x1, 374 .sclfrq = 0x11, .scllt = 0x0, .sclht = 0x0, 375 .fast_mode = false, 376 }, 377 { 378 .core_clk = 4000000, .hldt = 0x9, .dbcnt = 0x1, 379 .sclfrq = 0xB, .scllt = 0x0, .sclht = 0x0, 380 .fast_mode = false, 381 }, 382 }; 383 384 static struct smb_timing_t smb_timing_400khz[] = { 385 { 386 .core_clk = 100000000, .hldt = 0x2A, .dbcnt = 0x3, 387 .sclfrq = 0x0, .scllt = 0x47, .sclht = 0x35, 388 .fast_mode = true, 389 }, 390 { 391 .core_clk = 62500000, .hldt = 0x2A, .dbcnt = 0x2, 392 .sclfrq = 0x0, .scllt = 0x2C, .sclht = 0x22, 393 .fast_mode = true, 394 }, 395 { 396 .core_clk = 50000000, .hldt = 0x21, .dbcnt = 0x1, 397 .sclfrq = 0x0, .scllt = 0x24, .sclht = 0x1B, 398 .fast_mode = true, 399 }, 400 { 401 .core_clk = 48000000, .hldt = 0x1E, .dbcnt = 0x1, 402 .sclfrq = 0x0, .scllt = 0x24, .sclht = 0x19, 403 .fast_mode = true, 404 }, 405 { 406 .core_clk = 40000000, .hldt = 0x1B, .dbcnt = 0x1, 407 .sclfrq = 0x0, .scllt = 0x1E, .sclht = 0x14, 408 .fast_mode = true, 409 }, 410 { 411 .core_clk = 33000000, .hldt = 0x15, .dbcnt = 0x1, 412 .sclfrq = 0x0, .scllt = 0x19, .sclht = 0x11, 413 .fast_mode = true, 414 }, 415 { 416 .core_clk = 30000000, .hldt = 0x15, .dbcnt = 0x1, 417 .sclfrq = 0x0, .scllt = 0x19, .sclht = 0xD, 418 .fast_mode = true, 419 }, 420 { 421 .core_clk = 29000000, .hldt = 0x11, .dbcnt = 0x1, 422 .sclfrq = 0x0, .scllt = 0x15, .sclht = 0x10, 423 .fast_mode = true, 424 }, 425 { 426 .core_clk = 26000000, .hldt = 0x10, .dbcnt = 0x1, 427 .sclfrq = 0x0, .scllt = 0x13, .sclht = 0xE, 428 .fast_mode = true, 429 }, 430 { 431 .core_clk = 25000000, .hldt = 0xF, .dbcnt = 0x1, 432 .sclfrq = 0x0, .scllt = 0x13, .sclht = 0xD, 433 .fast_mode = true, 434 }, 435 { 436 .core_clk = 24000000, .hldt = 0xD, .dbcnt = 0x1, 437 .sclfrq = 0x0, .scllt = 0x12, .sclht = 0xD, 438 .fast_mode = true, 439 }, 440 { 441 .core_clk = 20000000, .hldt = 0xB, .dbcnt = 0x1, 442 .sclfrq = 0x0, .scllt = 0xF, .sclht = 0xA, 443 .fast_mode = true, 444 }, 445 { 446 .core_clk = 16180000, .hldt = 0xA, .dbcnt = 0x1, 447 .sclfrq = 0x0, .scllt = 0xC, .sclht = 0x9, 448 .fast_mode = true, 449 }, 450 { 451 .core_clk = 15000000, .hldt = 0x9, .dbcnt = 0x1, 452 .sclfrq = 0x0, .scllt = 0xB, .sclht = 0x8, 453 .fast_mode = true, 454 }, 455 { 456 .core_clk = 13000000, .hldt = 0x7, .dbcnt = 0x1, 457 .sclfrq = 0x0, .scllt = 0xA, .sclht = 0x7, 458 .fast_mode = true, 459 }, 460 { 461 .core_clk = 12000000, .hldt = 0x7, .dbcnt = 0x1, 462 .sclfrq = 0x0, .scllt = 0xA, .sclht = 0x6, 463 .fast_mode = true, 464 }, 465 { 466 .core_clk = 10000000, .hldt = 0x6, .dbcnt = 0x1, 467 .sclfrq = 0x0, .scllt = 0x8, .sclht = 0x5, 468 .fast_mode = true, 469 }, 470 }; 471 472 static struct smb_timing_t smb_timing_1000khz[] = { 473 { 474 .core_clk = 100000000, .hldt = 0x15, .dbcnt = 0x4, 475 .sclfrq = 0x0, .scllt = 0x1C, .sclht = 0x15, 476 .fast_mode = true, 477 }, 478 { 479 .core_clk = 62500000, .hldt = 0xF, .dbcnt = 0x3, 480 .sclfrq = 0x0, .scllt = 0x11, .sclht = 0xE, 481 .fast_mode = true, 482 }, 483 { 484 .core_clk = 50000000, .hldt = 0xA, .dbcnt = 0x2, 485 .sclfrq = 0x0, .scllt = 0xE, .sclht = 0xB, 486 .fast_mode = true, 487 }, 488 { 489 .core_clk = 48000000, .hldt = 0x9, .dbcnt = 0x2, 490 .sclfrq = 0x0, .scllt = 0xD, .sclht = 0xB, 491 .fast_mode = true, 492 }, 493 { 494 .core_clk = 41000000, .hldt = 0x9, .dbcnt = 0x2, 495 .sclfrq = 0x0, .scllt = 0xC, .sclht = 0x9, 496 .fast_mode = true, 497 }, 498 { 499 .core_clk = 40000000, .hldt = 0x8, .dbcnt = 0x2, 500 .sclfrq = 0x0, .scllt = 0xB, .sclht = 0x9, 501 .fast_mode = true, 502 }, 503 { 504 .core_clk = 33000000, .hldt = 0x7, .dbcnt = 0x1, 505 .sclfrq = 0x0, .scllt = 0xA, .sclht = 0x7, 506 .fast_mode = true, 507 }, 508 { 509 .core_clk = 25000000, .hldt = 0x4, .dbcnt = 0x1, 510 .sclfrq = 0x0, .scllt = 0x7, .sclht = 0x6, 511 .fast_mode = true, 512 }, 513 { 514 .core_clk = 24000000, .hldt = 0x7, .dbcnt = 0x1, 515 .sclfrq = 0x0, .scllt = 0x8, .sclht = 0x5, 516 .fast_mode = true, 517 }, 518 { 519 .core_clk = 20000000, .hldt = 0x4, .dbcnt = 0x1, 520 .sclfrq = 0x0, .scllt = 0x6, .sclht = 0x4, 521 .fast_mode = true, 522 }, 523 }; 524 525 struct npcm_i2c_data { 526 u8 fifo_size; 527 u32 segctl_init_val; 528 u8 txf_sts_tx_bytes; 529 u8 rxf_sts_rx_bytes; 530 u8 rxf_ctl_last_pec; 531 }; 532 533 static const struct npcm_i2c_data npxm7xx_i2c_data = { 534 .fifo_size = 16, 535 .segctl_init_val = 0x0333F000, 536 .txf_sts_tx_bytes = GENMASK(4, 0), 537 .rxf_sts_rx_bytes = GENMASK(4, 0), 538 .rxf_ctl_last_pec = BIT(5), 539 }; 540 541 static const struct npcm_i2c_data npxm8xx_i2c_data = { 542 .fifo_size = 32, 543 .segctl_init_val = 0x9333F000, 544 .txf_sts_tx_bytes = GENMASK(5, 0), 545 .rxf_sts_rx_bytes = GENMASK(5, 0), 546 .rxf_ctl_last_pec = BIT(7), 547 }; 548 549 /* Status of one I2C module */ 550 struct npcm_i2c { 551 struct i2c_adapter adap; 552 struct device *dev; 553 unsigned char __iomem *reg; 554 const struct npcm_i2c_data *data; 555 spinlock_t lock; /* IRQ synchronization */ 556 struct completion cmd_complete; 557 int cmd_err; 558 struct i2c_msg *msgs; 559 int msgs_num; 560 int num; 561 u32 apb_clk; 562 struct i2c_bus_recovery_info rinfo; 563 enum i2c_state state; 564 enum i2c_oper operation; 565 enum i2c_mode master_or_slave; 566 enum i2c_state_ind stop_ind; 567 u8 dest_addr; 568 u8 *rd_buf; 569 u16 rd_size; 570 u16 rd_ind; 571 u8 *wr_buf; 572 u16 wr_size; 573 u16 wr_ind; 574 bool fifo_use; 575 u16 PEC_mask; /* PEC bit mask per slave address */ 576 bool PEC_use; 577 bool read_block_use; 578 unsigned long int_time_stamp; 579 unsigned long bus_freq; /* in Hz */ 580 #if IS_ENABLED(CONFIG_I2C_SLAVE) 581 u8 own_slave_addr; 582 struct i2c_client *slave; 583 int slv_rd_size; 584 int slv_rd_ind; 585 int slv_wr_size; 586 int slv_wr_ind; 587 u8 slv_rd_buf[MAX_I2C_HW_FIFO_SIZE]; 588 u8 slv_wr_buf[MAX_I2C_HW_FIFO_SIZE]; 589 #endif 590 struct dentry *debugfs; /* debugfs device directory */ 591 u64 ber_cnt; 592 u64 rec_succ_cnt; 593 u64 rec_fail_cnt; 594 u64 nack_cnt; 595 u64 timeout_cnt; 596 u64 tx_complete_cnt; 597 bool ber_state; /* Indicate the bus error state */ 598 }; 599 npcm_i2c_select_bank(struct npcm_i2c * bus,enum i2c_bank bank)600 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus, 601 enum i2c_bank bank) 602 { 603 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); 604 605 if (bank == I2C_BANK_0) 606 i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL; 607 else 608 i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL; 609 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); 610 } 611 npcm_i2c_init_params(struct npcm_i2c * bus)612 static void npcm_i2c_init_params(struct npcm_i2c *bus) 613 { 614 bus->stop_ind = I2C_NO_STATUS_IND; 615 bus->rd_size = 0; 616 bus->wr_size = 0; 617 bus->rd_ind = 0; 618 bus->wr_ind = 0; 619 bus->read_block_use = false; 620 bus->int_time_stamp = 0; 621 bus->PEC_use = false; 622 bus->PEC_mask = 0; 623 #if IS_ENABLED(CONFIG_I2C_SLAVE) 624 if (bus->slave) 625 bus->master_or_slave = I2C_SLAVE; 626 #endif 627 } 628 npcm_i2c_wr_byte(struct npcm_i2c * bus,u8 data)629 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data) 630 { 631 iowrite8(data, bus->reg + NPCM_I2CSDA); 632 } 633 npcm_i2c_rd_byte(struct npcm_i2c * bus)634 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus) 635 { 636 return ioread8(bus->reg + NPCM_I2CSDA); 637 } 638 npcm_i2c_get_SCL(struct i2c_adapter * _adap)639 static int npcm_i2c_get_SCL(struct i2c_adapter *_adap) 640 { 641 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 642 643 return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3)); 644 } 645 npcm_i2c_get_SDA(struct i2c_adapter * _adap)646 static int npcm_i2c_get_SDA(struct i2c_adapter *_adap) 647 { 648 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 649 650 return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3)); 651 } 652 npcm_i2c_get_index(struct npcm_i2c * bus)653 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus) 654 { 655 if (bus->operation == I2C_READ_OPER) 656 return bus->rd_ind; 657 if (bus->operation == I2C_WRITE_OPER) 658 return bus->wr_ind; 659 return 0; 660 } 661 662 /* quick protocol (just address) */ npcm_i2c_is_quick(struct npcm_i2c * bus)663 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus) 664 { 665 return bus->wr_size == 0 && bus->rd_size == 0; 666 } 667 npcm_i2c_disable(struct npcm_i2c * bus)668 static void npcm_i2c_disable(struct npcm_i2c *bus) 669 { 670 u8 i2cctl2; 671 672 #if IS_ENABLED(CONFIG_I2C_SLAVE) 673 int i; 674 675 /* Slave addresses removal */ 676 for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) 677 iowrite8(0, bus->reg + npcm_i2caddr[i]); 678 679 #endif 680 /* Disable module */ 681 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2); 682 i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE; 683 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2); 684 685 bus->state = I2C_DISABLE; 686 } 687 npcm_i2c_enable(struct npcm_i2c * bus)688 static void npcm_i2c_enable(struct npcm_i2c *bus) 689 { 690 u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2); 691 692 i2cctl2 = i2cctl2 | I2CCTL2_ENABLE; 693 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2); 694 bus->state = I2C_IDLE; 695 } 696 697 /* enable\disable end of busy (EOB) interrupts */ npcm_i2c_eob_int(struct npcm_i2c * bus,bool enable)698 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable) 699 { 700 u8 val; 701 702 /* Clear EO_BUSY pending bit: */ 703 val = ioread8(bus->reg + NPCM_I2CCST3); 704 val = val | NPCM_I2CCST3_EO_BUSY; 705 iowrite8(val, bus->reg + NPCM_I2CCST3); 706 707 val = ioread8(bus->reg + NPCM_I2CCTL1); 708 val &= ~NPCM_I2CCTL1_RWS; 709 if (enable) 710 val |= NPCM_I2CCTL1_EOBINTE; 711 else 712 val &= ~NPCM_I2CCTL1_EOBINTE; 713 iowrite8(val, bus->reg + NPCM_I2CCTL1); 714 } 715 npcm_i2c_tx_fifo_empty(struct npcm_i2c * bus)716 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus) 717 { 718 u8 tx_fifo_sts; 719 720 tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS); 721 /* check if TX FIFO is not empty */ 722 if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0) 723 return false; 724 725 /* check if TX FIFO status bit is set: */ 726 return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts); 727 } 728 npcm_i2c_rx_fifo_full(struct npcm_i2c * bus)729 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus) 730 { 731 u8 rx_fifo_sts; 732 733 rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS); 734 /* check if RX FIFO is not empty: */ 735 if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0) 736 return false; 737 738 /* check if rx fifo full status is set: */ 739 return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts); 740 } 741 npcm_i2c_clear_fifo_int(struct npcm_i2c * bus)742 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus) 743 { 744 u8 val; 745 746 val = ioread8(bus->reg + NPCM_I2CFIF_CTS); 747 val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE; 748 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS); 749 } 750 npcm_i2c_clear_tx_fifo(struct npcm_i2c * bus)751 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus) 752 { 753 u8 val; 754 755 val = ioread8(bus->reg + NPCM_I2CTXF_STS); 756 val = val | NPCM_I2CTXF_STS_TX_THST; 757 iowrite8(val, bus->reg + NPCM_I2CTXF_STS); 758 } 759 npcm_i2c_clear_rx_fifo(struct npcm_i2c * bus)760 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus) 761 { 762 u8 val; 763 764 val = ioread8(bus->reg + NPCM_I2CRXF_STS); 765 val = val | NPCM_I2CRXF_STS_RX_THST; 766 iowrite8(val, bus->reg + NPCM_I2CRXF_STS); 767 } 768 npcm_i2c_int_enable(struct npcm_i2c * bus,bool enable)769 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable) 770 { 771 u8 val; 772 773 val = ioread8(bus->reg + NPCM_I2CCTL1); 774 val &= ~NPCM_I2CCTL1_RWS; 775 if (enable) 776 val |= NPCM_I2CCTL1_INTEN; 777 else 778 val &= ~NPCM_I2CCTL1_INTEN; 779 iowrite8(val, bus->reg + NPCM_I2CCTL1); 780 } 781 npcm_i2c_master_start(struct npcm_i2c * bus)782 static inline void npcm_i2c_master_start(struct npcm_i2c *bus) 783 { 784 u8 val; 785 786 val = ioread8(bus->reg + NPCM_I2CCTL1); 787 val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK); 788 val |= NPCM_I2CCTL1_START; 789 iowrite8(val, bus->reg + NPCM_I2CCTL1); 790 } 791 npcm_i2c_master_stop(struct npcm_i2c * bus)792 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus) 793 { 794 u8 val; 795 796 /* 797 * override HW issue: I2C may fail to supply stop condition in Master 798 * Write operation. 799 * Need to delay at least 5 us from the last int, before issueing a stop 800 */ 801 udelay(10); /* function called from interrupt, can't sleep */ 802 val = ioread8(bus->reg + NPCM_I2CCTL1); 803 val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK); 804 val |= NPCM_I2CCTL1_STOP; 805 iowrite8(val, bus->reg + NPCM_I2CCTL1); 806 807 if (!bus->fifo_use) 808 return; 809 810 npcm_i2c_select_bank(bus, I2C_BANK_1); 811 812 if (bus->operation == I2C_READ_OPER) 813 npcm_i2c_clear_rx_fifo(bus); 814 else 815 npcm_i2c_clear_tx_fifo(bus); 816 npcm_i2c_clear_fifo_int(bus); 817 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 818 } 819 npcm_i2c_stall_after_start(struct npcm_i2c * bus,bool stall)820 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall) 821 { 822 u8 val; 823 824 val = ioread8(bus->reg + NPCM_I2CCTL1); 825 val &= ~NPCM_I2CCTL1_RWS; 826 if (stall) 827 val |= NPCM_I2CCTL1_STASTRE; 828 else 829 val &= ~NPCM_I2CCTL1_STASTRE; 830 iowrite8(val, bus->reg + NPCM_I2CCTL1); 831 } 832 npcm_i2c_nack(struct npcm_i2c * bus)833 static inline void npcm_i2c_nack(struct npcm_i2c *bus) 834 { 835 u8 val; 836 837 val = ioread8(bus->reg + NPCM_I2CCTL1); 838 val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START); 839 val |= NPCM_I2CCTL1_ACK; 840 iowrite8(val, bus->reg + NPCM_I2CCTL1); 841 } 842 npcm_i2c_clear_master_status(struct npcm_i2c * bus)843 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus) 844 { 845 u8 val; 846 847 /* Clear NEGACK, STASTR and BER bits */ 848 val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR; 849 iowrite8(val, bus->reg + NPCM_I2CST); 850 } 851 852 #if IS_ENABLED(CONFIG_I2C_SLAVE) npcm_i2c_slave_int_enable(struct npcm_i2c * bus,bool enable)853 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable) 854 { 855 u8 i2cctl1; 856 857 /* enable interrupt on slave match: */ 858 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1); 859 i2cctl1 &= ~NPCM_I2CCTL1_RWS; 860 if (enable) 861 i2cctl1 |= NPCM_I2CCTL1_NMINTE; 862 else 863 i2cctl1 &= ~NPCM_I2CCTL1_NMINTE; 864 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); 865 } 866 npcm_i2c_slave_enable(struct npcm_i2c * bus,enum i2c_addr addr_type,u8 addr,bool enable)867 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type, 868 u8 addr, bool enable) 869 { 870 u8 i2cctl1; 871 u8 i2cctl3; 872 u8 sa_reg; 873 874 sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable); 875 if (addr_type == I2C_GC_ADDR) { 876 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1); 877 if (enable) 878 i2cctl1 |= NPCM_I2CCTL1_GCMEN; 879 else 880 i2cctl1 &= ~NPCM_I2CCTL1_GCMEN; 881 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); 882 return 0; 883 } else if (addr_type == I2C_ARP_ADDR) { 884 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); 885 if (enable) 886 i2cctl3 |= I2CCTL3_ARPMEN; 887 else 888 i2cctl3 &= ~I2CCTL3_ARPMEN; 889 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); 890 return 0; 891 } 892 if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10) 893 dev_err(bus->dev, "try to enable more than 2 SA not supported\n"); 894 895 if (addr_type >= I2C_ARP_ADDR) 896 return -EFAULT; 897 898 /* Set and enable the address */ 899 iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]); 900 npcm_i2c_slave_int_enable(bus, enable); 901 902 return 0; 903 } 904 #endif 905 npcm_i2c_reset(struct npcm_i2c * bus)906 static void npcm_i2c_reset(struct npcm_i2c *bus) 907 { 908 /* 909 * Save I2CCTL1 relevant bits. It is being cleared when the module 910 * is disabled. 911 */ 912 u8 i2cctl1; 913 #if IS_ENABLED(CONFIG_I2C_SLAVE) 914 u8 addr; 915 #endif 916 917 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1); 918 919 npcm_i2c_disable(bus); 920 npcm_i2c_enable(bus); 921 922 /* Restore NPCM_I2CCTL1 Status */ 923 i2cctl1 &= ~NPCM_I2CCTL1_RWS; 924 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); 925 926 /* Clear BB (BUS BUSY) bit */ 927 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 928 iowrite8(0xFF, bus->reg + NPCM_I2CST); 929 930 /* Clear and disable EOB */ 931 npcm_i2c_eob_int(bus, false); 932 933 /* Clear all fifo bits: */ 934 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS); 935 936 #if IS_ENABLED(CONFIG_I2C_SLAVE) 937 if (bus->slave) { 938 addr = bus->slave->addr; 939 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true); 940 } 941 #endif 942 943 /* Clear status bits for spurious interrupts */ 944 npcm_i2c_clear_master_status(bus); 945 946 bus->state = I2C_IDLE; 947 } 948 npcm_i2c_is_master(struct npcm_i2c * bus)949 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus) 950 { 951 return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST)); 952 } 953 npcm_i2c_callback(struct npcm_i2c * bus,enum i2c_state_ind op_status,u16 info)954 static void npcm_i2c_callback(struct npcm_i2c *bus, 955 enum i2c_state_ind op_status, u16 info) 956 { 957 struct i2c_msg *msgs; 958 int msgs_num; 959 bool do_complete = false; 960 961 msgs = bus->msgs; 962 msgs_num = bus->msgs_num; 963 /* 964 * check that transaction was not timed-out, and msgs still 965 * holds a valid value. 966 */ 967 if (!msgs) 968 return; 969 970 if (completion_done(&bus->cmd_complete)) 971 return; 972 973 switch (op_status) { 974 case I2C_MASTER_DONE_IND: 975 bus->cmd_err = bus->msgs_num; 976 if (bus->tx_complete_cnt < ULLONG_MAX) 977 bus->tx_complete_cnt++; 978 fallthrough; 979 case I2C_BLOCK_BYTES_ERR_IND: 980 /* Master tx finished and all transmit bytes were sent */ 981 if (bus->msgs) { 982 if (msgs[0].flags & I2C_M_RD) 983 msgs[0].len = info; 984 else if (msgs_num == 2 && 985 msgs[1].flags & I2C_M_RD) 986 msgs[1].len = info; 987 } 988 do_complete = true; 989 break; 990 case I2C_NACK_IND: 991 /* MASTER transmit got a NACK before tx all bytes */ 992 bus->cmd_err = -ENXIO; 993 do_complete = true; 994 break; 995 case I2C_BUS_ERR_IND: 996 /* Bus error */ 997 bus->cmd_err = -EAGAIN; 998 do_complete = true; 999 break; 1000 case I2C_WAKE_UP_IND: 1001 /* I2C wake up */ 1002 break; 1003 default: 1004 break; 1005 } 1006 1007 bus->operation = I2C_NO_OPER; 1008 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1009 if (bus->slave) 1010 bus->master_or_slave = I2C_SLAVE; 1011 #endif 1012 if (do_complete) 1013 complete(&bus->cmd_complete); 1014 } 1015 npcm_i2c_fifo_usage(struct npcm_i2c * bus)1016 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus) 1017 { 1018 if (bus->operation == I2C_WRITE_OPER) 1019 return (bus->data->txf_sts_tx_bytes & 1020 ioread8(bus->reg + NPCM_I2CTXF_STS)); 1021 if (bus->operation == I2C_READ_OPER) 1022 return (bus->data->rxf_sts_rx_bytes & 1023 ioread8(bus->reg + NPCM_I2CRXF_STS)); 1024 return 0; 1025 } 1026 npcm_i2c_write_to_fifo_master(struct npcm_i2c * bus,u16 max_bytes)1027 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes) 1028 { 1029 u8 size_free_fifo; 1030 1031 /* 1032 * Fill the FIFO, while the FIFO is not full and there are more bytes 1033 * to write 1034 */ 1035 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus); 1036 while (max_bytes-- && size_free_fifo) { 1037 if (bus->wr_ind < bus->wr_size) 1038 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]); 1039 else 1040 npcm_i2c_wr_byte(bus, 0xFF); 1041 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus); 1042 } 1043 } 1044 1045 /* 1046 * npcm_i2c_set_fifo: 1047 * configure the FIFO before using it. If nread is -1 RX FIFO will not be 1048 * configured. same for nwrite 1049 */ npcm_i2c_set_fifo(struct npcm_i2c * bus,int nread,int nwrite)1050 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite) 1051 { 1052 u8 rxf_ctl = 0; 1053 1054 if (!bus->fifo_use) 1055 return; 1056 npcm_i2c_select_bank(bus, I2C_BANK_1); 1057 npcm_i2c_clear_tx_fifo(bus); 1058 npcm_i2c_clear_rx_fifo(bus); 1059 1060 /* configure RX FIFO */ 1061 if (nread > 0) { 1062 rxf_ctl = min_t(int, nread, bus->data->fifo_size); 1063 1064 /* set LAST bit. if LAST is set next FIFO packet is nacked */ 1065 if (nread <= bus->data->fifo_size) 1066 rxf_ctl |= bus->data->rxf_ctl_last_pec; 1067 1068 /* 1069 * if we are about to read the first byte in blk rd mode, 1070 * don't NACK it. If slave returns zero size HW can't NACK 1071 * it immediately, it will read extra byte and then NACK. 1072 */ 1073 if (bus->rd_ind == 0 && bus->read_block_use) { 1074 /* set fifo to read one byte, no last: */ 1075 rxf_ctl = 1; 1076 } 1077 1078 /* set fifo size: */ 1079 iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL); 1080 } 1081 1082 /* configure TX FIFO */ 1083 if (nwrite > 0) { 1084 if (nwrite > bus->data->fifo_size) 1085 /* data to send is more then FIFO size. */ 1086 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL); 1087 else 1088 iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL); 1089 1090 npcm_i2c_clear_tx_fifo(bus); 1091 } 1092 } 1093 npcm_i2c_read_fifo(struct npcm_i2c * bus,u8 bytes_in_fifo)1094 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo) 1095 { 1096 u8 data; 1097 1098 while (bytes_in_fifo--) { 1099 data = npcm_i2c_rd_byte(bus); 1100 if (bus->rd_ind < bus->rd_size) 1101 bus->rd_buf[bus->rd_ind++] = data; 1102 } 1103 } 1104 npcm_i2c_master_abort(struct npcm_i2c * bus)1105 static void npcm_i2c_master_abort(struct npcm_i2c *bus) 1106 { 1107 /* Only current master is allowed to issue a stop condition */ 1108 if (!npcm_i2c_is_master(bus)) 1109 return; 1110 1111 npcm_i2c_eob_int(bus, true); 1112 npcm_i2c_master_stop(bus); 1113 npcm_i2c_clear_master_status(bus); 1114 } 1115 1116 #if IS_ENABLED(CONFIG_I2C_SLAVE) npcm_i2c_get_slave_addr(struct npcm_i2c * bus,enum i2c_addr addr_type)1117 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type) 1118 { 1119 u8 slave_add; 1120 1121 if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10) 1122 dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n"); 1123 1124 slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]); 1125 1126 return slave_add; 1127 } 1128 npcm_i2c_remove_slave_addr(struct npcm_i2c * bus,u8 slave_add)1129 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add) 1130 { 1131 int i; 1132 1133 /* Set the enable bit */ 1134 slave_add |= 0x80; 1135 1136 for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) { 1137 if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add) 1138 iowrite8(0, bus->reg + npcm_i2caddr[i]); 1139 } 1140 1141 return 0; 1142 } 1143 npcm_i2c_write_fifo_slave(struct npcm_i2c * bus,u16 max_bytes)1144 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes) 1145 { 1146 /* 1147 * Fill the FIFO, while the FIFO is not full and there are more bytes 1148 * to write 1149 */ 1150 npcm_i2c_clear_fifo_int(bus); 1151 npcm_i2c_clear_tx_fifo(bus); 1152 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 1153 while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) { 1154 if (bus->slv_wr_size <= 0) 1155 break; 1156 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1); 1157 npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]); 1158 bus->slv_wr_ind++; 1159 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1); 1160 bus->slv_wr_size--; 1161 } 1162 } 1163 npcm_i2c_read_fifo_slave(struct npcm_i2c * bus,u8 bytes_in_fifo)1164 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo) 1165 { 1166 u8 data; 1167 1168 if (!bus->slave) 1169 return; 1170 1171 while (bytes_in_fifo--) { 1172 data = npcm_i2c_rd_byte(bus); 1173 1174 bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1); 1175 bus->slv_rd_buf[bus->slv_rd_ind] = data; 1176 bus->slv_rd_ind++; 1177 1178 /* 1st byte is length in block protocol: */ 1179 if (bus->slv_rd_ind == 1 && bus->read_block_use) 1180 bus->slv_rd_size = data + bus->PEC_use + 1; 1181 } 1182 } 1183 npcm_i2c_slave_get_wr_buf(struct npcm_i2c * bus)1184 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus) 1185 { 1186 int i; 1187 u8 value; 1188 int ind; 1189 int ret = bus->slv_wr_ind; 1190 1191 /* fill a cyclic buffer */ 1192 for (i = 0; i < bus->data->fifo_size; i++) { 1193 if (bus->slv_wr_size >= bus->data->fifo_size) 1194 break; 1195 if (bus->state == I2C_SLAVE_MATCH) { 1196 i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value); 1197 bus->state = I2C_OPER_STARTED; 1198 } else { 1199 i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value); 1200 } 1201 ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1); 1202 bus->slv_wr_buf[ind] = value; 1203 bus->slv_wr_size++; 1204 } 1205 return bus->data->fifo_size - ret; 1206 } 1207 npcm_i2c_slave_send_rd_buf(struct npcm_i2c * bus)1208 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus) 1209 { 1210 int i; 1211 1212 for (i = 0; i < bus->slv_rd_ind; i++) 1213 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED, 1214 &bus->slv_rd_buf[i]); 1215 /* 1216 * once we send bytes up, need to reset the counter of the wr buf 1217 * got data from master (new offset in device), ignore wr fifo: 1218 */ 1219 if (bus->slv_rd_ind) { 1220 bus->slv_wr_size = 0; 1221 bus->slv_wr_ind = 0; 1222 } 1223 1224 bus->slv_rd_ind = 0; 1225 bus->slv_rd_size = bus->adap.quirks->max_read_len; 1226 1227 npcm_i2c_clear_fifo_int(bus); 1228 npcm_i2c_clear_rx_fifo(bus); 1229 } 1230 npcm_i2c_slave_receive(struct npcm_i2c * bus,u16 nread,u8 * read_data)1231 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread, 1232 u8 *read_data) 1233 { 1234 bus->state = I2C_OPER_STARTED; 1235 bus->operation = I2C_READ_OPER; 1236 bus->slv_rd_size = nread; 1237 bus->slv_rd_ind = 0; 1238 1239 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 1240 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL); 1241 npcm_i2c_clear_tx_fifo(bus); 1242 npcm_i2c_clear_rx_fifo(bus); 1243 } 1244 npcm_i2c_slave_xmit(struct npcm_i2c * bus,u16 nwrite,u8 * write_data)1245 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite, 1246 u8 *write_data) 1247 { 1248 if (nwrite == 0) 1249 return; 1250 1251 bus->operation = I2C_WRITE_OPER; 1252 1253 /* get the next buffer */ 1254 npcm_i2c_slave_get_wr_buf(bus); 1255 npcm_i2c_write_fifo_slave(bus, nwrite); 1256 } 1257 1258 /* 1259 * npcm_i2c_slave_wr_buf_sync: 1260 * currently slave IF only supports single byte operations. 1261 * in order to utilize the npcm HW FIFO, the driver will ask for 16 bytes 1262 * at a time, pack them in buffer, and then transmit them all together 1263 * to the FIFO and onward to the bus. 1264 * NACK on read will be once reached to bus->adap->quirks->max_read_len. 1265 * sending a NACK wherever the backend requests for it is not supported. 1266 * the next two functions allow reading to local buffer before writing it all 1267 * to the HW FIFO. 1268 */ npcm_i2c_slave_wr_buf_sync(struct npcm_i2c * bus)1269 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus) 1270 { 1271 int left_in_fifo; 1272 1273 left_in_fifo = bus->data->txf_sts_tx_bytes & 1274 ioread8(bus->reg + NPCM_I2CTXF_STS); 1275 1276 /* fifo already full: */ 1277 if (left_in_fifo >= bus->data->fifo_size || 1278 bus->slv_wr_size >= bus->data->fifo_size) 1279 return; 1280 1281 /* update the wr fifo index back to the untransmitted bytes: */ 1282 bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo; 1283 bus->slv_wr_size = bus->slv_wr_size + left_in_fifo; 1284 1285 if (bus->slv_wr_ind < 0) 1286 bus->slv_wr_ind += bus->data->fifo_size; 1287 } 1288 npcm_i2c_slave_rd_wr(struct npcm_i2c * bus)1289 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus) 1290 { 1291 if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) { 1292 /* 1293 * Slave got an address match with direction bit 1 so it should 1294 * transmit data. Write till the master will NACK 1295 */ 1296 bus->operation = I2C_WRITE_OPER; 1297 npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len, 1298 bus->slv_wr_buf); 1299 } else { 1300 /* 1301 * Slave got an address match with direction bit 0 so it should 1302 * receive data. 1303 * this module does not support saying no to bytes. 1304 * it will always ACK. 1305 */ 1306 bus->operation = I2C_READ_OPER; 1307 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus)); 1308 bus->stop_ind = I2C_SLAVE_RCV_IND; 1309 npcm_i2c_slave_send_rd_buf(bus); 1310 npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len, 1311 bus->slv_rd_buf); 1312 } 1313 } 1314 npcm_i2c_int_slave_handler(struct npcm_i2c * bus)1315 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus) 1316 { 1317 u8 val; 1318 irqreturn_t ret = IRQ_NONE; 1319 u8 i2cst = ioread8(bus->reg + NPCM_I2CST); 1320 1321 /* Slave: A NACK has occurred */ 1322 if (NPCM_I2CST_NEGACK & i2cst) { 1323 bus->stop_ind = I2C_NACK_IND; 1324 npcm_i2c_slave_wr_buf_sync(bus); 1325 if (bus->fifo_use) 1326 /* clear the FIFO */ 1327 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, 1328 bus->reg + NPCM_I2CFIF_CTS); 1329 1330 /* In slave write, NACK is OK, otherwise it is a problem */ 1331 bus->stop_ind = I2C_NO_STATUS_IND; 1332 bus->operation = I2C_NO_OPER; 1333 bus->own_slave_addr = 0xFF; 1334 1335 /* 1336 * Slave has to wait for STOP to decide this is the end 1337 * of the transaction. tx is not yet considered as done 1338 */ 1339 iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST); 1340 1341 ret = IRQ_HANDLED; 1342 } 1343 1344 /* Slave mode: a Bus Error (BER) has been identified */ 1345 if (NPCM_I2CST_BER & i2cst) { 1346 /* 1347 * Check whether bus arbitration or Start or Stop during data 1348 * xfer bus arbitration problem should not result in recovery 1349 */ 1350 bus->stop_ind = I2C_BUS_ERR_IND; 1351 1352 /* wait for bus busy before clear fifo */ 1353 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS); 1354 1355 bus->state = I2C_IDLE; 1356 1357 /* 1358 * in BER case we might get 2 interrupts: one for slave one for 1359 * master ( for a channel which is master\slave switching) 1360 */ 1361 if (completion_done(&bus->cmd_complete) == false) { 1362 bus->cmd_err = -EIO; 1363 complete(&bus->cmd_complete); 1364 } 1365 bus->own_slave_addr = 0xFF; 1366 iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST); 1367 ret = IRQ_HANDLED; 1368 } 1369 1370 /* A Slave Stop Condition has been identified */ 1371 if (NPCM_I2CST_SLVSTP & i2cst) { 1372 u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus); 1373 1374 bus->stop_ind = I2C_SLAVE_DONE_IND; 1375 1376 if (bus->operation == I2C_READ_OPER) 1377 npcm_i2c_read_fifo_slave(bus, bytes_in_fifo); 1378 1379 /* if the buffer is empty nothing will be sent */ 1380 npcm_i2c_slave_send_rd_buf(bus); 1381 1382 /* Slave done transmitting or receiving */ 1383 bus->stop_ind = I2C_NO_STATUS_IND; 1384 1385 /* 1386 * Note, just because we got here, it doesn't mean we through 1387 * away the wr buffer. 1388 * we keep it until the next received offset. 1389 */ 1390 bus->operation = I2C_NO_OPER; 1391 bus->own_slave_addr = 0xFF; 1392 i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0); 1393 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST); 1394 if (bus->fifo_use) { 1395 npcm_i2c_clear_fifo_int(bus); 1396 npcm_i2c_clear_rx_fifo(bus); 1397 npcm_i2c_clear_tx_fifo(bus); 1398 1399 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, 1400 bus->reg + NPCM_I2CFIF_CTS); 1401 } 1402 bus->state = I2C_IDLE; 1403 ret = IRQ_HANDLED; 1404 } 1405 1406 /* restart condition occurred and Rx-FIFO was not empty */ 1407 if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR, 1408 ioread8(bus->reg + NPCM_I2CFIF_CTS))) { 1409 bus->stop_ind = I2C_SLAVE_RESTART_IND; 1410 bus->master_or_slave = I2C_SLAVE; 1411 if (bus->operation == I2C_READ_OPER) 1412 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus)); 1413 bus->operation = I2C_WRITE_OPER; 1414 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL); 1415 val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR | 1416 NPCM_I2CFIF_CTS_RXF_TXE; 1417 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS); 1418 npcm_i2c_slave_rd_wr(bus); 1419 ret = IRQ_HANDLED; 1420 } 1421 1422 /* A Slave Address Match has been identified */ 1423 if (NPCM_I2CST_NMATCH & i2cst) { 1424 u8 info = 0; 1425 1426 /* Address match automatically implies slave mode */ 1427 bus->master_or_slave = I2C_SLAVE; 1428 npcm_i2c_clear_fifo_int(bus); 1429 npcm_i2c_clear_rx_fifo(bus); 1430 npcm_i2c_clear_tx_fifo(bus); 1431 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 1432 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL); 1433 if (NPCM_I2CST_XMIT & i2cst) { 1434 bus->operation = I2C_WRITE_OPER; 1435 } else { 1436 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED, 1437 &info); 1438 bus->operation = I2C_READ_OPER; 1439 } 1440 if (bus->own_slave_addr == 0xFF) { 1441 /* Check which type of address match */ 1442 val = ioread8(bus->reg + NPCM_I2CCST); 1443 if (NPCM_I2CCST_MATCH & val) { 1444 u16 addr; 1445 enum i2c_addr eaddr; 1446 u8 i2ccst2; 1447 u8 i2ccst3; 1448 1449 i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3); 1450 i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2); 1451 1452 /* 1453 * the i2c module can response to 10 own SA. 1454 * check which one was addressed by the master. 1455 * respond to the first one. 1456 */ 1457 addr = ((i2ccst3 & 0x07) << 7) | 1458 (i2ccst2 & 0x7F); 1459 info = ffs(addr); 1460 eaddr = (enum i2c_addr)info; 1461 addr = npcm_i2c_get_slave_addr(bus, eaddr); 1462 addr &= 0x7F; 1463 bus->own_slave_addr = addr; 1464 if (bus->PEC_mask & BIT(info)) 1465 bus->PEC_use = true; 1466 else 1467 bus->PEC_use = false; 1468 } else { 1469 if (NPCM_I2CCST_GCMATCH & val) 1470 bus->own_slave_addr = 0; 1471 if (NPCM_I2CCST_ARPMATCH & val) 1472 bus->own_slave_addr = 0x61; 1473 } 1474 } else { 1475 /* 1476 * Slave match can happen in two options: 1477 * 1. Start, SA, read (slave read without further ado) 1478 * 2. Start, SA, read, data, restart, SA, read, ... 1479 * (slave read in fragmented mode) 1480 * 3. Start, SA, write, data, restart, SA, read, .. 1481 * (regular write-read mode) 1482 */ 1483 if ((bus->state == I2C_OPER_STARTED && 1484 bus->operation == I2C_READ_OPER && 1485 bus->stop_ind == I2C_SLAVE_XMIT_IND) || 1486 bus->stop_ind == I2C_SLAVE_RCV_IND) { 1487 /* slave tx after slave rx w/o STOP */ 1488 bus->stop_ind = I2C_SLAVE_RESTART_IND; 1489 } 1490 } 1491 1492 if (NPCM_I2CST_XMIT & i2cst) 1493 bus->stop_ind = I2C_SLAVE_XMIT_IND; 1494 else 1495 bus->stop_ind = I2C_SLAVE_RCV_IND; 1496 bus->state = I2C_SLAVE_MATCH; 1497 npcm_i2c_slave_rd_wr(bus); 1498 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST); 1499 ret = IRQ_HANDLED; 1500 } 1501 1502 /* Slave SDA status is set - tx or rx */ 1503 if ((NPCM_I2CST_SDAST & i2cst) || 1504 (bus->fifo_use && 1505 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) { 1506 npcm_i2c_slave_rd_wr(bus); 1507 iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST); 1508 ret = IRQ_HANDLED; 1509 } /* SDAST */ 1510 1511 /* 1512 * If irq is not one of the above, make sure EOB is disabled and all 1513 * status bits are cleared. 1514 */ 1515 if (ret == IRQ_NONE) { 1516 npcm_i2c_eob_int(bus, false); 1517 npcm_i2c_clear_master_status(bus); 1518 } 1519 1520 return IRQ_HANDLED; 1521 } 1522 npcm_i2c_reg_slave(struct i2c_client * client)1523 static int npcm_i2c_reg_slave(struct i2c_client *client) 1524 { 1525 unsigned long lock_flags; 1526 struct npcm_i2c *bus = i2c_get_adapdata(client->adapter); 1527 1528 bus->slave = client; 1529 1530 if (client->flags & I2C_CLIENT_TEN) 1531 return -EAFNOSUPPORT; 1532 1533 spin_lock_irqsave(&bus->lock, lock_flags); 1534 1535 npcm_i2c_init_params(bus); 1536 bus->slv_rd_size = 0; 1537 bus->slv_wr_size = 0; 1538 bus->slv_rd_ind = 0; 1539 bus->slv_wr_ind = 0; 1540 if (client->flags & I2C_CLIENT_PEC) 1541 bus->PEC_use = true; 1542 1543 dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num, 1544 client->addr, bus->PEC_use); 1545 1546 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true); 1547 npcm_i2c_clear_fifo_int(bus); 1548 npcm_i2c_clear_rx_fifo(bus); 1549 npcm_i2c_clear_tx_fifo(bus); 1550 npcm_i2c_slave_int_enable(bus, true); 1551 1552 spin_unlock_irqrestore(&bus->lock, lock_flags); 1553 return 0; 1554 } 1555 npcm_i2c_unreg_slave(struct i2c_client * client)1556 static int npcm_i2c_unreg_slave(struct i2c_client *client) 1557 { 1558 struct npcm_i2c *bus = client->adapter->algo_data; 1559 unsigned long lock_flags; 1560 1561 spin_lock_irqsave(&bus->lock, lock_flags); 1562 if (!bus->slave) { 1563 spin_unlock_irqrestore(&bus->lock, lock_flags); 1564 return -EINVAL; 1565 } 1566 npcm_i2c_slave_int_enable(bus, false); 1567 npcm_i2c_remove_slave_addr(bus, client->addr); 1568 bus->slave = NULL; 1569 spin_unlock_irqrestore(&bus->lock, lock_flags); 1570 return 0; 1571 } 1572 #endif /* CONFIG_I2C_SLAVE */ 1573 npcm_i2c_master_fifo_read(struct npcm_i2c * bus)1574 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus) 1575 { 1576 int rcount; 1577 int fifo_bytes; 1578 enum i2c_state_ind ind = I2C_MASTER_DONE_IND; 1579 1580 fifo_bytes = npcm_i2c_fifo_usage(bus); 1581 rcount = bus->rd_size - bus->rd_ind; 1582 1583 /* 1584 * In order not to change the RX_TRH during transaction (we found that 1585 * this might be problematic if it takes too much time to read the FIFO) 1586 * we read the data in the following way. If the number of bytes to 1587 * read == FIFO Size + C (where C < FIFO Size)then first read C bytes 1588 * and in the next int we read rest of the data. 1589 */ 1590 if (rcount < (2 * bus->data->fifo_size) && rcount > bus->data->fifo_size) 1591 fifo_bytes = rcount - bus->data->fifo_size; 1592 1593 if (rcount <= fifo_bytes) { 1594 /* last bytes are about to be read - end of tx */ 1595 bus->state = I2C_STOP_PENDING; 1596 bus->stop_ind = ind; 1597 npcm_i2c_eob_int(bus, true); 1598 /* Stop should be set before reading last byte. */ 1599 npcm_i2c_master_stop(bus); 1600 npcm_i2c_read_fifo(bus, fifo_bytes); 1601 } else { 1602 npcm_i2c_read_fifo(bus, fifo_bytes); 1603 rcount = bus->rd_size - bus->rd_ind; 1604 npcm_i2c_set_fifo(bus, rcount, -1); 1605 } 1606 } 1607 npcm_i2c_irq_master_handler_write(struct npcm_i2c * bus)1608 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus) 1609 { 1610 u16 wcount; 1611 1612 if (bus->fifo_use) 1613 npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */ 1614 1615 /* Master write operation - last byte handling */ 1616 if (bus->wr_ind == bus->wr_size) { 1617 if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0) 1618 /* 1619 * No more bytes to send (to add to the FIFO), 1620 * however the FIFO is not empty yet. It is 1621 * still in the middle of tx. Currently there's nothing 1622 * to do except for waiting to the end of the tx 1623 * We will get an int when the FIFO will get empty. 1624 */ 1625 return; 1626 1627 if (bus->rd_size == 0) { 1628 /* all bytes have been written, in wr only operation */ 1629 npcm_i2c_eob_int(bus, true); 1630 bus->state = I2C_STOP_PENDING; 1631 bus->stop_ind = I2C_MASTER_DONE_IND; 1632 npcm_i2c_master_stop(bus); 1633 /* Clear SDA Status bit (by writing dummy byte) */ 1634 npcm_i2c_wr_byte(bus, 0xFF); 1635 1636 } else { 1637 /* last write-byte written on previous int - restart */ 1638 npcm_i2c_set_fifo(bus, bus->rd_size, -1); 1639 /* Generate repeated start upon next write to SDA */ 1640 npcm_i2c_master_start(bus); 1641 1642 /* 1643 * Receiving one byte only - stall after successful 1644 * completion of send address byte. If we NACK here, and 1645 * slave doesn't ACK the address, we might 1646 * unintentionally NACK the next multi-byte read. 1647 */ 1648 if (bus->rd_size == 1) 1649 npcm_i2c_stall_after_start(bus, true); 1650 1651 /* Next int will occur on read */ 1652 bus->operation = I2C_READ_OPER; 1653 /* send the slave address in read direction */ 1654 npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1); 1655 } 1656 } else { 1657 /* write next byte not last byte and not slave address */ 1658 if (!bus->fifo_use || bus->wr_size == 1) { 1659 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]); 1660 } else { 1661 wcount = bus->wr_size - bus->wr_ind; 1662 npcm_i2c_set_fifo(bus, -1, wcount); 1663 if (wcount) 1664 npcm_i2c_write_to_fifo_master(bus, wcount); 1665 } 1666 } 1667 } 1668 npcm_i2c_irq_master_handler_read(struct npcm_i2c * bus)1669 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus) 1670 { 1671 u16 block_extra_bytes_size; 1672 u8 data; 1673 1674 /* added bytes to the packet: */ 1675 block_extra_bytes_size = bus->read_block_use + bus->PEC_use; 1676 1677 /* 1678 * Perform master read, distinguishing between last byte and the rest of 1679 * the bytes. The last byte should be read when the clock is stopped 1680 */ 1681 if (bus->rd_ind == 0) { /* first byte handling: */ 1682 if (bus->read_block_use) { 1683 /* first byte in block protocol is the size: */ 1684 data = npcm_i2c_rd_byte(bus); 1685 data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX); 1686 bus->rd_size = data + block_extra_bytes_size; 1687 bus->rd_buf[bus->rd_ind++] = data; 1688 1689 /* clear RX FIFO interrupt status: */ 1690 if (bus->fifo_use) { 1691 data = ioread8(bus->reg + NPCM_I2CFIF_CTS); 1692 data = data | NPCM_I2CFIF_CTS_RXF_TXE; 1693 iowrite8(data, bus->reg + NPCM_I2CFIF_CTS); 1694 } 1695 1696 npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1); 1697 npcm_i2c_stall_after_start(bus, false); 1698 } else { 1699 npcm_i2c_clear_tx_fifo(bus); 1700 npcm_i2c_master_fifo_read(bus); 1701 } 1702 } else { 1703 if (bus->rd_size == block_extra_bytes_size && 1704 bus->read_block_use) { 1705 bus->state = I2C_STOP_PENDING; 1706 bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND; 1707 bus->cmd_err = -EIO; 1708 npcm_i2c_eob_int(bus, true); 1709 npcm_i2c_master_stop(bus); 1710 npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus)); 1711 } else { 1712 npcm_i2c_master_fifo_read(bus); 1713 } 1714 } 1715 } 1716 npcm_i2c_irq_handle_nmatch(struct npcm_i2c * bus)1717 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus) 1718 { 1719 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST); 1720 npcm_i2c_nack(bus); 1721 bus->stop_ind = I2C_BUS_ERR_IND; 1722 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus)); 1723 } 1724 1725 /* A NACK has occurred */ npcm_i2c_irq_handle_nack(struct npcm_i2c * bus)1726 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus) 1727 { 1728 u8 val; 1729 1730 if (bus->nack_cnt < ULLONG_MAX) 1731 bus->nack_cnt++; 1732 1733 if (bus->fifo_use) { 1734 /* 1735 * if there are still untransmitted bytes in TX FIFO 1736 * reduce them from wr_ind 1737 */ 1738 if (bus->operation == I2C_WRITE_OPER) 1739 bus->wr_ind -= npcm_i2c_fifo_usage(bus); 1740 1741 /* clear the FIFO */ 1742 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS); 1743 } 1744 1745 /* In master write operation, got unexpected NACK */ 1746 bus->stop_ind = I2C_NACK_IND; 1747 /* Only current master is allowed to issue Stop Condition */ 1748 if (npcm_i2c_is_master(bus)) { 1749 /* stopping in the middle */ 1750 npcm_i2c_eob_int(bus, false); 1751 npcm_i2c_master_stop(bus); 1752 1753 /* Clear SDA Status bit (by reading dummy byte) */ 1754 npcm_i2c_rd_byte(bus); 1755 1756 /* 1757 * The bus is released from stall only after the SW clears 1758 * NEGACK bit. Then a Stop condition is sent. 1759 */ 1760 npcm_i2c_clear_master_status(bus); 1761 readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val, 1762 !(val & NPCM_I2CCST_BUSY), 10, 200); 1763 /* Verify no status bits are still set after bus is released */ 1764 npcm_i2c_clear_master_status(bus); 1765 } 1766 bus->state = I2C_IDLE; 1767 1768 /* 1769 * In Master mode, NACK should be cleared only after STOP. 1770 * In such case, the bus is released from stall only after the 1771 * software clears NACK bit. Then a Stop condition is sent. 1772 */ 1773 npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind); 1774 } 1775 1776 /* Master mode: a Bus Error has been identified */ npcm_i2c_irq_handle_ber(struct npcm_i2c * bus)1777 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus) 1778 { 1779 if (bus->ber_cnt < ULLONG_MAX) 1780 bus->ber_cnt++; 1781 bus->stop_ind = I2C_BUS_ERR_IND; 1782 if (npcm_i2c_is_master(bus)) { 1783 npcm_i2c_master_abort(bus); 1784 } else { 1785 bus->ber_state = true; 1786 npcm_i2c_clear_master_status(bus); 1787 1788 /* Clear BB (BUS BUSY) bit */ 1789 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 1790 1791 bus->cmd_err = -EAGAIN; 1792 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus)); 1793 } 1794 bus->state = I2C_IDLE; 1795 } 1796 1797 /* EOB: a master End Of Busy (meaning STOP completed) */ npcm_i2c_irq_handle_eob(struct npcm_i2c * bus)1798 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus) 1799 { 1800 npcm_i2c_eob_int(bus, false); 1801 bus->state = I2C_IDLE; 1802 npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind); 1803 } 1804 1805 /* Address sent and requested stall occurred (Master mode) */ npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c * bus)1806 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus) 1807 { 1808 if (npcm_i2c_is_quick(bus)) { 1809 bus->state = I2C_STOP_PENDING; 1810 bus->stop_ind = I2C_MASTER_DONE_IND; 1811 npcm_i2c_eob_int(bus, true); 1812 npcm_i2c_master_stop(bus); 1813 } else if ((bus->rd_size == 1) && !bus->read_block_use) { 1814 /* 1815 * Receiving one byte only - set NACK after ensuring 1816 * slave ACKed the address byte. 1817 */ 1818 npcm_i2c_nack(bus); 1819 } 1820 1821 /* Reset stall-after-address-byte */ 1822 npcm_i2c_stall_after_start(bus, false); 1823 1824 /* Clear stall only after setting STOP */ 1825 iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST); 1826 } 1827 1828 /* SDA status is set - TX or RX, master */ npcm_i2c_irq_handle_sda(struct npcm_i2c * bus,u8 i2cst)1829 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst) 1830 { 1831 u8 fif_cts; 1832 1833 if (!npcm_i2c_is_master(bus)) 1834 return; 1835 1836 if (bus->state == I2C_IDLE) { 1837 bus->stop_ind = I2C_WAKE_UP_IND; 1838 1839 if (npcm_i2c_is_quick(bus) || bus->read_block_use) 1840 /* 1841 * Need to stall after successful 1842 * completion of sending address byte 1843 */ 1844 npcm_i2c_stall_after_start(bus, true); 1845 else 1846 npcm_i2c_stall_after_start(bus, false); 1847 1848 /* 1849 * Receiving one byte only - stall after successful completion 1850 * of sending address byte If we NACK here, and slave doesn't 1851 * ACK the address, we might unintentionally NACK the next 1852 * multi-byte read 1853 */ 1854 if (bus->wr_size == 0 && bus->rd_size == 1) 1855 npcm_i2c_stall_after_start(bus, true); 1856 1857 /* Initiate I2C master tx */ 1858 1859 /* select bank 1 for FIFO regs */ 1860 npcm_i2c_select_bank(bus, I2C_BANK_1); 1861 1862 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS); 1863 fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR; 1864 1865 /* clear FIFO and relevant status bits. */ 1866 fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO; 1867 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS); 1868 1869 /* re-enable */ 1870 fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE; 1871 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS); 1872 1873 /* 1874 * Configure the FIFO threshold: 1875 * according to the needed # of bytes to read. 1876 * Note: due to HW limitation can't config the rx fifo before it 1877 * got and ACK on the restart. LAST bit will not be reset unless 1878 * RX completed. It will stay set on the next tx. 1879 */ 1880 if (bus->wr_size) 1881 npcm_i2c_set_fifo(bus, -1, bus->wr_size); 1882 else 1883 npcm_i2c_set_fifo(bus, bus->rd_size, -1); 1884 1885 bus->state = I2C_OPER_STARTED; 1886 1887 if (npcm_i2c_is_quick(bus) || bus->wr_size) 1888 npcm_i2c_wr_byte(bus, bus->dest_addr); 1889 else 1890 npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0)); 1891 /* SDA interrupt, after start\restart */ 1892 } else { 1893 if (bus->operation == I2C_WRITE_OPER) 1894 npcm_i2c_irq_master_handler_write(bus); 1895 else if (bus->operation == I2C_READ_OPER) 1896 npcm_i2c_irq_master_handler_read(bus); 1897 } 1898 } 1899 npcm_i2c_int_master_handler(struct npcm_i2c * bus)1900 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus) 1901 { 1902 u8 i2cst; 1903 int ret = -EIO; 1904 1905 i2cst = ioread8(bus->reg + NPCM_I2CST); 1906 1907 if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) { 1908 npcm_i2c_irq_handle_nmatch(bus); 1909 return 0; 1910 } 1911 /* A NACK has occurred */ 1912 if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) { 1913 npcm_i2c_irq_handle_nack(bus); 1914 return 0; 1915 } 1916 1917 /* Master mode: a Bus Error has been identified */ 1918 if (FIELD_GET(NPCM_I2CST_BER, i2cst)) { 1919 npcm_i2c_irq_handle_ber(bus); 1920 return 0; 1921 } 1922 1923 /* EOB: a master End Of Busy (meaning STOP completed) */ 1924 if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE, 1925 ioread8(bus->reg + NPCM_I2CCTL1)) == 1) && 1926 (FIELD_GET(NPCM_I2CCST3_EO_BUSY, 1927 ioread8(bus->reg + NPCM_I2CCST3)))) { 1928 npcm_i2c_irq_handle_eob(bus); 1929 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1930 /* reenable slave if it was enabled */ 1931 if (bus->slave) 1932 iowrite8(bus->slave->addr | NPCM_I2CADDR_SAEN, 1933 bus->reg + NPCM_I2CADDR1); 1934 #endif 1935 return 0; 1936 } 1937 1938 /* Address sent and requested stall occurred (Master mode) */ 1939 if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) { 1940 npcm_i2c_irq_handle_stall_after_start(bus); 1941 ret = 0; 1942 } 1943 1944 /* SDA status is set - TX or RX, master */ 1945 if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) || 1946 (bus->fifo_use && 1947 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) { 1948 npcm_i2c_irq_handle_sda(bus, i2cst); 1949 ret = 0; 1950 } 1951 1952 return ret; 1953 } 1954 1955 /* recovery using TGCLK functionality of the module */ npcm_i2c_recovery_tgclk(struct i2c_adapter * _adap)1956 static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap) 1957 { 1958 u8 val; 1959 u8 fif_cts; 1960 bool done = false; 1961 int status = -ENOTRECOVERABLE; 1962 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 1963 /* Allow 3 bytes (27 toggles) to be read from the slave: */ 1964 int iter = 27; 1965 1966 if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) { 1967 dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck", 1968 bus->num, bus->dest_addr); 1969 npcm_i2c_reset(bus); 1970 bus->ber_state = false; 1971 return 0; 1972 } 1973 1974 npcm_i2c_int_enable(bus, false); 1975 npcm_i2c_disable(bus); 1976 npcm_i2c_enable(bus); 1977 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 1978 npcm_i2c_clear_tx_fifo(bus); 1979 npcm_i2c_clear_rx_fifo(bus); 1980 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL); 1981 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 1982 npcm_i2c_stall_after_start(bus, false); 1983 1984 /* select bank 1 for FIFO regs */ 1985 npcm_i2c_select_bank(bus, I2C_BANK_1); 1986 1987 /* clear FIFO and relevant status bits. */ 1988 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS); 1989 fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR; 1990 fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO; 1991 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS); 1992 npcm_i2c_set_fifo(bus, -1, 0); 1993 1994 /* Repeat the following sequence until SDA is released */ 1995 do { 1996 /* Issue a single SCL toggle */ 1997 iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST); 1998 usleep_range(20, 30); 1999 /* If SDA line is inactive (high), stop */ 2000 if (npcm_i2c_get_SDA(_adap)) { 2001 done = true; 2002 status = 0; 2003 } 2004 } while (!done && iter--); 2005 2006 /* If SDA line is released: send start-addr-stop, to re-sync. */ 2007 if (npcm_i2c_get_SDA(_adap)) { 2008 /* Send an address byte in write direction: */ 2009 npcm_i2c_wr_byte(bus, bus->dest_addr); 2010 npcm_i2c_master_start(bus); 2011 /* Wait until START condition is sent */ 2012 status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val, 2013 20, 200); 2014 /* If START condition was sent */ 2015 if (npcm_i2c_is_master(bus) > 0) { 2016 usleep_range(20, 30); 2017 npcm_i2c_master_stop(bus); 2018 usleep_range(200, 500); 2019 } 2020 } 2021 npcm_i2c_reset(bus); 2022 npcm_i2c_int_enable(bus, true); 2023 2024 if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) 2025 status = 0; 2026 else 2027 status = -ENOTRECOVERABLE; 2028 if (status) { 2029 if (bus->rec_fail_cnt < ULLONG_MAX) 2030 bus->rec_fail_cnt++; 2031 } else { 2032 if (bus->rec_succ_cnt < ULLONG_MAX) 2033 bus->rec_succ_cnt++; 2034 } 2035 bus->ber_state = false; 2036 return status; 2037 } 2038 2039 /* recovery using bit banging functionality of the module */ npcm_i2c_recovery_init(struct i2c_adapter * _adap)2040 static void npcm_i2c_recovery_init(struct i2c_adapter *_adap) 2041 { 2042 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 2043 struct i2c_bus_recovery_info *rinfo = &bus->rinfo; 2044 2045 rinfo->recover_bus = npcm_i2c_recovery_tgclk; 2046 2047 /* 2048 * npcm i2c HW allows direct reading of SCL and SDA. 2049 * However, it does not support setting SCL and SDA directly. 2050 * The recovery function can toggle SCL when SDA is low (but not set) 2051 * Getter functions used internally, and can be used externally. 2052 */ 2053 rinfo->get_scl = npcm_i2c_get_SCL; 2054 rinfo->get_sda = npcm_i2c_get_SDA; 2055 _adap->bus_recovery_info = rinfo; 2056 } 2057 2058 /* SCLFRQ min/max field values */ 2059 #define SCLFRQ_MIN 10 2060 #define SCLFRQ_MAX 511 2061 #define clk_coef(freq, mul) DIV_ROUND_UP((freq) * (mul), 1000000) 2062 2063 /* 2064 * npcm_i2c_init_clk: init HW timing parameters. 2065 * NPCM7XX i2c module timing parameters are dependent on module core clk (APB) 2066 * and bus frequency. 2067 * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric. 2068 * 400kHz bus requires asymmetric HT and LT. A different equation is recommended 2069 * by the HW designer, given core clock range (equations in comments below). 2070 * 2071 */ npcm_i2c_init_clk(struct npcm_i2c * bus,u32 bus_freq_hz)2072 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz) 2073 { 2074 struct smb_timing_t *smb_timing; 2075 u8 scl_table_cnt = 0, table_size = 0; 2076 u8 fast_mode = 0; 2077 2078 bus->bus_freq = bus_freq_hz; 2079 2080 switch (bus_freq_hz) { 2081 case I2C_MAX_STANDARD_MODE_FREQ: 2082 smb_timing = smb_timing_100khz; 2083 table_size = ARRAY_SIZE(smb_timing_100khz); 2084 break; 2085 case I2C_MAX_FAST_MODE_FREQ: 2086 smb_timing = smb_timing_400khz; 2087 table_size = ARRAY_SIZE(smb_timing_400khz); 2088 fast_mode = I2CCTL3_400K_MODE; 2089 break; 2090 case I2C_MAX_FAST_MODE_PLUS_FREQ: 2091 smb_timing = smb_timing_1000khz; 2092 table_size = ARRAY_SIZE(smb_timing_1000khz); 2093 fast_mode = I2CCTL3_400K_MODE; 2094 break; 2095 default: 2096 return -EINVAL; 2097 } 2098 2099 for (scl_table_cnt = 0; scl_table_cnt < table_size; scl_table_cnt++) 2100 if (bus->apb_clk >= smb_timing[scl_table_cnt].core_clk) 2101 break; 2102 2103 if (scl_table_cnt == table_size) 2104 return -EINVAL; 2105 2106 /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */ 2107 iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, smb_timing[scl_table_cnt].sclfrq & 0x7F), 2108 bus->reg + NPCM_I2CCTL2); 2109 2110 /* bits [8:7] are in I2CCTL3 reg */ 2111 iowrite8(FIELD_PREP(I2CCTL3_SCLFRQ8_7, (smb_timing[scl_table_cnt].sclfrq >> 7) & 0x3) | 2112 fast_mode, 2113 bus->reg + NPCM_I2CCTL3); 2114 2115 /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */ 2116 npcm_i2c_select_bank(bus, I2C_BANK_0); 2117 2118 if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) { 2119 /* 2120 * Set SCL Low/High Time: 2121 * k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2 2122 * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2 2123 */ 2124 iowrite8(smb_timing[scl_table_cnt].scllt, bus->reg + NPCM_I2CSCLLT); 2125 iowrite8(smb_timing[scl_table_cnt].sclht, bus->reg + NPCM_I2CSCLHT); 2126 2127 iowrite8(smb_timing[scl_table_cnt].dbcnt, bus->reg + NPCM_I2CCTL5); 2128 } 2129 2130 iowrite8(smb_timing[scl_table_cnt].hldt, bus->reg + NPCM_I2CCTL4); 2131 2132 /* Return to Bank 1, and stay there by default: */ 2133 npcm_i2c_select_bank(bus, I2C_BANK_1); 2134 2135 return 0; 2136 } 2137 npcm_i2c_init_module(struct npcm_i2c * bus,enum i2c_mode mode,u32 bus_freq_hz)2138 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode, 2139 u32 bus_freq_hz) 2140 { 2141 u8 val; 2142 int ret; 2143 2144 /* Check whether module already enabled or frequency is out of bounds */ 2145 if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) || 2146 bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ) 2147 return -EINVAL; 2148 2149 npcm_i2c_int_enable(bus, false); 2150 npcm_i2c_disable(bus); 2151 2152 /* Configure FIFO mode : */ 2153 if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) { 2154 bus->fifo_use = true; 2155 npcm_i2c_select_bank(bus, I2C_BANK_0); 2156 val = ioread8(bus->reg + NPCM_I2CFIF_CTL); 2157 val |= NPCM_I2CFIF_CTL_FIFO_EN; 2158 iowrite8(val, bus->reg + NPCM_I2CFIF_CTL); 2159 npcm_i2c_select_bank(bus, I2C_BANK_1); 2160 } else { 2161 bus->fifo_use = false; 2162 } 2163 2164 /* Configure I2C module clock frequency */ 2165 ret = npcm_i2c_init_clk(bus, bus_freq_hz); 2166 if (ret) { 2167 dev_err(bus->dev, "npcm_i2c_init_clk failed\n"); 2168 return ret; 2169 } 2170 2171 /* Enable module (before configuring CTL1) */ 2172 npcm_i2c_enable(bus); 2173 bus->state = I2C_IDLE; 2174 val = ioread8(bus->reg + NPCM_I2CCTL1); 2175 val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS; 2176 iowrite8(val, bus->reg + NPCM_I2CCTL1); 2177 2178 npcm_i2c_reset(bus); 2179 2180 /* Check HW is OK: SDA and SCL should be high at this point. */ 2181 if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) { 2182 dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num); 2183 dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap), 2184 npcm_i2c_get_SCL(&bus->adap)); 2185 return -ENXIO; 2186 } 2187 2188 npcm_i2c_int_enable(bus, true); 2189 return 0; 2190 } 2191 __npcm_i2c_init(struct npcm_i2c * bus,struct platform_device * pdev)2192 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev) 2193 { 2194 u32 clk_freq_hz; 2195 int ret; 2196 2197 /* Initialize the internal data structures */ 2198 bus->state = I2C_DISABLE; 2199 bus->master_or_slave = I2C_SLAVE; 2200 bus->int_time_stamp = 0; 2201 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2202 bus->slave = NULL; 2203 #endif 2204 2205 ret = device_property_read_u32(&pdev->dev, "clock-frequency", 2206 &clk_freq_hz); 2207 if (ret) { 2208 dev_info(&pdev->dev, "Could not read clock-frequency property"); 2209 clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 2210 } 2211 2212 ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz); 2213 if (ret) { 2214 dev_err(&pdev->dev, "npcm_i2c_init_module failed\n"); 2215 return ret; 2216 } 2217 2218 return 0; 2219 } 2220 npcm_i2c_bus_irq(int irq,void * dev_id)2221 static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id) 2222 { 2223 struct npcm_i2c *bus = dev_id; 2224 2225 if (npcm_i2c_is_master(bus)) 2226 bus->master_or_slave = I2C_MASTER; 2227 2228 if (bus->master_or_slave == I2C_MASTER) { 2229 bus->int_time_stamp = jiffies; 2230 if (!npcm_i2c_int_master_handler(bus)) 2231 return IRQ_HANDLED; 2232 } 2233 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2234 if (bus->slave) { 2235 bus->master_or_slave = I2C_SLAVE; 2236 if (npcm_i2c_int_slave_handler(bus)) 2237 return IRQ_HANDLED; 2238 } 2239 #endif 2240 /* Clear status bits for spurious interrupts */ 2241 npcm_i2c_clear_master_status(bus); 2242 2243 return IRQ_HANDLED; 2244 } 2245 npcm_i2c_master_start_xmit(struct npcm_i2c * bus,u16 nwrite,u16 nread,u8 * write_data,u8 * read_data,bool use_PEC,bool use_read_block)2246 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus, 2247 u16 nwrite, u16 nread, 2248 u8 *write_data, u8 *read_data, 2249 bool use_PEC, bool use_read_block) 2250 { 2251 if (bus->state != I2C_IDLE) { 2252 bus->cmd_err = -EBUSY; 2253 return false; 2254 } 2255 bus->wr_buf = write_data; 2256 bus->wr_size = nwrite; 2257 bus->wr_ind = 0; 2258 bus->rd_buf = read_data; 2259 bus->rd_size = nread; 2260 bus->rd_ind = 0; 2261 bus->PEC_use = 0; 2262 2263 /* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */ 2264 if (nread) 2265 bus->PEC_use = use_PEC; 2266 2267 bus->read_block_use = use_read_block; 2268 if (nread && !nwrite) 2269 bus->operation = I2C_READ_OPER; 2270 else 2271 bus->operation = I2C_WRITE_OPER; 2272 if (bus->fifo_use) { 2273 u8 i2cfif_cts; 2274 2275 npcm_i2c_select_bank(bus, I2C_BANK_1); 2276 /* clear FIFO and relevant status bits. */ 2277 i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS); 2278 i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR; 2279 i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO; 2280 iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS); 2281 } 2282 2283 bus->state = I2C_IDLE; 2284 npcm_i2c_stall_after_start(bus, true); 2285 npcm_i2c_master_start(bus); 2286 return true; 2287 } 2288 npcm_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)2289 static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 2290 int num) 2291 { 2292 struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap); 2293 struct i2c_msg *msg0, *msg1; 2294 unsigned long time_left, flags; 2295 u16 nwrite, nread; 2296 u8 *write_data, *read_data; 2297 unsigned long timeout; 2298 bool read_block = false; 2299 bool read_PEC = false; 2300 u8 bus_busy; 2301 unsigned long timeout_usec; 2302 2303 if (bus->state == I2C_DISABLE) { 2304 dev_err(bus->dev, "I2C%d module is disabled", bus->num); 2305 return -EINVAL; 2306 } 2307 2308 msg0 = &msgs[0]; 2309 if (msg0->flags & I2C_M_RD) { /* read */ 2310 nwrite = 0; 2311 write_data = NULL; 2312 read_data = msg0->buf; 2313 if (msg0->flags & I2C_M_RECV_LEN) { 2314 nread = 1; 2315 read_block = true; 2316 if (msg0->flags & I2C_CLIENT_PEC) 2317 read_PEC = true; 2318 } else { 2319 nread = msg0->len; 2320 } 2321 } else { /* write */ 2322 nwrite = msg0->len; 2323 write_data = msg0->buf; 2324 nread = 0; 2325 read_data = NULL; 2326 if (num == 2) { 2327 msg1 = &msgs[1]; 2328 read_data = msg1->buf; 2329 if (msg1->flags & I2C_M_RECV_LEN) { 2330 nread = 1; 2331 read_block = true; 2332 if (msg1->flags & I2C_CLIENT_PEC) 2333 read_PEC = true; 2334 } else { 2335 nread = msg1->len; 2336 read_block = false; 2337 } 2338 } 2339 } 2340 2341 if (nwrite >= 32 * 1024 || nread >= 32 * 1024) { 2342 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num); 2343 return -EINVAL; 2344 } 2345 2346 time_left = jiffies + bus->adap.timeout / bus->adap.retries + 1; 2347 do { 2348 /* 2349 * we must clear slave address immediately when the bus is not 2350 * busy, so we spinlock it, but we don't keep the lock for the 2351 * entire while since it is too long. 2352 */ 2353 spin_lock_irqsave(&bus->lock, flags); 2354 bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB; 2355 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2356 if (!bus_busy && bus->slave) 2357 iowrite8((bus->slave->addr & 0x7F), 2358 bus->reg + NPCM_I2CADDR1); 2359 #endif 2360 spin_unlock_irqrestore(&bus->lock, flags); 2361 2362 } while (time_is_after_jiffies(time_left) && bus_busy); 2363 2364 /* 2365 * Store the address early in a global position to ensure it is 2366 * accessible for a potential call to i2c_recover_bus(). 2367 * 2368 * Since the transfer might be a read operation, remove the I2C_M_RD flag 2369 * from the bus->dest_addr for the i2c_recover_bus() call later. 2370 * 2371 * The i2c_recover_bus() uses the address in a write direction to recover 2372 * the i2c bus if some error condition occurs. 2373 * 2374 * Remove the I2C_M_RD flag from the address since npcm_i2c_master_start_xmit() 2375 * handles the read/write operation internally. 2376 */ 2377 bus->dest_addr = i2c_8bit_addr_from_msg(msg0) & ~I2C_M_RD; 2378 2379 /* 2380 * Check the BER (bus error) state, when ber_state is true, it means that the module 2381 * detects the bus error which is caused by some factor like that the electricity 2382 * noise occurs on the bus. Under this condition, the module is reset and the bus 2383 * gets recovered. 2384 * 2385 * While ber_state is false, the module reset and bus recovery also get done as the 2386 * bus is busy. 2387 */ 2388 if (bus_busy || bus->ber_state) { 2389 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 2390 npcm_i2c_reset(bus); 2391 i2c_recover_bus(adap); 2392 return -EAGAIN; 2393 } 2394 2395 npcm_i2c_init_params(bus); 2396 bus->msgs = msgs; 2397 bus->msgs_num = num; 2398 bus->cmd_err = 0; 2399 bus->read_block_use = read_block; 2400 2401 reinit_completion(&bus->cmd_complete); 2402 2403 npcm_i2c_int_enable(bus, true); 2404 2405 if (npcm_i2c_master_start_xmit(bus, nwrite, nread, 2406 write_data, read_data, read_PEC, 2407 read_block)) { 2408 /* 2409 * Adaptive TimeOut: estimated time in usec + 100% margin: 2410 * 2: double the timeout for clock stretching case 2411 * 9: bits per transaction (including the ack/nack) 2412 */ 2413 timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite); 2414 timeout = max_t(unsigned long, bus->adap.timeout / bus->adap.retries, 2415 usecs_to_jiffies(timeout_usec)); 2416 time_left = wait_for_completion_timeout(&bus->cmd_complete, 2417 timeout); 2418 2419 if (time_left == 0) { 2420 if (bus->timeout_cnt < ULLONG_MAX) 2421 bus->timeout_cnt++; 2422 if (bus->master_or_slave == I2C_MASTER) { 2423 i2c_recover_bus(adap); 2424 bus->cmd_err = -EIO; 2425 bus->state = I2C_IDLE; 2426 } 2427 } 2428 } 2429 2430 /* if there was BER, check if need to recover the bus: */ 2431 if (bus->cmd_err == -EAGAIN) 2432 bus->cmd_err = i2c_recover_bus(adap); 2433 2434 /* 2435 * After any type of error, check if LAST bit is still set, 2436 * due to a HW issue. 2437 * It cannot be cleared without resetting the module. 2438 */ 2439 else if (bus->cmd_err && 2440 (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL))) 2441 npcm_i2c_reset(bus); 2442 2443 /* After any xfer, successful or not, stall and EOB must be disabled */ 2444 npcm_i2c_stall_after_start(bus, false); 2445 npcm_i2c_eob_int(bus, false); 2446 2447 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2448 /* reenable slave if it was enabled */ 2449 if (bus->slave) 2450 iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN, 2451 bus->reg + NPCM_I2CADDR1); 2452 #else 2453 npcm_i2c_int_enable(bus, false); 2454 #endif 2455 return bus->cmd_err; 2456 } 2457 npcm_i2c_functionality(struct i2c_adapter * adap)2458 static u32 npcm_i2c_functionality(struct i2c_adapter *adap) 2459 { 2460 return I2C_FUNC_I2C | 2461 I2C_FUNC_SMBUS_EMUL | 2462 I2C_FUNC_SMBUS_BLOCK_DATA | 2463 I2C_FUNC_SMBUS_PEC | 2464 I2C_FUNC_SLAVE; 2465 } 2466 2467 static const struct i2c_adapter_quirks npcm_i2c_quirks = { 2468 .max_read_len = 32768, 2469 .max_write_len = 32768, 2470 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 2471 }; 2472 2473 static const struct i2c_algorithm npcm_i2c_algo = { 2474 .master_xfer = npcm_i2c_master_xfer, 2475 .functionality = npcm_i2c_functionality, 2476 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2477 .reg_slave = npcm_i2c_reg_slave, 2478 .unreg_slave = npcm_i2c_unreg_slave, 2479 #endif 2480 }; 2481 2482 /* i2c debugfs directory: used to keep health monitor of i2c devices */ 2483 static struct dentry *npcm_i2c_debugfs_dir; 2484 npcm_i2c_init_debugfs(struct platform_device * pdev,struct npcm_i2c * bus)2485 static void npcm_i2c_init_debugfs(struct platform_device *pdev, 2486 struct npcm_i2c *bus) 2487 { 2488 struct dentry *d; 2489 2490 if (!npcm_i2c_debugfs_dir) 2491 return; 2492 d = debugfs_create_dir(dev_name(&pdev->dev), npcm_i2c_debugfs_dir); 2493 if (IS_ERR_OR_NULL(d)) 2494 return; 2495 debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt); 2496 debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt); 2497 debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt); 2498 debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt); 2499 debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt); 2500 debugfs_create_u64("tx_complete_cnt", 0444, d, &bus->tx_complete_cnt); 2501 2502 bus->debugfs = d; 2503 } 2504 npcm_i2c_probe_bus(struct platform_device * pdev)2505 static int npcm_i2c_probe_bus(struct platform_device *pdev) 2506 { 2507 struct device_node *np = pdev->dev.of_node; 2508 static struct regmap *gcr_regmap; 2509 struct device *dev = &pdev->dev; 2510 struct i2c_adapter *adap; 2511 struct npcm_i2c *bus; 2512 struct clk *i2c_clk; 2513 int irq; 2514 int ret; 2515 2516 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); 2517 if (!bus) 2518 return -ENOMEM; 2519 2520 bus->dev = &pdev->dev; 2521 2522 bus->data = of_device_get_match_data(dev); 2523 if (!bus->data) { 2524 dev_err(dev, "OF data missing\n"); 2525 return -EINVAL; 2526 } 2527 2528 bus->num = of_alias_get_id(pdev->dev.of_node, "i2c"); 2529 /* core clk must be acquired to calculate module timing settings */ 2530 i2c_clk = devm_clk_get(&pdev->dev, NULL); 2531 if (IS_ERR(i2c_clk)) 2532 return PTR_ERR(i2c_clk); 2533 bus->apb_clk = clk_get_rate(i2c_clk); 2534 2535 gcr_regmap = syscon_regmap_lookup_by_phandle(np, "nuvoton,sys-mgr"); 2536 if (IS_ERR(gcr_regmap)) 2537 gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); 2538 2539 if (IS_ERR(gcr_regmap)) 2540 return PTR_ERR(gcr_regmap); 2541 regmap_write(gcr_regmap, NPCM_I2CSEGCTL, bus->data->segctl_init_val); 2542 2543 bus->reg = devm_platform_ioremap_resource(pdev, 0); 2544 if (IS_ERR(bus->reg)) 2545 return PTR_ERR(bus->reg); 2546 2547 spin_lock_init(&bus->lock); 2548 init_completion(&bus->cmd_complete); 2549 2550 adap = &bus->adap; 2551 adap->owner = THIS_MODULE; 2552 adap->retries = 3; 2553 /* 2554 * The users want to connect a lot of masters on the same bus. 2555 * This timeout is used to determine the time it takes to take bus ownership. 2556 * The transactions are very long, so waiting 35ms is not enough. 2557 */ 2558 adap->timeout = 2 * HZ; 2559 adap->algo = &npcm_i2c_algo; 2560 adap->quirks = &npcm_i2c_quirks; 2561 adap->algo_data = bus; 2562 adap->dev.parent = &pdev->dev; 2563 adap->dev.of_node = pdev->dev.of_node; 2564 adap->nr = pdev->id; 2565 2566 irq = platform_get_irq(pdev, 0); 2567 if (irq < 0) 2568 return irq; 2569 2570 ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0, 2571 dev_name(bus->dev), bus); 2572 if (ret) 2573 return ret; 2574 2575 ret = __npcm_i2c_init(bus, pdev); 2576 if (ret) 2577 return ret; 2578 2579 npcm_i2c_recovery_init(adap); 2580 2581 i2c_set_adapdata(adap, bus); 2582 2583 snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d", 2584 bus->num); 2585 ret = i2c_add_numbered_adapter(&bus->adap); 2586 if (ret) 2587 return ret; 2588 2589 platform_set_drvdata(pdev, bus); 2590 npcm_i2c_init_debugfs(pdev, bus); 2591 return 0; 2592 } 2593 npcm_i2c_remove_bus(struct platform_device * pdev)2594 static void npcm_i2c_remove_bus(struct platform_device *pdev) 2595 { 2596 unsigned long lock_flags; 2597 struct npcm_i2c *bus = platform_get_drvdata(pdev); 2598 2599 debugfs_remove_recursive(bus->debugfs); 2600 spin_lock_irqsave(&bus->lock, lock_flags); 2601 npcm_i2c_disable(bus); 2602 spin_unlock_irqrestore(&bus->lock, lock_flags); 2603 i2c_del_adapter(&bus->adap); 2604 } 2605 2606 static const struct of_device_id npcm_i2c_bus_of_table[] = { 2607 { .compatible = "nuvoton,npcm750-i2c", .data = &npxm7xx_i2c_data }, 2608 { .compatible = "nuvoton,npcm845-i2c", .data = &npxm8xx_i2c_data }, 2609 {} 2610 }; 2611 MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table); 2612 2613 static struct platform_driver npcm_i2c_bus_driver = { 2614 .probe = npcm_i2c_probe_bus, 2615 .remove_new = npcm_i2c_remove_bus, 2616 .driver = { 2617 .name = "nuvoton-i2c", 2618 .of_match_table = npcm_i2c_bus_of_table, 2619 } 2620 }; 2621 npcm_i2c_init(void)2622 static int __init npcm_i2c_init(void) 2623 { 2624 int ret; 2625 2626 npcm_i2c_debugfs_dir = debugfs_create_dir("npcm_i2c", NULL); 2627 2628 ret = platform_driver_register(&npcm_i2c_bus_driver); 2629 if (ret) { 2630 debugfs_remove_recursive(npcm_i2c_debugfs_dir); 2631 return ret; 2632 } 2633 2634 return 0; 2635 } 2636 module_init(npcm_i2c_init); 2637 npcm_i2c_exit(void)2638 static void __exit npcm_i2c_exit(void) 2639 { 2640 platform_driver_unregister(&npcm_i2c_bus_driver); 2641 debugfs_remove_recursive(npcm_i2c_debugfs_dir); 2642 } 2643 module_exit(npcm_i2c_exit); 2644 2645 MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>"); 2646 MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>"); 2647 MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>"); 2648 MODULE_DESCRIPTION("Nuvoton I2C Bus Driver"); 2649 MODULE_LICENSE("GPL v2"); 2650