Searched hist:"9 cf3bc65afdb63f6fc28560274600b4e6e0c91ca" (Results 1 – 5 of 5) sorted by relevance
| /openbmc/qemu/include/hw/i2c/ |
| H A D | bcm2835_i2c.h | 9cf3bc65afdb63f6fc28560274600b4e6e0c91ca Sat Feb 24 13:10:36 CST 2024 Rayhan Faizel <rayhan.faizel@gmail.com> hw/i2c: Implement Broadcom Serial Controller (BSC)
A few deficiencies in the current device model need to be noted.
1. FIFOs are not used. All sends and receives are done directly.
2. Repeated starts are not emulated. Repeated starts can be triggered in real
hardware by sending a new read transfer request in the window time between
transfer active set of write transfer request and done bit set of the same.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240224191038.2409945-2-rayhan.faizel@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
| /openbmc/qemu/hw/i2c/ |
| H A D | bcm2835_i2c.c | 9cf3bc65afdb63f6fc28560274600b4e6e0c91ca Sat Feb 24 13:10:36 CST 2024 Rayhan Faizel <rayhan.faizel@gmail.com> hw/i2c: Implement Broadcom Serial Controller (BSC)
A few deficiencies in the current device model need to be noted.
1. FIFOs are not used. All sends and receives are done directly.
2. Repeated starts are not emulated. Repeated starts can be triggered in real
hardware by sending a new read transfer request in the window time between
transfer active set of write transfer request and done bit set of the same.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240224191038.2409945-2-rayhan.faizel@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
| H A D | meson.build | diff 9cf3bc65afdb63f6fc28560274600b4e6e0c91ca Sat Feb 24 13:10:36 CST 2024 Rayhan Faizel <rayhan.faizel@gmail.com> hw/i2c: Implement Broadcom Serial Controller (BSC)
A few deficiencies in the current device model need to be noted.
1. FIFOs are not used. All sends and receives are done directly.
2. Repeated starts are not emulated. Repeated starts can be triggered in real
hardware by sending a new read transfer request in the window time between
transfer active set of write transfer request and done bit set of the same.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240224191038.2409945-2-rayhan.faizel@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
| H A D | Kconfig | diff 9cf3bc65afdb63f6fc28560274600b4e6e0c91ca Sat Feb 24 13:10:36 CST 2024 Rayhan Faizel <rayhan.faizel@gmail.com> hw/i2c: Implement Broadcom Serial Controller (BSC)
A few deficiencies in the current device model need to be noted.
1. FIFOs are not used. All sends and receives are done directly.
2. Repeated starts are not emulated. Repeated starts can be triggered in real
hardware by sending a new read transfer request in the window time between
transfer active set of write transfer request and done bit set of the same.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240224191038.2409945-2-rayhan.faizel@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
| /openbmc/qemu/docs/system/arm/ |
| H A D | raspi.rst | diff 9cf3bc65afdb63f6fc28560274600b4e6e0c91ca Sat Feb 24 13:10:36 CST 2024 Rayhan Faizel <rayhan.faizel@gmail.com> hw/i2c: Implement Broadcom Serial Controller (BSC)
A few deficiencies in the current device model need to be noted.
1. FIFOs are not used. All sends and receives are done directly.
2. Repeated starts are not emulated. Repeated starts can be triggered in real
hardware by sending a new read transfer request in the window time between
transfer active set of write transfer request and done bit set of the same.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240224191038.2409945-2-rayhan.faizel@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|