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Searched full:sd3_dat1 (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-dhcom-drc02.dtsi14 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
109 * disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as
H A Dimx6qdl-dhcom-som.dtsi89 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
/openbmc/linux/drivers/pinctrl/renesas/
H A Dpfc-r8a77990.c166 #define GPSR4_3 F_(SD3_DAT1, IP9_27_24)
296 #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
1034 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1),
5029 { RCAR_GP_PIN(4, 3), 5, 2 }, /* SD3_DAT1 */
5198 [18] = RCAR_GP_PIN(4, 3), /* SD3_DAT1 */
H A Dpfc-r8a77965.c177 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
344 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
1135 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
5969 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
6224 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
H A Dpfc-r8a77951.c172 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
339 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
1129 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
5776 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
6031 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
H A Dpfc-r8a7796.c177 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
344 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
1132 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
5728 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5983 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
H A Dpfc-r8a7790.c1421 PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
6007 [27] = RCAR_GP_PIN(3, 27), /* SD3_DAT1 */
H A Dpfc-r8a7779.c1003 PINMUX_IPSR_GPSR(IP5_2_0, SD3_DAT1),
/openbmc/u-boot/drivers/pinctrl/renesas/
H A Dpfc-r8a7795.c130 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
297 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
1082 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
5796 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
6049 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
H A Dpfc-r8a7796.c136 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
303 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
1083 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
5751 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
6004 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
H A Dpfc-r8a77990.c141 #define GPSR4_3 F_(SD3_DAT1, IP9_27_24)
271 #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
1004 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1),
H A Dpfc-r8a7790.c1415 PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),