Searched full:gicv2m (Results 1 – 7 of 7) sorted by relevance
5 * implement ARM Generic Interrupt Controller: GICv2m.13 #define pr_fmt(fmt) "GICv2m: " fmt50 /* APM X-Gene with GICv2m MSI_IIDR register value */53 /* Broadcom NS2 GICv2m MSI_IIDR register value */66 struct resource res; /* GICv2m resource */67 void __iomem *base; /* GICv2m virt address */127 .name = "GICv2m",293 pr_err("Failed to create GICv2m domain\n"); in gicv2m_allocate_domains()336 pr_err("Failed to map GICv2m resource\n"); in gicv2m_init_one()364 * APM X-Gene GICv2m implementation has an erratum where in gicv2m_init_one()[all …]
2 * GICv2m extension for MSI/MSI-x support with a GICv2-based system22 /* This file implements an emulated GICv2m widget as described in the ARM39 #define TYPE_ARM_GICV2M "arm-gicv2m"142 "requested %u SPIs exceeds GICv2m frame maximum %d", in gicv2m_realize()169 "gicv2m", 0x1000); in gicv2m_init()
153 * GICv2m extension for MSI/MSI-x support (Optional)166 description: GICv2m MSI interface register base and size215 // GICv2m extension for MSI/MSI-x support
36 - An MSI controller (GICv2M or ITS). GICv2M is selected by default along
49 * - GICv2m MSI register is at 0xe0080000
360 [ 0.000000] GICv2m: range[mem 0x09bd0000-0x09bd0fff], SPI[544:639]
735 dev = qdev_new("arm-gicv2m"); in create_v2m()