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/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62a.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62p.dtsi53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am64.dtsi53 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
57 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
58 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
59 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
60 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
62 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dmicrochip,pcie-host.yaml49 0-3
53 pattern: '^fic[0-3]$'
84 const: 0
116 reg = <0x0 0x70000000 0x0 0x08000000>,
117 <0x0 0x43000000 0x0 0x00010000>;
124 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
125 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
126 <0 0 0 2 &pcie_intc0 1>,
127 <0 0 0 3 &pcie_intc0 2>,
128 <0 0 0 4 &pcie_intc0 3>;
[all …]
/openbmc/u-boot/drivers/spi/
H A Dcf_spi.c30 #define CONFIG_SPI_IDLE_VAL 0xFFFF
32 #define CONFIG_SPI_IDLE_VAL 0x0
38 #define SPI_MODE_MOD 0x00200000
39 #define SPI_DBLRATE 0x00100000
59 dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0; in cfspi_init()
88 while ((dspi->sr & 0x0000F000) >= 4) ; in cfspi_tx()
97 while ((dspi->sr & 0x000000F0) == 0) ; in cfspi_rx()
99 return (dspi->rfr & 0xFFFF); in cfspi_rx()
108 static u32 ctrl = 0; in cfspi_xfer()
123 ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16); in cfspi_xfer()
[all …]
/openbmc/qemu/linux-user/sparc/
H A Dtarget_mman.h4 #define TARGET_MAP_NORESERVE 0x40
5 #define TARGET_MAP_LOCKED 0x100
6 #define TARGET_MAP_GROWSDOWN 0x0200
11 * _AC(0x0000000070000000,UL) : \
13 * But VA_EXCLUDE_END is > 0xffff800000000000UL which doesn't work
17 #define TASK_UNMAPPED_BASE 0x70000000
28 #define ELF_ET_DYN_BASE 0x78000000
30 #define ELF_ET_DYN_BASE 0x0000010000000000ull
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77965-ulcb.dts20 reg = <0x0 0x48000000 0x0 0x78000000>;
31 clock-names = "du.0", "du.1", "du.3",
32 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77965-salvator-xs.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
30 clock-names = "du.0", "du.1", "du.3",
31 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77965-salvator-x.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
30 clock-names = "du.0", "du.1", "du.3",
31 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77960-salvator-xs.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774e1-hihope-rzg2h.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x5 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77960-salvator-x.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774a1-hihope-rzg2m-rev2.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774a1-hihope-rzg2m.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a779m5-salvator-xs.dts23 reg = <0x0 0x48000000 0x0 0x78000000>;
34 clock-names = "du.0", "du.1", "du.3",
35 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77961-ulcb.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
29 reg = <0x6 0x00000000 0x1 0x00000000>;
40 clock-names = "du.0", "du.1", "du.2",
41 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774b1-hihope-rzg2n.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a774b1-hihope-rzg2n-rev2.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77961-salvator-xs.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
29 reg = <0x6 0x00000000 0x1 0x00000000>;
40 clock-names = "du.0", "du.1", "du.2",
41 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a779m3-ulcb.dts22 reg = <0x0 0x48000000 0x0 0x78000000>;
27 reg = <0x4 0x80000000 0x0 0x80000000>;
32 reg = <0x6 0x00000000 0x1 0x00000000>;
43 clock-names = "du.0", "du.1", "du.2",
44 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a779m3-salvator-xs.dts23 reg = <0x0 0x48000000 0x0 0x78000000>;
28 reg = <0x4 0x80000000 0x0 0x80000000>;
33 reg = <0x6 0x00000000 0x1 0x00000000>;
44 clock-names = "du.0", "du.1", "du.2",
45 "dclkin.0", "dclkin.1", "dclkin.2";
/openbmc/linux/drivers/net/ethernet/dec/tulip/
H A Dpnic.c23 u32 phy_reg = ioread32(ioaddr + 0xB8); in pnic_do_nway()
26 if (phy_reg & 0x78000000) { /* Ignore baseT4 */ in pnic_do_nway()
27 if (phy_reg & 0x20000000) dev->if_port = 5; in pnic_do_nway()
28 else if (phy_reg & 0x40000000) dev->if_port = 3; in pnic_do_nway()
29 else if (phy_reg & 0x10000000) dev->if_port = 4; in pnic_do_nway()
30 else if (phy_reg & 0x08000000) dev->if_port = 0; in pnic_do_nway()
32 new_csr6 = (dev->if_port & 1) ? 0x01860000 : 0x00420000; in pnic_do_nway()
33 iowrite32(0x32 | (dev->if_port & 1), ioaddr + CSR12); in pnic_do_nway()
35 iowrite32(0x1F868, ioaddr + 0xB8); in pnic_do_nway()
36 if (phy_reg & 0x30000000) { in pnic_do_nway()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dr8a77965-salvator-x.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
30 clock-names = "du.0", "du.1", "du.3",
31 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a7796-salvator-x.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
36 clock-names = "du.0", "du.1", "du.2", "lvds.0",
37 "dclkin.0", "dclkin.1", "dclkin.2";
/openbmc/linux/arch/sparc/include/asm/
H A Dpcr.h19 #define PCR_PIC_PRIV 0x00000001 /* PIC access is privileged */
20 #define PCR_STRACE 0x00000002 /* Trace supervisor events */
21 #define PCR_UTRACE 0x00000004 /* Trace user events */
22 #define PCR_N2_HTRACE 0x00000008 /* Trace hypervisor events */
23 #define PCR_N2_TOE_OV0 0x00000010 /* Trap if PIC 0 overflows */
24 #define PCR_N2_TOE_OV1 0x00000020 /* Trap if PIC 1 overflows */
25 #define PCR_N2_MASK0 0x00003fc0
27 #define PCR_N2_SL0 0x0003c000
29 #define PCR_N2_OV0 0x00040000
30 #define PCR_N2_MASK1 0x07f80000
[all …]

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