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/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dnetspace_v2.h15 #define NETSPACE_V2_OE_LOW 0x06004000
16 #define NETSPACE_V2_OE_HIGH 0x00000031
17 #define NETSPACE_V2_OE_VAL_LOW 0x10030000
18 #define NETSPACE_V2_OE_VAL_HIGH 0x00000000
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dgen7_renderstate.c11 0x0000000c,
12 0x00000010,
13 0x00000018,
14 0x000001ec,
19 0x69040000,
20 0x61010008,
21 0x00000000,
22 0x00000001, /* reloc */
23 0x00000001, /* reloc */
24 0x00000000,
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Dinitvals.c32 * @ini_mode: 0 to write 1 to read (and clear)
39 AR5K_INI_WRITE = 0, /* Default */
57 { AR5K_NOQCU_TXDP0, 0 },
58 { AR5K_NOQCU_TXDP1, 0 },
59 { AR5K_RXDP, 0 },
60 { AR5K_CR, 0 },
61 { AR5K_ISR, 0, AR5K_INI_READ },
62 { AR5K_IMR, 0 },
64 { AR5K_BSR, 0, AR5K_INI_READ },
70 { AR5K_RPGTO, 0 },
[all …]
H A Drfgain.h38 { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } },
39 { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } },
40 { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } },
41 { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } },
42 { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } },
43 { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } },
44 { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } },
45 { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } },
46 { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } },
47 { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } },
[all …]
/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_dram_tables.h12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcx2072x.c58 * max : 74 : 0 dB
60 * min : 0 : -74 dB
62 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7400, 100, 0);
63 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7400, 100, 0);
64 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 1200, 0);
72 0, 0, TLV_DB_SCALE_ITEM(120, 0, 0),
73 1, 63, TLV_DB_SCALE_ITEM(30, 30, 0)
96 { CX2072X_AFG_POWER_STATE, 0x00000003 },
97 { CX2072X_UM_RESPONSE, 0x00000000 },
98 { CX2072X_GPIO_DATA, 0x00000000 },
[all …]
H A Drt286.c33 #define RT286_VENDOR_ID 0x10ec0286
34 #define RT288_VENDOR_ID 0x10ec0288
50 { 0x01, 0xaaaa },
51 { 0x02, 0x8aaa },
52 { 0x03, 0x0002 },
53 { 0x04, 0xaf01 },
54 { 0x08, 0x000d },
55 { 0x09, 0xd810 },
56 { 0x0a, 0x0120 },
57 { 0x0b, 0x0000 },
[all …]
H A Drt274.c32 #define RT274_VENDOR_ID 0x10ec0274
49 { 0x00, 0x1004 },
50 { 0x01, 0xaaaa },
51 { 0x02, 0x88aa },
52 { 0x03, 0x0002 },
53 { 0x04, 0xaa09 },
54 { 0x05, 0x0700 },
55 { 0x06, 0x6110 },
56 { 0x07, 0x0200 },
57 { 0x08, 0xa807 },
[all …]
H A Drt298.c33 #define RT298_VENDOR_ID 0x10ec0298
50 { 0x01, 0xa5a8 },
51 { 0x02, 0x8e95 },
52 { 0x03, 0x0002 },
53 { 0x04, 0xaf67 },
54 { 0x08, 0x200f },
55 { 0x09, 0xd010 },
56 { 0x0a, 0x0100 },
57 { 0x0b, 0x0000 },
58 { 0x0d, 0x2800 },
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
H A Dnavi10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 GATCL1_TYPE_NORMAL = 0x00000000,
185 GATCL1_TYPE_SHOOTDOWN = 0x00000001,
186 GATCL1_TYPE_BYPASS = 0x00000002,
194 UTCL1_TYPE_NORMAL = 0x00000000,
195 UTCL1_TYPE_SHOOTDOWN = 0x00000001,
196 UTCL1_TYPE_BYPASS = 0x00000002,
204 UTCL1_XNACK_SUCCESS = 0x00000000,
205 UTCL1_XNACK_RETRY = 0x00000001,
206 UTCL1_XNACK_PRT = 0x00000002,
[all …]
H A Dsoc21_enum.h55 DSM_DATA_SEL_DISABLE = 0x00000000,
56 DSM_DATA_SEL_0 = 0x00000001,
57 DSM_DATA_SEL_1 = 0x00000002,
58 DSM_DATA_SEL_BOTH = 0x00000003,
66 DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
67 DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
68 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002,
69 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003,
77 DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
78 DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dfsl_epu.c13 {EPGCR, 0},
15 {EPECR0 + EPECR_STRIDE * 0, 0},
16 {EPECR0 + EPECR_STRIDE * 1, 0},
17 {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
18 {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
19 {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
20 {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
21 {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
22 {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
23 {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
[all …]
/openbmc/linux/sound/ppc/
H A Dtumbler_volume.h4 /* 0 = -70 dB, 175 = 18.0 dB in 0.5 dB step */
6 0x00000015, 0x00000016, 0x00000017,
7 0x00000019, 0x0000001a, 0x0000001c,
8 0x0000001d, 0x0000001f, 0x00000021,
9 0x00000023, 0x00000025, 0x00000027,
10 0x00000029, 0x0000002c, 0x0000002e,
11 0x00000031, 0x00000034, 0x00000037,
12 0x0000003a, 0x0000003e, 0x00000042,
13 0x00000045, 0x0000004a, 0x0000004e,
14 0x00000053, 0x00000057, 0x0000005d,
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
H A Dnv31.c44 if (ret == 0) { in nv31_mpeg_object_bind()
46 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv31_mpeg_object_bind()
47 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv31_mpeg_object_bind()
48 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv31_mpeg_object_bind()
49 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv31_mpeg_object_bind()
102 ret = 0; in nv31_mpeg_chan_new()
118 nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch); in nv31_mpeg_tile()
119 nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit); in nv31_mpeg_tile()
120 nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr); in nv31_mpeg_tile()
129 u32 dma0 = nvkm_rd32(device, 0x700000 + inst); in nv31_mpeg_mthd_dma()
[all …]
/openbmc/linux/arch/arm/mm/
H A Dproc-arm946.S19 * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 bic r0, r0, #0x00001000 @ i-cache
45 bic r0, r0, #0x00000004 @ d-cache
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
56 mov ip, #0
57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
60 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
[all …]
/openbmc/linux/drivers/net/wireless/ath/carl9170/
H A Dphy.c48 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE_MAX, 0x7f); in carl9170_init_power_cal()
49 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE1, 0x3f3f3f3f); in carl9170_init_power_cal()
50 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE2, 0x3f3f3f3f); in carl9170_init_power_cal()
51 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE3, 0x3f3f3f3f); in carl9170_init_power_cal()
52 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE4, 0x3f3f3f3f); in carl9170_init_power_cal()
53 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE5, 0x3f3f3f3f); in carl9170_init_power_cal()
54 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE6, 0x3f3f3f3f); in carl9170_init_power_cal()
55 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE7, 0x3f3f3f3f); in carl9170_init_power_cal()
56 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE8, 0x3f3f3f3f); in carl9170_init_power_cal()
57 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE9, 0x3f3f3f3f); in carl9170_init_power_cal()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmem.h11 #define CS0 0x0
12 #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
16 STACKED = 0,
32 #define SDRC_SHARING 0x00000100
33 #define SDRC_MR_0_SDR 0x00000031
37 * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The
40 #define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
41 #define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
42 #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
43 #define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
[all …]
/openbmc/linux/drivers/scsi/lpfc/
H A Dlpfc_debugfs.h65 #define LPFC_PCI_CFG_BROWSE 0xffff
71 #define IDIAG_PCICFG_WHERE_INDX 0
76 #define LPFC_PCI_BAR_BROWSE 0xffff
93 #define IDIAG_BARACC_BAR_NUM_INDX 0
99 #define IDIAG_BARACC_BAR_0 0
109 #define LPFC_QUE_ACC_BROWSE 0xffff
121 #define IDIAG_QUEACC_QUETP_INDX 0
129 #define LPFC_DRB_ACC_ALL 0xffff
142 #define IDIAG_DRBACC_REGID_INDX 0
146 #define LPFC_CTL_ACC_ALL 0xffff
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9001_initvals.h19 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
20 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
21 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
22 {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000},
23 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
24 {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab},
25 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
26 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
27 {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300},
28 {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200},
[all …]
H A Dar5008_initvals.h19 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
20 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
21 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
22 {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000},
23 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
24 {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab},
25 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
26 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
27 {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300},
28 {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200},
[all …]
/openbmc/u-boot/include/linux/
H A Dethtool.h98 __u8 data[0];
107 __u8 data[0];
115 * a packet arrives. If 0, only rx_max_coalesced_frames
121 * a packet arrives. If 0, only rx_coalesce_usecs is
137 * a packet is sent. If 0, only tx_max_coalesced_frames
143 * a packet is sent. If 0, only tx_coalesce_usecs is
249 ETH_SS_TEST = 0,
261 __u8 data[0];
269 __u32 data[0]; /* ETH_SS_xxx count, in order, based on bits
276 ETH_TEST_FL_OFFLINE = (1 << 0), /* online / offline */
[all …]
/openbmc/linux/drivers/scsi/
H A D53c700_d.h_shipped28 ABSOLUTE Device_ID = 0 ; ID of target for command
29 ABSOLUTE MessageCount = 0 ; Number of bytes in message
30 ABSOLUTE MessageLocation = 0 ; Addr of message
31 ABSOLUTE CommandCount = 0 ; Number of bytes in command
32 ABSOLUTE CommandAddress = 0 ; Addr of Command
33 ABSOLUTE StatusAddress = 0 ; Addr to receive status return
34 ABSOLUTE ReceiveMsgAddress = 0 ; Addr to receive msg
42 ABSOLUTE SGScriptStartAddress = 0
45 ; this: 0xPRS where
48 ABSOLUTE AFTER_SELECTION = 0x100
[all …]

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