1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2023, Linaro Ltd. All rights reserved.
4 */
5
6 #include <linux/delay.h>
7 #include <linux/err.h>
8 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/slab.h>
16 #include <linux/usb/tcpm.h>
17 #include <linux/usb/typec_mux.h>
18 #include <linux/workqueue.h>
19 #include "qcom_pmic_typec_port.h"
20
21 struct pmic_typec_port_irq_data {
22 int virq;
23 int irq;
24 struct pmic_typec_port *pmic_typec_port;
25 };
26
27 struct pmic_typec_port {
28 struct device *dev;
29 struct tcpm_port *tcpm_port;
30 struct regmap *regmap;
31 u32 base;
32 unsigned int nr_irqs;
33 struct pmic_typec_port_irq_data *irq_data;
34
35 struct regulator *vdd_vbus;
36
37 int cc;
38 bool debouncing_cc;
39 struct delayed_work cc_debounce_dwork;
40
41 spinlock_t lock; /* Register atomicity */
42 };
43
44 static const char * const typec_cc_status_name[] = {
45 [TYPEC_CC_OPEN] = "Open",
46 [TYPEC_CC_RA] = "Ra",
47 [TYPEC_CC_RD] = "Rd",
48 [TYPEC_CC_RP_DEF] = "Rp-def",
49 [TYPEC_CC_RP_1_5] = "Rp-1.5",
50 [TYPEC_CC_RP_3_0] = "Rp-3.0",
51 };
52
53 static const char *rp_unknown = "unknown";
54
cc_to_name(enum typec_cc_status cc)55 static const char *cc_to_name(enum typec_cc_status cc)
56 {
57 if (cc > TYPEC_CC_RP_3_0)
58 return rp_unknown;
59
60 return typec_cc_status_name[cc];
61 }
62
63 static const char * const rp_sel_name[] = {
64 [TYPEC_SRC_RP_SEL_80UA] = "Rp-def-80uA",
65 [TYPEC_SRC_RP_SEL_180UA] = "Rp-1.5-180uA",
66 [TYPEC_SRC_RP_SEL_330UA] = "Rp-3.0-330uA",
67 };
68
rp_sel_to_name(int rp_sel)69 static const char *rp_sel_to_name(int rp_sel)
70 {
71 if (rp_sel > TYPEC_SRC_RP_SEL_330UA)
72 return rp_unknown;
73
74 return rp_sel_name[rp_sel];
75 }
76
77 #define misc_to_cc(msic) !!(misc & CC_ORIENTATION) ? "cc1" : "cc2"
78 #define misc_to_vconn(msic) !!(misc & CC_ORIENTATION) ? "cc2" : "cc1"
79
qcom_pmic_typec_port_cc_debounce(struct work_struct * work)80 static void qcom_pmic_typec_port_cc_debounce(struct work_struct *work)
81 {
82 struct pmic_typec_port *pmic_typec_port =
83 container_of(work, struct pmic_typec_port, cc_debounce_dwork.work);
84 unsigned long flags;
85
86 spin_lock_irqsave(&pmic_typec_port->lock, flags);
87 pmic_typec_port->debouncing_cc = false;
88 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
89
90 dev_dbg(pmic_typec_port->dev, "Debounce cc complete\n");
91 }
92
pmic_typec_port_isr(int irq,void * dev_id)93 static irqreturn_t pmic_typec_port_isr(int irq, void *dev_id)
94 {
95 struct pmic_typec_port_irq_data *irq_data = dev_id;
96 struct pmic_typec_port *pmic_typec_port = irq_data->pmic_typec_port;
97 u32 misc_stat;
98 bool vbus_change = false;
99 bool cc_change = false;
100 unsigned long flags;
101 int ret;
102
103 spin_lock_irqsave(&pmic_typec_port->lock, flags);
104
105 ret = regmap_read(pmic_typec_port->regmap,
106 pmic_typec_port->base + TYPEC_MISC_STATUS_REG,
107 &misc_stat);
108 if (ret)
109 goto done;
110
111 switch (irq_data->virq) {
112 case PMIC_TYPEC_VBUS_IRQ:
113 vbus_change = true;
114 break;
115 case PMIC_TYPEC_CC_STATE_IRQ:
116 case PMIC_TYPEC_ATTACH_DETACH_IRQ:
117 if (!pmic_typec_port->debouncing_cc)
118 cc_change = true;
119 break;
120 }
121
122 done:
123 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
124
125 if (vbus_change)
126 tcpm_vbus_change(pmic_typec_port->tcpm_port);
127
128 if (cc_change)
129 tcpm_cc_change(pmic_typec_port->tcpm_port);
130
131 return IRQ_HANDLED;
132 }
133
qcom_pmic_typec_port_get_vbus(struct pmic_typec_port * pmic_typec_port)134 int qcom_pmic_typec_port_get_vbus(struct pmic_typec_port *pmic_typec_port)
135 {
136 struct device *dev = pmic_typec_port->dev;
137 unsigned int misc;
138 int ret;
139
140 ret = regmap_read(pmic_typec_port->regmap,
141 pmic_typec_port->base + TYPEC_MISC_STATUS_REG,
142 &misc);
143 if (ret)
144 misc = 0;
145
146 dev_dbg(dev, "get_vbus: 0x%08x detect %d\n", misc, !!(misc & TYPEC_VBUS_DETECT));
147
148 return !!(misc & TYPEC_VBUS_DETECT);
149 }
150
qcom_pmic_typec_port_set_vbus(struct pmic_typec_port * pmic_typec_port,bool on)151 int qcom_pmic_typec_port_set_vbus(struct pmic_typec_port *pmic_typec_port, bool on)
152 {
153 u32 sm_stat;
154 u32 val;
155 int ret;
156
157 if (on) {
158 ret = regulator_enable(pmic_typec_port->vdd_vbus);
159 if (ret)
160 return ret;
161
162 val = TYPEC_SM_VBUS_VSAFE5V;
163 } else {
164 ret = regulator_disable(pmic_typec_port->vdd_vbus);
165 if (ret)
166 return ret;
167
168 val = TYPEC_SM_VBUS_VSAFE0V;
169 }
170
171 /* Poll waiting for transition to required vSafe5V or vSafe0V */
172 ret = regmap_read_poll_timeout(pmic_typec_port->regmap,
173 pmic_typec_port->base + TYPEC_SM_STATUS_REG,
174 sm_stat, sm_stat & val,
175 100, 250000);
176 if (ret)
177 dev_warn(pmic_typec_port->dev, "vbus vsafe%dv fail\n", on ? 5 : 0);
178
179 return 0;
180 }
181
qcom_pmic_typec_port_get_cc(struct pmic_typec_port * pmic_typec_port,enum typec_cc_status * cc1,enum typec_cc_status * cc2)182 int qcom_pmic_typec_port_get_cc(struct pmic_typec_port *pmic_typec_port,
183 enum typec_cc_status *cc1,
184 enum typec_cc_status *cc2)
185 {
186 struct device *dev = pmic_typec_port->dev;
187 unsigned int misc, val;
188 bool attached;
189 int ret = 0;
190
191 ret = regmap_read(pmic_typec_port->regmap,
192 pmic_typec_port->base + TYPEC_MISC_STATUS_REG, &misc);
193 if (ret)
194 goto done;
195
196 attached = !!(misc & CC_ATTACHED);
197
198 if (pmic_typec_port->debouncing_cc) {
199 ret = -EBUSY;
200 goto done;
201 }
202
203 *cc1 = TYPEC_CC_OPEN;
204 *cc2 = TYPEC_CC_OPEN;
205
206 if (!attached)
207 goto done;
208
209 if (misc & SNK_SRC_MODE) {
210 ret = regmap_read(pmic_typec_port->regmap,
211 pmic_typec_port->base + TYPEC_SRC_STATUS_REG,
212 &val);
213 if (ret)
214 goto done;
215 switch (val & DETECTED_SRC_TYPE_MASK) {
216 case AUDIO_ACCESS_RA_RA:
217 val = TYPEC_CC_RA;
218 *cc1 = TYPEC_CC_RA;
219 *cc2 = TYPEC_CC_RA;
220 break;
221 case SRC_RD_OPEN:
222 val = TYPEC_CC_RD;
223 break;
224 case SRC_RD_RA_VCONN:
225 val = TYPEC_CC_RD;
226 *cc1 = TYPEC_CC_RA;
227 *cc2 = TYPEC_CC_RA;
228 break;
229 default:
230 dev_warn(dev, "unexpected src status %.2x\n", val);
231 val = TYPEC_CC_RD;
232 break;
233 }
234 } else {
235 ret = regmap_read(pmic_typec_port->regmap,
236 pmic_typec_port->base + TYPEC_SNK_STATUS_REG,
237 &val);
238 if (ret)
239 goto done;
240 switch (val & DETECTED_SNK_TYPE_MASK) {
241 case SNK_RP_STD:
242 val = TYPEC_CC_RP_DEF;
243 break;
244 case SNK_RP_1P5:
245 val = TYPEC_CC_RP_1_5;
246 break;
247 case SNK_RP_3P0:
248 val = TYPEC_CC_RP_3_0;
249 break;
250 default:
251 dev_warn(dev, "unexpected snk status %.2x\n", val);
252 val = TYPEC_CC_RP_DEF;
253 break;
254 }
255 }
256
257 if (misc & CC_ORIENTATION)
258 *cc2 = val;
259 else
260 *cc1 = val;
261
262 done:
263 dev_dbg(dev, "get_cc: misc 0x%08x cc1 0x%08x %s cc2 0x%08x %s attached %d cc=%s\n",
264 misc, *cc1, cc_to_name(*cc1), *cc2, cc_to_name(*cc2), attached,
265 misc_to_cc(misc));
266
267 return ret;
268 }
269
qcom_pmic_set_cc_debounce(struct pmic_typec_port * pmic_typec_port)270 static void qcom_pmic_set_cc_debounce(struct pmic_typec_port *pmic_typec_port)
271 {
272 pmic_typec_port->debouncing_cc = true;
273 schedule_delayed_work(&pmic_typec_port->cc_debounce_dwork,
274 msecs_to_jiffies(2));
275 }
276
qcom_pmic_typec_port_set_cc(struct pmic_typec_port * pmic_typec_port,enum typec_cc_status cc)277 int qcom_pmic_typec_port_set_cc(struct pmic_typec_port *pmic_typec_port,
278 enum typec_cc_status cc)
279 {
280 struct device *dev = pmic_typec_port->dev;
281 unsigned int mode, currsrc;
282 unsigned int misc;
283 unsigned long flags;
284 int ret;
285
286 spin_lock_irqsave(&pmic_typec_port->lock, flags);
287
288 ret = regmap_read(pmic_typec_port->regmap,
289 pmic_typec_port->base + TYPEC_MISC_STATUS_REG,
290 &misc);
291 if (ret)
292 goto done;
293
294 mode = EN_SRC_ONLY;
295
296 switch (cc) {
297 case TYPEC_CC_OPEN:
298 currsrc = TYPEC_SRC_RP_SEL_80UA;
299 break;
300 case TYPEC_CC_RP_DEF:
301 currsrc = TYPEC_SRC_RP_SEL_80UA;
302 break;
303 case TYPEC_CC_RP_1_5:
304 currsrc = TYPEC_SRC_RP_SEL_180UA;
305 break;
306 case TYPEC_CC_RP_3_0:
307 currsrc = TYPEC_SRC_RP_SEL_330UA;
308 break;
309 case TYPEC_CC_RD:
310 currsrc = TYPEC_SRC_RP_SEL_80UA;
311 mode = EN_SNK_ONLY;
312 break;
313 default:
314 dev_warn(dev, "unexpected set_cc %d\n", cc);
315 ret = -EINVAL;
316 goto done;
317 }
318
319 if (mode == EN_SRC_ONLY) {
320 ret = regmap_write(pmic_typec_port->regmap,
321 pmic_typec_port->base + TYPEC_CURRSRC_CFG_REG,
322 currsrc);
323 if (ret)
324 goto done;
325 }
326
327 pmic_typec_port->cc = cc;
328 qcom_pmic_set_cc_debounce(pmic_typec_port);
329 ret = 0;
330
331 done:
332 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
333
334 dev_dbg(dev, "set_cc: currsrc=%x %s mode %s debounce %d attached %d cc=%s\n",
335 currsrc, rp_sel_to_name(currsrc),
336 mode == EN_SRC_ONLY ? "EN_SRC_ONLY" : "EN_SNK_ONLY",
337 pmic_typec_port->debouncing_cc, !!(misc & CC_ATTACHED),
338 misc_to_cc(misc));
339
340 return ret;
341 }
342
qcom_pmic_typec_port_set_vconn(struct pmic_typec_port * pmic_typec_port,bool on)343 int qcom_pmic_typec_port_set_vconn(struct pmic_typec_port *pmic_typec_port, bool on)
344 {
345 struct device *dev = pmic_typec_port->dev;
346 unsigned int orientation, misc, mask, value;
347 unsigned long flags;
348 int ret;
349
350 spin_lock_irqsave(&pmic_typec_port->lock, flags);
351
352 ret = regmap_read(pmic_typec_port->regmap,
353 pmic_typec_port->base + TYPEC_MISC_STATUS_REG, &misc);
354 if (ret)
355 goto done;
356
357 /* Set VCONN on the inversion of the active CC channel */
358 orientation = (misc & CC_ORIENTATION) ? 0 : VCONN_EN_ORIENTATION;
359 if (on) {
360 mask = VCONN_EN_ORIENTATION | VCONN_EN_VALUE;
361 value = orientation | VCONN_EN_VALUE | VCONN_EN_SRC;
362 } else {
363 mask = VCONN_EN_VALUE;
364 value = 0;
365 }
366
367 ret = regmap_update_bits(pmic_typec_port->regmap,
368 pmic_typec_port->base + TYPEC_VCONN_CONTROL_REG,
369 mask, value);
370 done:
371 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
372
373 dev_dbg(dev, "set_vconn: orientation %d control 0x%08x state %s cc %s vconn %s\n",
374 orientation, value, on ? "on" : "off", misc_to_vconn(misc), misc_to_cc(misc));
375
376 return ret;
377 }
378
qcom_pmic_typec_port_start_toggling(struct pmic_typec_port * pmic_typec_port,enum typec_port_type port_type,enum typec_cc_status cc)379 int qcom_pmic_typec_port_start_toggling(struct pmic_typec_port *pmic_typec_port,
380 enum typec_port_type port_type,
381 enum typec_cc_status cc)
382 {
383 struct device *dev = pmic_typec_port->dev;
384 unsigned int misc;
385 u8 mode = 0;
386 unsigned long flags;
387 int ret;
388
389 switch (port_type) {
390 case TYPEC_PORT_SRC:
391 mode = EN_SRC_ONLY;
392 break;
393 case TYPEC_PORT_SNK:
394 mode = EN_SNK_ONLY;
395 break;
396 case TYPEC_PORT_DRP:
397 mode = EN_TRY_SNK;
398 break;
399 }
400
401 spin_lock_irqsave(&pmic_typec_port->lock, flags);
402
403 ret = regmap_read(pmic_typec_port->regmap,
404 pmic_typec_port->base + TYPEC_MISC_STATUS_REG, &misc);
405 if (ret)
406 goto done;
407
408 dev_dbg(dev, "start_toggling: misc 0x%08x attached %d port_type %d current cc %d new %d\n",
409 misc, !!(misc & CC_ATTACHED), port_type, pmic_typec_port->cc, cc);
410
411 qcom_pmic_set_cc_debounce(pmic_typec_port);
412
413 /* force it to toggle at least once */
414 ret = regmap_write(pmic_typec_port->regmap,
415 pmic_typec_port->base + TYPEC_MODE_CFG_REG,
416 TYPEC_DISABLE_CMD);
417 if (ret)
418 goto done;
419
420 ret = regmap_write(pmic_typec_port->regmap,
421 pmic_typec_port->base + TYPEC_MODE_CFG_REG,
422 mode);
423 done:
424 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
425
426 return ret;
427 }
428
429 #define TYPEC_INTR_EN_CFG_1_MASK \
430 (TYPEC_LEGACY_CABLE_INT_EN | \
431 TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN | \
432 TYPEC_TRYSOURCE_DETECT_INT_EN | \
433 TYPEC_TRYSINK_DETECT_INT_EN | \
434 TYPEC_CCOUT_DETACH_INT_EN | \
435 TYPEC_CCOUT_ATTACH_INT_EN | \
436 TYPEC_VBUS_DEASSERT_INT_EN | \
437 TYPEC_VBUS_ASSERT_INT_EN)
438
439 #define TYPEC_INTR_EN_CFG_2_MASK \
440 (TYPEC_STATE_MACHINE_CHANGE_INT_EN | TYPEC_VBUS_ERROR_INT_EN | \
441 TYPEC_DEBOUNCE_DONE_INT_EN)
442
qcom_pmic_typec_port_start(struct pmic_typec_port * pmic_typec_port,struct tcpm_port * tcpm_port)443 int qcom_pmic_typec_port_start(struct pmic_typec_port *pmic_typec_port,
444 struct tcpm_port *tcpm_port)
445 {
446 int i;
447 int mask;
448 int ret;
449
450 /* Configure interrupt sources */
451 ret = regmap_write(pmic_typec_port->regmap,
452 pmic_typec_port->base + TYPEC_INTERRUPT_EN_CFG_1_REG,
453 TYPEC_INTR_EN_CFG_1_MASK);
454 if (ret)
455 goto done;
456
457 ret = regmap_write(pmic_typec_port->regmap,
458 pmic_typec_port->base + TYPEC_INTERRUPT_EN_CFG_2_REG,
459 TYPEC_INTR_EN_CFG_2_MASK);
460 if (ret)
461 goto done;
462
463 /* start in TRY_SNK mode */
464 ret = regmap_write(pmic_typec_port->regmap,
465 pmic_typec_port->base + TYPEC_MODE_CFG_REG, EN_TRY_SNK);
466 if (ret)
467 goto done;
468
469 /* Configure VCONN for software control */
470 ret = regmap_update_bits(pmic_typec_port->regmap,
471 pmic_typec_port->base + TYPEC_VCONN_CONTROL_REG,
472 VCONN_EN_SRC | VCONN_EN_VALUE, VCONN_EN_SRC);
473 if (ret)
474 goto done;
475
476 /* Set CC threshold to 1.6 Volts | tPDdebounce = 10-20ms */
477 mask = SEL_SRC_UPPER_REF | USE_TPD_FOR_EXITING_ATTACHSRC;
478 ret = regmap_update_bits(pmic_typec_port->regmap,
479 pmic_typec_port->base + TYPEC_EXIT_STATE_CFG_REG,
480 mask, mask);
481 if (ret)
482 goto done;
483
484 pmic_typec_port->tcpm_port = tcpm_port;
485
486 for (i = 0; i < pmic_typec_port->nr_irqs; i++)
487 enable_irq(pmic_typec_port->irq_data[i].irq);
488
489 done:
490 return ret;
491 }
492
qcom_pmic_typec_port_stop(struct pmic_typec_port * pmic_typec_port)493 void qcom_pmic_typec_port_stop(struct pmic_typec_port *pmic_typec_port)
494 {
495 int i;
496
497 for (i = 0; i < pmic_typec_port->nr_irqs; i++)
498 disable_irq(pmic_typec_port->irq_data[i].irq);
499 }
500
qcom_pmic_typec_port_alloc(struct device * dev)501 struct pmic_typec_port *qcom_pmic_typec_port_alloc(struct device *dev)
502 {
503 return devm_kzalloc(dev, sizeof(struct pmic_typec_port), GFP_KERNEL);
504 }
505
qcom_pmic_typec_port_probe(struct platform_device * pdev,struct pmic_typec_port * pmic_typec_port,struct pmic_typec_port_resources * res,struct regmap * regmap,u32 base)506 int qcom_pmic_typec_port_probe(struct platform_device *pdev,
507 struct pmic_typec_port *pmic_typec_port,
508 struct pmic_typec_port_resources *res,
509 struct regmap *regmap,
510 u32 base)
511 {
512 struct device *dev = &pdev->dev;
513 struct pmic_typec_port_irq_data *irq_data;
514 int i, ret, irq;
515
516 if (!res->nr_irqs || res->nr_irqs > PMIC_TYPEC_MAX_IRQS)
517 return -EINVAL;
518
519 irq_data = devm_kzalloc(dev, sizeof(*irq_data) * res->nr_irqs,
520 GFP_KERNEL);
521 if (!irq_data)
522 return -ENOMEM;
523
524 pmic_typec_port->vdd_vbus = devm_regulator_get(dev, "vdd-vbus");
525 if (IS_ERR(pmic_typec_port->vdd_vbus))
526 return PTR_ERR(pmic_typec_port->vdd_vbus);
527
528 pmic_typec_port->dev = dev;
529 pmic_typec_port->base = base;
530 pmic_typec_port->regmap = regmap;
531 pmic_typec_port->nr_irqs = res->nr_irqs;
532 pmic_typec_port->irq_data = irq_data;
533 spin_lock_init(&pmic_typec_port->lock);
534 INIT_DELAYED_WORK(&pmic_typec_port->cc_debounce_dwork,
535 qcom_pmic_typec_port_cc_debounce);
536
537 irq = platform_get_irq(pdev, 0);
538 if (irq < 0)
539 return irq;
540
541 for (i = 0; i < res->nr_irqs; i++, irq_data++) {
542 irq = platform_get_irq_byname(pdev,
543 res->irq_params[i].irq_name);
544 if (irq < 0)
545 return irq;
546
547 irq_data->pmic_typec_port = pmic_typec_port;
548 irq_data->irq = irq;
549 irq_data->virq = res->irq_params[i].virq;
550 ret = devm_request_threaded_irq(dev, irq, NULL, pmic_typec_port_isr,
551 IRQF_ONESHOT | IRQF_NO_AUTOEN,
552 res->irq_params[i].irq_name,
553 irq_data);
554 if (ret)
555 return ret;
556 }
557
558 return 0;
559 }
560