1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 pcs_to_mt753x_pcs(struct phylink_pcs * pcs)27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int core_read_mmd_indirect(struct mt7530_priv * priv,int prtad,int devad)83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int core_write_mmd_indirect(struct mt7530_priv * priv,int prtad,int devad,u32 data)114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void mt7530_mutex_lock(struct mt7530_priv * priv)145 mt7530_mutex_lock(struct mt7530_priv *priv) 146 { 147 if (priv->bus) 148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 149 } 150 151 static void mt7530_mutex_unlock(struct mt7530_priv * priv)152 mt7530_mutex_unlock(struct mt7530_priv *priv) 153 { 154 if (priv->bus) 155 mutex_unlock(&priv->bus->mdio_lock); 156 } 157 158 static void core_write(struct mt7530_priv * priv,u32 reg,u32 val)159 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 160 { 161 mt7530_mutex_lock(priv); 162 163 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 164 165 mt7530_mutex_unlock(priv); 166 } 167 168 static void core_rmw(struct mt7530_priv * priv,u32 reg,u32 mask,u32 set)169 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 170 { 171 u32 val; 172 173 mt7530_mutex_lock(priv); 174 175 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 176 val &= ~mask; 177 val |= set; 178 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 179 180 mt7530_mutex_unlock(priv); 181 } 182 183 static void core_set(struct mt7530_priv * priv,u32 reg,u32 val)184 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 185 { 186 core_rmw(priv, reg, 0, val); 187 } 188 189 static void core_clear(struct mt7530_priv * priv,u32 reg,u32 val)190 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 191 { 192 core_rmw(priv, reg, val, 0); 193 } 194 195 static int mt7530_mii_write(struct mt7530_priv * priv,u32 reg,u32 val)196 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 197 { 198 int ret; 199 200 ret = regmap_write(priv->regmap, reg, val); 201 202 if (ret < 0) 203 dev_err(priv->dev, 204 "failed to write mt7530 register\n"); 205 206 return ret; 207 } 208 209 static u32 mt7530_mii_read(struct mt7530_priv * priv,u32 reg)210 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 211 { 212 int ret; 213 u32 val; 214 215 ret = regmap_read(priv->regmap, reg, &val); 216 if (ret) { 217 WARN_ON_ONCE(1); 218 dev_err(priv->dev, 219 "failed to read mt7530 register\n"); 220 return 0; 221 } 222 223 return val; 224 } 225 226 static void mt7530_write(struct mt7530_priv * priv,u32 reg,u32 val)227 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 228 { 229 mt7530_mutex_lock(priv); 230 231 mt7530_mii_write(priv, reg, val); 232 233 mt7530_mutex_unlock(priv); 234 } 235 236 static u32 _mt7530_unlocked_read(struct mt7530_dummy_poll * p)237 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 238 { 239 return mt7530_mii_read(p->priv, p->reg); 240 } 241 242 static u32 _mt7530_read(struct mt7530_dummy_poll * p)243 _mt7530_read(struct mt7530_dummy_poll *p) 244 { 245 u32 val; 246 247 mt7530_mutex_lock(p->priv); 248 249 val = mt7530_mii_read(p->priv, p->reg); 250 251 mt7530_mutex_unlock(p->priv); 252 253 return val; 254 } 255 256 static u32 mt7530_read(struct mt7530_priv * priv,u32 reg)257 mt7530_read(struct mt7530_priv *priv, u32 reg) 258 { 259 struct mt7530_dummy_poll p; 260 261 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 262 return _mt7530_read(&p); 263 } 264 265 static void mt7530_rmw(struct mt7530_priv * priv,u32 reg,u32 mask,u32 set)266 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 267 u32 mask, u32 set) 268 { 269 mt7530_mutex_lock(priv); 270 271 regmap_update_bits(priv->regmap, reg, mask, set); 272 273 mt7530_mutex_unlock(priv); 274 } 275 276 static void mt7530_set(struct mt7530_priv * priv,u32 reg,u32 val)277 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 278 { 279 mt7530_rmw(priv, reg, val, val); 280 } 281 282 static void mt7530_clear(struct mt7530_priv * priv,u32 reg,u32 val)283 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 284 { 285 mt7530_rmw(priv, reg, val, 0); 286 } 287 288 static int mt7530_fdb_cmd(struct mt7530_priv * priv,enum mt7530_fdb_cmd cmd,u32 * rsp)289 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 290 { 291 u32 val; 292 int ret; 293 struct mt7530_dummy_poll p; 294 295 /* Set the command operating upon the MAC address entries */ 296 val = ATC_BUSY | ATC_MAT(0) | cmd; 297 mt7530_write(priv, MT7530_ATC, val); 298 299 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 300 ret = readx_poll_timeout(_mt7530_read, &p, val, 301 !(val & ATC_BUSY), 20, 20000); 302 if (ret < 0) { 303 dev_err(priv->dev, "reset timeout\n"); 304 return ret; 305 } 306 307 /* Additional sanity for read command if the specified 308 * entry is invalid 309 */ 310 val = mt7530_read(priv, MT7530_ATC); 311 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 312 return -EINVAL; 313 314 if (rsp) 315 *rsp = val; 316 317 return 0; 318 } 319 320 static void mt7530_fdb_read(struct mt7530_priv * priv,struct mt7530_fdb * fdb)321 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 322 { 323 u32 reg[3]; 324 int i; 325 326 /* Read from ARL table into an array */ 327 for (i = 0; i < 3; i++) { 328 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 329 330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 331 __func__, __LINE__, i, reg[i]); 332 } 333 334 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 344 } 345 346 static void mt7530_fdb_write(struct mt7530_priv * priv,u16 vid,u8 port_mask,const u8 * mac,u8 aging,u8 type)347 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 348 u8 port_mask, const u8 *mac, 349 u8 aging, u8 type) 350 { 351 u32 reg[3] = { 0 }; 352 int i; 353 354 reg[1] |= vid & CVID_MASK; 355 reg[1] |= ATA2_IVL; 356 reg[1] |= ATA2_FID(FID_BRIDGED); 357 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 358 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 359 /* STATIC_ENT indicate that entry is static wouldn't 360 * be aged out and STATIC_EMP specified as erasing an 361 * entry 362 */ 363 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 364 reg[1] |= mac[5] << MAC_BYTE_5; 365 reg[1] |= mac[4] << MAC_BYTE_4; 366 reg[0] |= mac[3] << MAC_BYTE_3; 367 reg[0] |= mac[2] << MAC_BYTE_2; 368 reg[0] |= mac[1] << MAC_BYTE_1; 369 reg[0] |= mac[0] << MAC_BYTE_0; 370 371 /* Write array into the ARL table */ 372 for (i = 0; i < 3; i++) 373 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 374 } 375 376 /* Set up switch core clock for MT7530 */ mt7530_pll_setup(struct mt7530_priv * priv)377 static void mt7530_pll_setup(struct mt7530_priv *priv) 378 { 379 /* Disable core clock */ 380 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 381 382 /* Disable PLL */ 383 core_write(priv, CORE_GSWPLL_GRP1, 0); 384 385 /* Set core clock into 500Mhz */ 386 core_write(priv, CORE_GSWPLL_GRP2, 387 RG_GSWPLL_POSDIV_500M(1) | 388 RG_GSWPLL_FBKDIV_500M(25)); 389 390 /* Enable PLL */ 391 core_write(priv, CORE_GSWPLL_GRP1, 392 RG_GSWPLL_EN_PRE | 393 RG_GSWPLL_POSDIV_200M(2) | 394 RG_GSWPLL_FBKDIV_200M(32)); 395 396 udelay(20); 397 398 /* Enable core clock */ 399 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 400 } 401 402 /* If port 6 is available as a CPU port, always prefer that as the default, 403 * otherwise don't care. 404 */ 405 static struct dsa_port * mt753x_preferred_default_local_cpu_port(struct dsa_switch * ds)406 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 407 { 408 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 409 410 if (dsa_port_is_cpu(cpu_dp)) 411 return cpu_dp; 412 413 return NULL; 414 } 415 416 /* Setup port 6 interface mode and TRGMII TX circuit */ 417 static int mt7530_pad_clk_setup(struct dsa_switch * ds,phy_interface_t interface)418 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 419 { 420 struct mt7530_priv *priv = ds->priv; 421 u32 ncpo1, ssc_delta, trgint, xtal; 422 423 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 424 425 if (xtal == HWTRAP_XTAL_20MHZ) { 426 dev_err(priv->dev, 427 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 428 __func__); 429 return -EINVAL; 430 } 431 432 switch (interface) { 433 case PHY_INTERFACE_MODE_RGMII: 434 trgint = 0; 435 break; 436 case PHY_INTERFACE_MODE_TRGMII: 437 trgint = 1; 438 if (xtal == HWTRAP_XTAL_25MHZ) 439 ssc_delta = 0x57; 440 else 441 ssc_delta = 0x87; 442 if (priv->id == ID_MT7621) { 443 /* PLL frequency: 125MHz: 1.0GBit */ 444 if (xtal == HWTRAP_XTAL_40MHZ) 445 ncpo1 = 0x0640; 446 if (xtal == HWTRAP_XTAL_25MHZ) 447 ncpo1 = 0x0a00; 448 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 449 if (xtal == HWTRAP_XTAL_40MHZ) 450 ncpo1 = 0x0c80; 451 if (xtal == HWTRAP_XTAL_25MHZ) 452 ncpo1 = 0x1400; 453 } 454 break; 455 default: 456 dev_err(priv->dev, "xMII interface %d not supported\n", 457 interface); 458 return -EINVAL; 459 } 460 461 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 462 P6_INTF_MODE(trgint)); 463 464 if (trgint) { 465 /* Disable the MT7530 TRGMII clocks */ 466 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 467 468 /* Setup the MT7530 TRGMII Tx Clock */ 469 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 470 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 471 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 472 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 473 core_write(priv, CORE_PLL_GROUP4, 474 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 475 RG_SYSPLL_BIAS_LPF_EN); 476 core_write(priv, CORE_PLL_GROUP2, 477 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 478 RG_SYSPLL_POSDIV(1)); 479 core_write(priv, CORE_PLL_GROUP7, 480 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 481 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 482 483 /* Enable the MT7530 TRGMII clocks */ 484 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 485 } 486 487 return 0; 488 } 489 mt7531_dual_sgmii_supported(struct mt7530_priv * priv)490 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 491 { 492 u32 val; 493 494 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 495 496 return (val & PAD_DUAL_SGMII_EN) != 0; 497 } 498 499 static int mt7531_pad_setup(struct dsa_switch * ds,phy_interface_t interface)500 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 501 { 502 return 0; 503 } 504 505 static void mt7531_pll_setup(struct mt7530_priv * priv)506 mt7531_pll_setup(struct mt7530_priv *priv) 507 { 508 u32 top_sig; 509 u32 hwstrap; 510 u32 xtal; 511 u32 val; 512 513 if (mt7531_dual_sgmii_supported(priv)) 514 return; 515 516 val = mt7530_read(priv, MT7531_CREV); 517 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 518 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 519 if ((val & CHIP_REV_M) > 0) 520 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 521 HWTRAP_XTAL_FSEL_25MHZ; 522 else 523 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 524 525 /* Step 1 : Disable MT7531 COREPLL */ 526 val = mt7530_read(priv, MT7531_PLLGP_EN); 527 val &= ~EN_COREPLL; 528 mt7530_write(priv, MT7531_PLLGP_EN, val); 529 530 /* Step 2: switch to XTAL output */ 531 val = mt7530_read(priv, MT7531_PLLGP_EN); 532 val |= SW_CLKSW; 533 mt7530_write(priv, MT7531_PLLGP_EN, val); 534 535 val = mt7530_read(priv, MT7531_PLLGP_CR0); 536 val &= ~RG_COREPLL_EN; 537 mt7530_write(priv, MT7531_PLLGP_CR0, val); 538 539 /* Step 3: disable PLLGP and enable program PLLGP */ 540 val = mt7530_read(priv, MT7531_PLLGP_EN); 541 val |= SW_PLLGP; 542 mt7530_write(priv, MT7531_PLLGP_EN, val); 543 544 /* Step 4: program COREPLL output frequency to 500MHz */ 545 val = mt7530_read(priv, MT7531_PLLGP_CR0); 546 val &= ~RG_COREPLL_POSDIV_M; 547 val |= 2 << RG_COREPLL_POSDIV_S; 548 mt7530_write(priv, MT7531_PLLGP_CR0, val); 549 usleep_range(25, 35); 550 551 switch (xtal) { 552 case HWTRAP_XTAL_FSEL_25MHZ: 553 val = mt7530_read(priv, MT7531_PLLGP_CR0); 554 val &= ~RG_COREPLL_SDM_PCW_M; 555 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 556 mt7530_write(priv, MT7531_PLLGP_CR0, val); 557 break; 558 case HWTRAP_XTAL_FSEL_40MHZ: 559 val = mt7530_read(priv, MT7531_PLLGP_CR0); 560 val &= ~RG_COREPLL_SDM_PCW_M; 561 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 562 mt7530_write(priv, MT7531_PLLGP_CR0, val); 563 break; 564 } 565 566 /* Set feedback divide ratio update signal to high */ 567 val = mt7530_read(priv, MT7531_PLLGP_CR0); 568 val |= RG_COREPLL_SDM_PCW_CHG; 569 mt7530_write(priv, MT7531_PLLGP_CR0, val); 570 /* Wait for at least 16 XTAL clocks */ 571 usleep_range(10, 20); 572 573 /* Step 5: set feedback divide ratio update signal to low */ 574 val = mt7530_read(priv, MT7531_PLLGP_CR0); 575 val &= ~RG_COREPLL_SDM_PCW_CHG; 576 mt7530_write(priv, MT7531_PLLGP_CR0, val); 577 578 /* Enable 325M clock for SGMII */ 579 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 580 581 /* Enable 250SSC clock for RGMII */ 582 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 583 584 /* Step 6: Enable MT7531 PLL */ 585 val = mt7530_read(priv, MT7531_PLLGP_CR0); 586 val |= RG_COREPLL_EN; 587 mt7530_write(priv, MT7531_PLLGP_CR0, val); 588 589 val = mt7530_read(priv, MT7531_PLLGP_EN); 590 val |= EN_COREPLL; 591 mt7530_write(priv, MT7531_PLLGP_EN, val); 592 usleep_range(25, 35); 593 } 594 595 static void mt7530_mib_reset(struct dsa_switch * ds)596 mt7530_mib_reset(struct dsa_switch *ds) 597 { 598 struct mt7530_priv *priv = ds->priv; 599 600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 601 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 602 } 603 mt7530_phy_read_c22(struct mt7530_priv * priv,int port,int regnum)604 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 605 { 606 return mdiobus_read_nested(priv->bus, port, regnum); 607 } 608 mt7530_phy_write_c22(struct mt7530_priv * priv,int port,int regnum,u16 val)609 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 610 u16 val) 611 { 612 return mdiobus_write_nested(priv->bus, port, regnum, val); 613 } 614 mt7530_phy_read_c45(struct mt7530_priv * priv,int port,int devad,int regnum)615 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 616 int devad, int regnum) 617 { 618 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 619 } 620 mt7530_phy_write_c45(struct mt7530_priv * priv,int port,int devad,int regnum,u16 val)621 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 622 int regnum, u16 val) 623 { 624 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 625 } 626 627 static int mt7531_ind_c45_phy_read(struct mt7530_priv * priv,int port,int devad,int regnum)628 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 629 int regnum) 630 { 631 struct mt7530_dummy_poll p; 632 u32 reg, val; 633 int ret; 634 635 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 636 637 mt7530_mutex_lock(priv); 638 639 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 640 !(val & MT7531_PHY_ACS_ST), 20, 100000); 641 if (ret < 0) { 642 dev_err(priv->dev, "poll timeout\n"); 643 goto out; 644 } 645 646 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 647 MT7531_MDIO_DEV_ADDR(devad) | regnum; 648 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 649 650 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 651 !(val & MT7531_PHY_ACS_ST), 20, 100000); 652 if (ret < 0) { 653 dev_err(priv->dev, "poll timeout\n"); 654 goto out; 655 } 656 657 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 658 MT7531_MDIO_DEV_ADDR(devad); 659 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 660 661 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 662 !(val & MT7531_PHY_ACS_ST), 20, 100000); 663 if (ret < 0) { 664 dev_err(priv->dev, "poll timeout\n"); 665 goto out; 666 } 667 668 ret = val & MT7531_MDIO_RW_DATA_MASK; 669 out: 670 mt7530_mutex_unlock(priv); 671 672 return ret; 673 } 674 675 static int mt7531_ind_c45_phy_write(struct mt7530_priv * priv,int port,int devad,int regnum,u16 data)676 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 677 int regnum, u16 data) 678 { 679 struct mt7530_dummy_poll p; 680 u32 val, reg; 681 int ret; 682 683 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 684 685 mt7530_mutex_lock(priv); 686 687 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 688 !(val & MT7531_PHY_ACS_ST), 20, 100000); 689 if (ret < 0) { 690 dev_err(priv->dev, "poll timeout\n"); 691 goto out; 692 } 693 694 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 695 MT7531_MDIO_DEV_ADDR(devad) | regnum; 696 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 697 698 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 699 !(val & MT7531_PHY_ACS_ST), 20, 100000); 700 if (ret < 0) { 701 dev_err(priv->dev, "poll timeout\n"); 702 goto out; 703 } 704 705 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 706 MT7531_MDIO_DEV_ADDR(devad) | data; 707 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 708 709 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 710 !(val & MT7531_PHY_ACS_ST), 20, 100000); 711 if (ret < 0) { 712 dev_err(priv->dev, "poll timeout\n"); 713 goto out; 714 } 715 716 out: 717 mt7530_mutex_unlock(priv); 718 719 return ret; 720 } 721 722 static int mt7531_ind_c22_phy_read(struct mt7530_priv * priv,int port,int regnum)723 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 724 { 725 struct mt7530_dummy_poll p; 726 int ret; 727 u32 val; 728 729 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 730 731 mt7530_mutex_lock(priv); 732 733 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 734 !(val & MT7531_PHY_ACS_ST), 20, 100000); 735 if (ret < 0) { 736 dev_err(priv->dev, "poll timeout\n"); 737 goto out; 738 } 739 740 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 741 MT7531_MDIO_REG_ADDR(regnum); 742 743 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 744 745 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 746 !(val & MT7531_PHY_ACS_ST), 20, 100000); 747 if (ret < 0) { 748 dev_err(priv->dev, "poll timeout\n"); 749 goto out; 750 } 751 752 ret = val & MT7531_MDIO_RW_DATA_MASK; 753 out: 754 mt7530_mutex_unlock(priv); 755 756 return ret; 757 } 758 759 static int mt7531_ind_c22_phy_write(struct mt7530_priv * priv,int port,int regnum,u16 data)760 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 761 u16 data) 762 { 763 struct mt7530_dummy_poll p; 764 int ret; 765 u32 reg; 766 767 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 768 769 mt7530_mutex_lock(priv); 770 771 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 772 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 773 if (ret < 0) { 774 dev_err(priv->dev, "poll timeout\n"); 775 goto out; 776 } 777 778 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 779 MT7531_MDIO_REG_ADDR(regnum) | data; 780 781 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 782 783 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 784 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 785 if (ret < 0) { 786 dev_err(priv->dev, "poll timeout\n"); 787 goto out; 788 } 789 790 out: 791 mt7530_mutex_unlock(priv); 792 793 return ret; 794 } 795 796 static int mt753x_phy_read_c22(struct mii_bus * bus,int port,int regnum)797 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 798 { 799 struct mt7530_priv *priv = bus->priv; 800 801 return priv->info->phy_read_c22(priv, port, regnum); 802 } 803 804 static int mt753x_phy_read_c45(struct mii_bus * bus,int port,int devad,int regnum)805 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 806 { 807 struct mt7530_priv *priv = bus->priv; 808 809 return priv->info->phy_read_c45(priv, port, devad, regnum); 810 } 811 812 static int mt753x_phy_write_c22(struct mii_bus * bus,int port,int regnum,u16 val)813 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 814 { 815 struct mt7530_priv *priv = bus->priv; 816 817 return priv->info->phy_write_c22(priv, port, regnum, val); 818 } 819 820 static int mt753x_phy_write_c45(struct mii_bus * bus,int port,int devad,int regnum,u16 val)821 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 822 u16 val) 823 { 824 struct mt7530_priv *priv = bus->priv; 825 826 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 827 } 828 829 static void mt7530_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)830 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 831 uint8_t *data) 832 { 833 int i; 834 835 if (stringset != ETH_SS_STATS) 836 return; 837 838 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 839 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 840 ETH_GSTRING_LEN); 841 } 842 843 static void mt7530_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)844 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 845 uint64_t *data) 846 { 847 struct mt7530_priv *priv = ds->priv; 848 const struct mt7530_mib_desc *mib; 849 u32 reg, i; 850 u64 hi; 851 852 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 853 mib = &mt7530_mib[i]; 854 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 855 856 data[i] = mt7530_read(priv, reg); 857 if (mib->size == 2) { 858 hi = mt7530_read(priv, reg + 4); 859 data[i] |= hi << 32; 860 } 861 } 862 } 863 864 static int mt7530_get_sset_count(struct dsa_switch * ds,int port,int sset)865 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 866 { 867 if (sset != ETH_SS_STATS) 868 return 0; 869 870 return ARRAY_SIZE(mt7530_mib); 871 } 872 873 static int mt7530_set_ageing_time(struct dsa_switch * ds,unsigned int msecs)874 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 875 { 876 struct mt7530_priv *priv = ds->priv; 877 unsigned int secs = msecs / 1000; 878 unsigned int tmp_age_count; 879 unsigned int error = -1; 880 unsigned int age_count; 881 unsigned int age_unit; 882 883 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 884 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 885 return -ERANGE; 886 887 /* iterate through all possible age_count to find the closest pair */ 888 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 889 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 890 891 if (tmp_age_unit <= AGE_UNIT_MAX) { 892 unsigned int tmp_error = secs - 893 (tmp_age_count + 1) * (tmp_age_unit + 1); 894 895 /* found a closer pair */ 896 if (error > tmp_error) { 897 error = tmp_error; 898 age_count = tmp_age_count; 899 age_unit = tmp_age_unit; 900 } 901 902 /* found the exact match, so break the loop */ 903 if (!error) 904 break; 905 } 906 } 907 908 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 909 910 return 0; 911 } 912 p5_intf_modes(unsigned int p5_interface)913 static const char *p5_intf_modes(unsigned int p5_interface) 914 { 915 switch (p5_interface) { 916 case P5_DISABLED: 917 return "DISABLED"; 918 case P5_INTF_SEL_PHY_P0: 919 return "PHY P0"; 920 case P5_INTF_SEL_PHY_P4: 921 return "PHY P4"; 922 case P5_INTF_SEL_GMAC5: 923 return "GMAC5"; 924 case P5_INTF_SEL_GMAC5_SGMII: 925 return "GMAC5_SGMII"; 926 default: 927 return "unknown"; 928 } 929 } 930 mt7530_setup_port5(struct dsa_switch * ds,phy_interface_t interface)931 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 932 { 933 struct mt7530_priv *priv = ds->priv; 934 u8 tx_delay = 0; 935 int val; 936 937 mutex_lock(&priv->reg_mutex); 938 939 val = mt7530_read(priv, MT7530_MHWTRAP); 940 941 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 942 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 943 944 switch (priv->p5_intf_sel) { 945 case P5_INTF_SEL_PHY_P0: 946 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 947 val |= MHWTRAP_PHY0_SEL; 948 fallthrough; 949 case P5_INTF_SEL_PHY_P4: 950 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 951 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 952 953 /* Setup the MAC by default for the cpu port */ 954 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 955 break; 956 case P5_INTF_SEL_GMAC5: 957 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 958 val &= ~MHWTRAP_P5_DIS; 959 break; 960 case P5_DISABLED: 961 interface = PHY_INTERFACE_MODE_NA; 962 break; 963 default: 964 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 965 priv->p5_intf_sel); 966 goto unlock_exit; 967 } 968 969 /* Setup RGMII settings */ 970 if (phy_interface_mode_is_rgmii(interface)) { 971 val |= MHWTRAP_P5_RGMII_MODE; 972 973 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 974 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 975 976 /* Don't set delay in DSA mode */ 977 if (!dsa_is_dsa_port(priv->ds, 5) && 978 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 979 interface == PHY_INTERFACE_MODE_RGMII_ID)) 980 tx_delay = 4; /* n * 0.5 ns */ 981 982 /* P5 RGMII TX Clock Control: delay x */ 983 mt7530_write(priv, MT7530_P5RGMIITXCR, 984 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 985 986 /* reduce P5 RGMII Tx driving, 8mA */ 987 mt7530_write(priv, MT7530_IO_DRV_CR, 988 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 989 } 990 991 mt7530_write(priv, MT7530_MHWTRAP, val); 992 993 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 994 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 995 996 priv->p5_interface = interface; 997 998 unlock_exit: 999 mutex_unlock(&priv->reg_mutex); 1000 } 1001 1002 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL) 1003 * of the Open Systems Interconnection basic reference model (OSI/RM) are 1004 * described; the medium access control (MAC) and logical link control (LLC) 1005 * sublayers. The MAC sublayer is the one facing the physical layer. 1006 * 1007 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A 1008 * Bridge component comprises a MAC Relay Entity for interconnecting the Ports 1009 * of the Bridge, at least two Ports, and higher layer entities with at least a 1010 * Spanning Tree Protocol Entity included. 1011 * 1012 * Each Bridge Port also functions as an end station and shall provide the MAC 1013 * Service to an LLC Entity. Each instance of the MAC Service is provided to a 1014 * distinct LLC Entity that supports protocol identification, multiplexing, and 1015 * demultiplexing, for protocol data unit (PDU) transmission and reception by 1016 * one or more higher layer entities. 1017 * 1018 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC 1019 * Entity associated with each Bridge Port is modeled as being directly 1020 * connected to the attached Local Area Network (LAN). 1021 * 1022 * On the switch with CPU port architecture, CPU port functions as Management 1023 * Port, and the Management Port functionality is provided by software which 1024 * functions as an end station. Software is connected to an IEEE 802 LAN that is 1025 * wholly contained within the system that incorporates the Bridge. Software 1026 * provides access to the LLC Entity associated with each Bridge Port by the 1027 * value of the source port field on the special tag on the frame received by 1028 * software. 1029 * 1030 * We call frames that carry control information to determine the active 1031 * topology and current extent of each Virtual Local Area Network (VLAN), i.e., 1032 * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration 1033 * Protocol Data Units (MVRPDUs), and frames from other link constrained 1034 * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and 1035 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not 1036 * forwarded by a Bridge. Permanently configured entries in the filtering 1037 * database (FDB) ensure that such frames are discarded by the Forwarding 1038 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: 1039 * 1040 * Each of the reserved MAC addresses specified in Table 8-1 1041 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be 1042 * permanently configured in the FDB in C-VLAN components and ERs. 1043 * 1044 * Each of the reserved MAC addresses specified in Table 8-2 1045 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently 1046 * configured in the FDB in S-VLAN components. 1047 * 1048 * Each of the reserved MAC addresses specified in Table 8-3 1049 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in 1050 * TPMR components. 1051 * 1052 * The FDB entries for reserved MAC addresses shall specify filtering for all 1053 * Bridge Ports and all VIDs. Management shall not provide the capability to 1054 * modify or remove entries for reserved MAC addresses. 1055 * 1056 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of 1057 * propagation of PDUs within a Bridged Network, as follows: 1058 * 1059 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no 1060 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) 1061 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. 1062 * PDUs transmitted using this destination address, or any other addresses 1063 * that appear in Table 8-1, Table 8-2, and Table 8-3 1064 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can 1065 * therefore travel no further than those stations that can be reached via a 1066 * single individual LAN from the originating station. 1067 * 1068 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an 1069 * address that no conformant S-VLAN component, C-VLAN component, or MAC 1070 * Bridge can forward; however, this address is relayed by a TPMR component. 1071 * PDUs using this destination address, or any of the other addresses that 1072 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 1073 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by 1074 * any TPMRs but will propagate no further than the nearest S-VLAN component, 1075 * C-VLAN component, or MAC Bridge. 1076 * 1077 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address 1078 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is 1079 * relayed by TPMR components and S-VLAN components. PDUs using this 1080 * destination address, or any of the other addresses that appear in Table 8-1 1081 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]), 1082 * will be relayed by TPMR components and S-VLAN components but will propagate 1083 * no further than the nearest C-VLAN component or MAC Bridge. 1084 * 1085 * Because the LLC Entity associated with each Bridge Port is provided via CPU 1086 * port, we must not filter these frames but forward them to CPU port. 1087 * 1088 * In a Bridge, the transmission Port is majorly decided by ingress and egress 1089 * rules, FDB, and spanning tree Port State functions of the Forwarding Process. 1090 * For link-local frames, only CPU port should be designated as destination port 1091 * in the FDB, and the other functions of the Forwarding Process must not 1092 * interfere with the decision of the transmission Port. We call this process 1093 * trapping frames to CPU port. 1094 * 1095 * Therefore, on the switch with CPU port architecture, link-local frames must 1096 * be trapped to CPU port, and certain link-local frames received by a Port of a 1097 * Bridge comprising a TPMR component or an S-VLAN component must be excluded 1098 * from it. 1099 * 1100 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port 1101 * MAC Relay (TPMR) component as a TPMR component supports only a subset of the 1102 * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port 1103 * doesn't count) of this architecture will either function as a standard MAC 1104 * Bridge or a standard VLAN Bridge. 1105 * 1106 * Therefore, a Bridge of this architecture can only comprise S-VLAN components, 1107 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component, 1108 * we don't need to relay PDUs using the destination addresses specified on the 1109 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge 1110 * section where they must be relayed by TPMR components. 1111 * 1112 * One option to trap link-local frames to CPU port is to add static FDB entries 1113 * with CPU port designated as destination port. However, because that 1114 * Independent VLAN Learning (IVL) is being used on every VID, each entry only 1115 * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC 1116 * Bridge component or a C-VLAN component, there would have to be 16 times 4096 1117 * entries. This switch intellectual property can only hold a maximum of 2048 1118 * entries. Using this option, there also isn't a mechanism to prevent 1119 * link-local frames from being discarded when the spanning tree Port State of 1120 * the reception Port is discarding. 1121 * 1122 * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 1123 * registers. Whilst this applies to every VID, it doesn't contain all of the 1124 * reserved MAC addresses without affecting the remaining Standard Group MAC 1125 * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the 1126 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination 1127 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF 1128 * destination addresses which may be relayed by MAC Bridges or VLAN Bridges. 1129 * The latter option provides better but not complete conformance. 1130 * 1131 * This switch intellectual property also does not provide a mechanism to trap 1132 * link-local frames with specific destination addresses to CPU port by Bridge, 1133 * to conform to the filtering rules for the distinct Bridge components. 1134 * 1135 * Therefore, regardless of the type of the Bridge component, link-local frames 1136 * with these destination addresses will be trapped to CPU port: 1137 * 1138 * 01-80-C2-00-00-[00,01,02,03,0E] 1139 * 1140 * In a Bridge comprising a MAC Bridge component or a C-VLAN component: 1141 * 1142 * Link-local frames with these destination addresses won't be trapped to CPU 1143 * port which won't conform to IEEE Std 802.1Q-2022: 1144 * 1145 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] 1146 * 1147 * In a Bridge comprising an S-VLAN component: 1148 * 1149 * Link-local frames with these destination addresses will be trapped to CPU 1150 * port which won't conform to IEEE Std 802.1Q-2022: 1151 * 1152 * 01-80-C2-00-00-00 1153 * 1154 * Link-local frames with these destination addresses won't be trapped to CPU 1155 * port which won't conform to IEEE Std 802.1Q-2022: 1156 * 1157 * 01-80-C2-00-00-[04,05,06,07,08,09,0A] 1158 * 1159 * To trap link-local frames to CPU port as conformant as this switch 1160 * intellectual property can allow, link-local frames are made to be regarded as 1161 * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual 1162 * property only lets the frames regarded as BPDUs bypass the spanning tree Port 1163 * State function of the Forwarding Process. 1164 * 1165 * The only remaining interference is the ingress rules. When the reception Port 1166 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in. 1167 * There doesn't seem to be a mechanism on the switch intellectual property to 1168 * have link-local frames bypass this function of the Forwarding Process. 1169 */ 1170 static void mt753x_trap_frames(struct mt7530_priv * priv)1171 mt753x_trap_frames(struct mt7530_priv *priv) 1172 { 1173 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them 1174 * VLAN-untagged. 1175 */ 1176 mt7530_rmw(priv, MT753X_BPC, 1177 MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK | 1178 MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK | 1179 MT753X_BPDU_PORT_FW_MASK, 1180 MT753X_PAE_BPDU_FR | 1181 MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1182 MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) | 1183 MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1184 MT753X_BPDU_CPU_ONLY); 1185 1186 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress 1187 * them VLAN-untagged. 1188 */ 1189 mt7530_rmw(priv, MT753X_RGAC1, 1190 MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK | 1191 MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR | 1192 MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK, 1193 MT753X_R02_BPDU_FR | 1194 MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1195 MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) | 1196 MT753X_R01_BPDU_FR | 1197 MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1198 MT753X_BPDU_CPU_ONLY); 1199 1200 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress 1201 * them VLAN-untagged. 1202 */ 1203 mt7530_rmw(priv, MT753X_RGAC2, 1204 MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK | 1205 MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR | 1206 MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK, 1207 MT753X_R0E_BPDU_FR | 1208 MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1209 MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) | 1210 MT753X_R03_BPDU_FR | 1211 MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1212 MT753X_BPDU_CPU_ONLY); 1213 } 1214 1215 static int mt753x_cpu_port_enable(struct dsa_switch * ds,int port)1216 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1217 { 1218 struct mt7530_priv *priv = ds->priv; 1219 int ret; 1220 1221 /* Setup max capability of CPU port at first */ 1222 if (priv->info->cpu_port_config) { 1223 ret = priv->info->cpu_port_config(ds, port); 1224 if (ret) 1225 return ret; 1226 } 1227 1228 /* Enable Mediatek header mode on the cpu port */ 1229 mt7530_write(priv, MT7530_PVC_P(port), 1230 PORT_SPEC_TAG); 1231 1232 /* Enable flooding on the CPU port */ 1233 mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1234 UNU_FFP(BIT(port))); 1235 1236 /* Set CPU port number */ 1237 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 1238 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1239 1240 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1241 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1242 * is affine to the inbound user port. 1243 */ 1244 if (priv->id == ID_MT7531 || priv->id == ID_MT7988) 1245 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1246 1247 /* CPU port gets connected to all user ports of 1248 * the switch. 1249 */ 1250 mt7530_write(priv, MT7530_PCR_P(port), 1251 PCR_MATRIX(dsa_user_ports(priv->ds))); 1252 1253 /* Set to fallback mode for independent VLAN learning */ 1254 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1255 MT7530_PORT_FALLBACK_MODE); 1256 1257 return 0; 1258 } 1259 1260 static int mt7530_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)1261 mt7530_port_enable(struct dsa_switch *ds, int port, 1262 struct phy_device *phy) 1263 { 1264 struct dsa_port *dp = dsa_to_port(ds, port); 1265 struct mt7530_priv *priv = ds->priv; 1266 1267 mutex_lock(&priv->reg_mutex); 1268 1269 /* Allow the user port gets connected to the cpu port and also 1270 * restore the port matrix if the port is the member of a certain 1271 * bridge. 1272 */ 1273 if (dsa_port_is_user(dp)) { 1274 struct dsa_port *cpu_dp = dp->cpu_dp; 1275 1276 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1277 } 1278 priv->ports[port].enable = true; 1279 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1280 priv->ports[port].pm); 1281 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1282 1283 mutex_unlock(&priv->reg_mutex); 1284 1285 return 0; 1286 } 1287 1288 static void mt7530_port_disable(struct dsa_switch * ds,int port)1289 mt7530_port_disable(struct dsa_switch *ds, int port) 1290 { 1291 struct mt7530_priv *priv = ds->priv; 1292 1293 mutex_lock(&priv->reg_mutex); 1294 1295 /* Clear up all port matrix which could be restored in the next 1296 * enablement for the port. 1297 */ 1298 priv->ports[port].enable = false; 1299 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1300 PCR_MATRIX_CLR); 1301 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1302 1303 mutex_unlock(&priv->reg_mutex); 1304 } 1305 1306 static int mt7530_port_change_mtu(struct dsa_switch * ds,int port,int new_mtu)1307 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1308 { 1309 struct mt7530_priv *priv = ds->priv; 1310 int length; 1311 u32 val; 1312 1313 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1314 * largest MTU of the slave ports. Because the switch only has a global 1315 * RX length register, only allowing CPU port here is enough. 1316 */ 1317 if (!dsa_is_cpu_port(ds, port)) 1318 return 0; 1319 1320 mt7530_mutex_lock(priv); 1321 1322 val = mt7530_mii_read(priv, MT7530_GMACCR); 1323 val &= ~MAX_RX_PKT_LEN_MASK; 1324 1325 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1326 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1327 if (length <= 1522) { 1328 val |= MAX_RX_PKT_LEN_1522; 1329 } else if (length <= 1536) { 1330 val |= MAX_RX_PKT_LEN_1536; 1331 } else if (length <= 1552) { 1332 val |= MAX_RX_PKT_LEN_1552; 1333 } else { 1334 val &= ~MAX_RX_JUMBO_MASK; 1335 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1336 val |= MAX_RX_PKT_LEN_JUMBO; 1337 } 1338 1339 mt7530_mii_write(priv, MT7530_GMACCR, val); 1340 1341 mt7530_mutex_unlock(priv); 1342 1343 return 0; 1344 } 1345 1346 static int mt7530_port_max_mtu(struct dsa_switch * ds,int port)1347 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1348 { 1349 return MT7530_MAX_MTU; 1350 } 1351 1352 static void mt7530_stp_state_set(struct dsa_switch * ds,int port,u8 state)1353 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1354 { 1355 struct mt7530_priv *priv = ds->priv; 1356 u32 stp_state; 1357 1358 switch (state) { 1359 case BR_STATE_DISABLED: 1360 stp_state = MT7530_STP_DISABLED; 1361 break; 1362 case BR_STATE_BLOCKING: 1363 stp_state = MT7530_STP_BLOCKING; 1364 break; 1365 case BR_STATE_LISTENING: 1366 stp_state = MT7530_STP_LISTENING; 1367 break; 1368 case BR_STATE_LEARNING: 1369 stp_state = MT7530_STP_LEARNING; 1370 break; 1371 case BR_STATE_FORWARDING: 1372 default: 1373 stp_state = MT7530_STP_FORWARDING; 1374 break; 1375 } 1376 1377 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1378 FID_PST(FID_BRIDGED, stp_state)); 1379 } 1380 1381 static int mt7530_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1382 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1383 struct switchdev_brport_flags flags, 1384 struct netlink_ext_ack *extack) 1385 { 1386 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1387 BR_BCAST_FLOOD)) 1388 return -EINVAL; 1389 1390 return 0; 1391 } 1392 1393 static int mt7530_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1394 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1395 struct switchdev_brport_flags flags, 1396 struct netlink_ext_ack *extack) 1397 { 1398 struct mt7530_priv *priv = ds->priv; 1399 1400 if (flags.mask & BR_LEARNING) 1401 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1402 flags.val & BR_LEARNING ? 0 : SA_DIS); 1403 1404 if (flags.mask & BR_FLOOD) 1405 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1406 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1407 1408 if (flags.mask & BR_MCAST_FLOOD) 1409 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1410 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1411 1412 if (flags.mask & BR_BCAST_FLOOD) 1413 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1414 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1415 1416 return 0; 1417 } 1418 1419 static int mt7530_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)1420 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1421 struct dsa_bridge bridge, bool *tx_fwd_offload, 1422 struct netlink_ext_ack *extack) 1423 { 1424 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1425 struct dsa_port *cpu_dp = dp->cpu_dp; 1426 u32 port_bitmap = BIT(cpu_dp->index); 1427 struct mt7530_priv *priv = ds->priv; 1428 1429 mutex_lock(&priv->reg_mutex); 1430 1431 dsa_switch_for_each_user_port(other_dp, ds) { 1432 int other_port = other_dp->index; 1433 1434 if (dp == other_dp) 1435 continue; 1436 1437 /* Add this port to the port matrix of the other ports in the 1438 * same bridge. If the port is disabled, port matrix is kept 1439 * and not being setup until the port becomes enabled. 1440 */ 1441 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1442 continue; 1443 1444 if (priv->ports[other_port].enable) 1445 mt7530_set(priv, MT7530_PCR_P(other_port), 1446 PCR_MATRIX(BIT(port))); 1447 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1448 1449 port_bitmap |= BIT(other_port); 1450 } 1451 1452 /* Add the all other ports to this port matrix. */ 1453 if (priv->ports[port].enable) 1454 mt7530_rmw(priv, MT7530_PCR_P(port), 1455 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1456 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1457 1458 /* Set to fallback mode for independent VLAN learning */ 1459 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1460 MT7530_PORT_FALLBACK_MODE); 1461 1462 mutex_unlock(&priv->reg_mutex); 1463 1464 return 0; 1465 } 1466 1467 static void mt7530_port_set_vlan_unaware(struct dsa_switch * ds,int port)1468 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1469 { 1470 struct mt7530_priv *priv = ds->priv; 1471 bool all_user_ports_removed = true; 1472 int i; 1473 1474 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1475 * bridge. Don't set standalone ports to fallback mode. 1476 */ 1477 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1478 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1479 MT7530_PORT_FALLBACK_MODE); 1480 1481 mt7530_rmw(priv, MT7530_PVC_P(port), 1482 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1483 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1484 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1485 MT7530_VLAN_ACC_ALL); 1486 1487 /* Set PVID to 0 */ 1488 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1489 G0_PORT_VID_DEF); 1490 1491 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1492 if (dsa_is_user_port(ds, i) && 1493 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1494 all_user_ports_removed = false; 1495 break; 1496 } 1497 } 1498 1499 /* CPU port also does the same thing until all user ports belonging to 1500 * the CPU port get out of VLAN filtering mode. 1501 */ 1502 if (all_user_ports_removed) { 1503 struct dsa_port *dp = dsa_to_port(ds, port); 1504 struct dsa_port *cpu_dp = dp->cpu_dp; 1505 1506 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1507 PCR_MATRIX(dsa_user_ports(priv->ds))); 1508 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1509 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1510 } 1511 } 1512 1513 static void mt7530_port_set_vlan_aware(struct dsa_switch * ds,int port)1514 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1515 { 1516 struct mt7530_priv *priv = ds->priv; 1517 1518 /* Trapped into security mode allows packet forwarding through VLAN 1519 * table lookup. 1520 */ 1521 if (dsa_is_user_port(ds, port)) { 1522 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1523 MT7530_PORT_SECURITY_MODE); 1524 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1525 G0_PORT_VID(priv->ports[port].pvid)); 1526 1527 /* Only accept tagged frames if PVID is not set */ 1528 if (!priv->ports[port].pvid) 1529 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1530 MT7530_VLAN_ACC_TAGGED); 1531 1532 /* Set the port as a user port which is to be able to recognize 1533 * VID from incoming packets before fetching entry within the 1534 * VLAN table. 1535 */ 1536 mt7530_rmw(priv, MT7530_PVC_P(port), 1537 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1538 VLAN_ATTR(MT7530_VLAN_USER) | 1539 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1540 } else { 1541 /* Also set CPU ports to the "user" VLAN port attribute, to 1542 * allow VLAN classification, but keep the EG_TAG attribute as 1543 * "consistent" (i.o.w. don't change its value) for packets 1544 * received by the switch from the CPU, so that tagged packets 1545 * are forwarded to user ports as tagged, and untagged as 1546 * untagged. 1547 */ 1548 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1549 VLAN_ATTR(MT7530_VLAN_USER)); 1550 } 1551 } 1552 1553 static void mt7530_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)1554 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1555 struct dsa_bridge bridge) 1556 { 1557 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1558 struct dsa_port *cpu_dp = dp->cpu_dp; 1559 struct mt7530_priv *priv = ds->priv; 1560 1561 mutex_lock(&priv->reg_mutex); 1562 1563 dsa_switch_for_each_user_port(other_dp, ds) { 1564 int other_port = other_dp->index; 1565 1566 if (dp == other_dp) 1567 continue; 1568 1569 /* Remove this port from the port matrix of the other ports 1570 * in the same bridge. If the port is disabled, port matrix 1571 * is kept and not being setup until the port becomes enabled. 1572 */ 1573 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1574 continue; 1575 1576 if (priv->ports[other_port].enable) 1577 mt7530_clear(priv, MT7530_PCR_P(other_port), 1578 PCR_MATRIX(BIT(port))); 1579 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1580 } 1581 1582 /* Set the cpu port to be the only one in the port matrix of 1583 * this port. 1584 */ 1585 if (priv->ports[port].enable) 1586 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1587 PCR_MATRIX(BIT(cpu_dp->index))); 1588 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1589 1590 /* When a port is removed from the bridge, the port would be set up 1591 * back to the default as is at initial boot which is a VLAN-unaware 1592 * port. 1593 */ 1594 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1595 MT7530_PORT_MATRIX_MODE); 1596 1597 mutex_unlock(&priv->reg_mutex); 1598 } 1599 1600 static int mt7530_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1601 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1602 const unsigned char *addr, u16 vid, 1603 struct dsa_db db) 1604 { 1605 struct mt7530_priv *priv = ds->priv; 1606 int ret; 1607 u8 port_mask = BIT(port); 1608 1609 mutex_lock(&priv->reg_mutex); 1610 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1611 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1612 mutex_unlock(&priv->reg_mutex); 1613 1614 return ret; 1615 } 1616 1617 static int mt7530_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1618 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1619 const unsigned char *addr, u16 vid, 1620 struct dsa_db db) 1621 { 1622 struct mt7530_priv *priv = ds->priv; 1623 int ret; 1624 u8 port_mask = BIT(port); 1625 1626 mutex_lock(&priv->reg_mutex); 1627 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1628 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1629 mutex_unlock(&priv->reg_mutex); 1630 1631 return ret; 1632 } 1633 1634 static int mt7530_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)1635 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1636 dsa_fdb_dump_cb_t *cb, void *data) 1637 { 1638 struct mt7530_priv *priv = ds->priv; 1639 struct mt7530_fdb _fdb = { 0 }; 1640 int cnt = MT7530_NUM_FDB_RECORDS; 1641 int ret = 0; 1642 u32 rsp = 0; 1643 1644 mutex_lock(&priv->reg_mutex); 1645 1646 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1647 if (ret < 0) 1648 goto err; 1649 1650 do { 1651 if (rsp & ATC_SRCH_HIT) { 1652 mt7530_fdb_read(priv, &_fdb); 1653 if (_fdb.port_mask & BIT(port)) { 1654 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1655 data); 1656 if (ret < 0) 1657 break; 1658 } 1659 } 1660 } while (--cnt && 1661 !(rsp & ATC_SRCH_END) && 1662 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1663 err: 1664 mutex_unlock(&priv->reg_mutex); 1665 1666 return 0; 1667 } 1668 1669 static int mt7530_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1670 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1671 const struct switchdev_obj_port_mdb *mdb, 1672 struct dsa_db db) 1673 { 1674 struct mt7530_priv *priv = ds->priv; 1675 const u8 *addr = mdb->addr; 1676 u16 vid = mdb->vid; 1677 u8 port_mask = 0; 1678 int ret; 1679 1680 mutex_lock(&priv->reg_mutex); 1681 1682 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1683 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1684 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1685 & PORT_MAP_MASK; 1686 1687 port_mask |= BIT(port); 1688 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1689 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1690 1691 mutex_unlock(&priv->reg_mutex); 1692 1693 return ret; 1694 } 1695 1696 static int mt7530_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1697 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1698 const struct switchdev_obj_port_mdb *mdb, 1699 struct dsa_db db) 1700 { 1701 struct mt7530_priv *priv = ds->priv; 1702 const u8 *addr = mdb->addr; 1703 u16 vid = mdb->vid; 1704 u8 port_mask = 0; 1705 int ret; 1706 1707 mutex_lock(&priv->reg_mutex); 1708 1709 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1710 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1711 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1712 & PORT_MAP_MASK; 1713 1714 port_mask &= ~BIT(port); 1715 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1716 port_mask ? STATIC_ENT : STATIC_EMP); 1717 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1718 1719 mutex_unlock(&priv->reg_mutex); 1720 1721 return ret; 1722 } 1723 1724 static int mt7530_vlan_cmd(struct mt7530_priv * priv,enum mt7530_vlan_cmd cmd,u16 vid)1725 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1726 { 1727 struct mt7530_dummy_poll p; 1728 u32 val; 1729 int ret; 1730 1731 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1732 mt7530_write(priv, MT7530_VTCR, val); 1733 1734 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1735 ret = readx_poll_timeout(_mt7530_read, &p, val, 1736 !(val & VTCR_BUSY), 20, 20000); 1737 if (ret < 0) { 1738 dev_err(priv->dev, "poll timeout\n"); 1739 return ret; 1740 } 1741 1742 val = mt7530_read(priv, MT7530_VTCR); 1743 if (val & VTCR_INVALID) { 1744 dev_err(priv->dev, "read VTCR invalid\n"); 1745 return -EINVAL; 1746 } 1747 1748 return 0; 1749 } 1750 1751 static int mt7530_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1752 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1753 struct netlink_ext_ack *extack) 1754 { 1755 struct dsa_port *dp = dsa_to_port(ds, port); 1756 struct dsa_port *cpu_dp = dp->cpu_dp; 1757 1758 if (vlan_filtering) { 1759 /* The port is being kept as VLAN-unaware port when bridge is 1760 * set up with vlan_filtering not being set, Otherwise, the 1761 * port and the corresponding CPU port is required the setup 1762 * for becoming a VLAN-aware port. 1763 */ 1764 mt7530_port_set_vlan_aware(ds, port); 1765 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1766 } else { 1767 mt7530_port_set_vlan_unaware(ds, port); 1768 } 1769 1770 return 0; 1771 } 1772 1773 static void mt7530_hw_vlan_add(struct mt7530_priv * priv,struct mt7530_hw_vlan_entry * entry)1774 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1775 struct mt7530_hw_vlan_entry *entry) 1776 { 1777 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1778 u8 new_members; 1779 u32 val; 1780 1781 new_members = entry->old_members | BIT(entry->port); 1782 1783 /* Validate the entry with independent learning, create egress tag per 1784 * VLAN and joining the port as one of the port members. 1785 */ 1786 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1787 VLAN_VALID; 1788 mt7530_write(priv, MT7530_VAWD1, val); 1789 1790 /* Decide whether adding tag or not for those outgoing packets from the 1791 * port inside the VLAN. 1792 * CPU port is always taken as a tagged port for serving more than one 1793 * VLANs across and also being applied with egress type stack mode for 1794 * that VLAN tags would be appended after hardware special tag used as 1795 * DSA tag. 1796 */ 1797 if (dsa_port_is_cpu(dp)) 1798 val = MT7530_VLAN_EGRESS_STACK; 1799 else if (entry->untagged) 1800 val = MT7530_VLAN_EGRESS_UNTAG; 1801 else 1802 val = MT7530_VLAN_EGRESS_TAG; 1803 mt7530_rmw(priv, MT7530_VAWD2, 1804 ETAG_CTRL_P_MASK(entry->port), 1805 ETAG_CTRL_P(entry->port, val)); 1806 } 1807 1808 static void mt7530_hw_vlan_del(struct mt7530_priv * priv,struct mt7530_hw_vlan_entry * entry)1809 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1810 struct mt7530_hw_vlan_entry *entry) 1811 { 1812 u8 new_members; 1813 u32 val; 1814 1815 new_members = entry->old_members & ~BIT(entry->port); 1816 1817 val = mt7530_read(priv, MT7530_VAWD1); 1818 if (!(val & VLAN_VALID)) { 1819 dev_err(priv->dev, 1820 "Cannot be deleted due to invalid entry\n"); 1821 return; 1822 } 1823 1824 if (new_members) { 1825 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1826 VLAN_VALID; 1827 mt7530_write(priv, MT7530_VAWD1, val); 1828 } else { 1829 mt7530_write(priv, MT7530_VAWD1, 0); 1830 mt7530_write(priv, MT7530_VAWD2, 0); 1831 } 1832 } 1833 1834 static void mt7530_hw_vlan_update(struct mt7530_priv * priv,u16 vid,struct mt7530_hw_vlan_entry * entry,mt7530_vlan_op vlan_op)1835 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1836 struct mt7530_hw_vlan_entry *entry, 1837 mt7530_vlan_op vlan_op) 1838 { 1839 u32 val; 1840 1841 /* Fetch entry */ 1842 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1843 1844 val = mt7530_read(priv, MT7530_VAWD1); 1845 1846 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1847 1848 /* Manipulate entry */ 1849 vlan_op(priv, entry); 1850 1851 /* Flush result to hardware */ 1852 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1853 } 1854 1855 static int mt7530_setup_vlan0(struct mt7530_priv * priv)1856 mt7530_setup_vlan0(struct mt7530_priv *priv) 1857 { 1858 u32 val; 1859 1860 /* Validate the entry with independent learning, keep the original 1861 * ingress tag attribute. 1862 */ 1863 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1864 VLAN_VALID; 1865 mt7530_write(priv, MT7530_VAWD1, val); 1866 1867 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1868 } 1869 1870 static int mt7530_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1871 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1872 const struct switchdev_obj_port_vlan *vlan, 1873 struct netlink_ext_ack *extack) 1874 { 1875 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1876 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1877 struct mt7530_hw_vlan_entry new_entry; 1878 struct mt7530_priv *priv = ds->priv; 1879 1880 mutex_lock(&priv->reg_mutex); 1881 1882 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1883 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1884 1885 if (pvid) { 1886 priv->ports[port].pvid = vlan->vid; 1887 1888 /* Accept all frames if PVID is set */ 1889 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1890 MT7530_VLAN_ACC_ALL); 1891 1892 /* Only configure PVID if VLAN filtering is enabled */ 1893 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1894 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1895 G0_PORT_VID_MASK, 1896 G0_PORT_VID(vlan->vid)); 1897 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1898 /* This VLAN is overwritten without PVID, so unset it */ 1899 priv->ports[port].pvid = G0_PORT_VID_DEF; 1900 1901 /* Only accept tagged frames if the port is VLAN-aware */ 1902 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1903 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1904 MT7530_VLAN_ACC_TAGGED); 1905 1906 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1907 G0_PORT_VID_DEF); 1908 } 1909 1910 mutex_unlock(&priv->reg_mutex); 1911 1912 return 0; 1913 } 1914 1915 static int mt7530_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1916 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1917 const struct switchdev_obj_port_vlan *vlan) 1918 { 1919 struct mt7530_hw_vlan_entry target_entry; 1920 struct mt7530_priv *priv = ds->priv; 1921 1922 mutex_lock(&priv->reg_mutex); 1923 1924 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1925 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1926 mt7530_hw_vlan_del); 1927 1928 /* PVID is being restored to the default whenever the PVID port 1929 * is being removed from the VLAN. 1930 */ 1931 if (priv->ports[port].pvid == vlan->vid) { 1932 priv->ports[port].pvid = G0_PORT_VID_DEF; 1933 1934 /* Only accept tagged frames if the port is VLAN-aware */ 1935 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1936 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1937 MT7530_VLAN_ACC_TAGGED); 1938 1939 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1940 G0_PORT_VID_DEF); 1941 } 1942 1943 1944 mutex_unlock(&priv->reg_mutex); 1945 1946 return 0; 1947 } 1948 mt753x_mirror_port_get(unsigned int id,u32 val)1949 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1950 { 1951 return (id == ID_MT7531 || id == ID_MT7988) ? 1952 MT7531_MIRROR_PORT_GET(val) : 1953 MIRROR_PORT(val); 1954 } 1955 mt753x_mirror_port_set(unsigned int id,u32 val)1956 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1957 { 1958 return (id == ID_MT7531 || id == ID_MT7988) ? 1959 MT7531_MIRROR_PORT_SET(val) : 1960 MIRROR_PORT(val); 1961 } 1962 mt753x_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)1963 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1964 struct dsa_mall_mirror_tc_entry *mirror, 1965 bool ingress, struct netlink_ext_ack *extack) 1966 { 1967 struct mt7530_priv *priv = ds->priv; 1968 int monitor_port; 1969 u32 val; 1970 1971 /* Check for existent entry */ 1972 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1973 return -EEXIST; 1974 1975 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1976 1977 /* MT7530 only supports one monitor port */ 1978 monitor_port = mt753x_mirror_port_get(priv->id, val); 1979 if (val & MT753X_MIRROR_EN(priv->id) && 1980 monitor_port != mirror->to_local_port) 1981 return -EEXIST; 1982 1983 val |= MT753X_MIRROR_EN(priv->id); 1984 val &= ~MT753X_MIRROR_MASK(priv->id); 1985 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1986 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1987 1988 val = mt7530_read(priv, MT7530_PCR_P(port)); 1989 if (ingress) { 1990 val |= PORT_RX_MIR; 1991 priv->mirror_rx |= BIT(port); 1992 } else { 1993 val |= PORT_TX_MIR; 1994 priv->mirror_tx |= BIT(port); 1995 } 1996 mt7530_write(priv, MT7530_PCR_P(port), val); 1997 1998 return 0; 1999 } 2000 mt753x_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)2001 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 2002 struct dsa_mall_mirror_tc_entry *mirror) 2003 { 2004 struct mt7530_priv *priv = ds->priv; 2005 u32 val; 2006 2007 val = mt7530_read(priv, MT7530_PCR_P(port)); 2008 if (mirror->ingress) { 2009 val &= ~PORT_RX_MIR; 2010 priv->mirror_rx &= ~BIT(port); 2011 } else { 2012 val &= ~PORT_TX_MIR; 2013 priv->mirror_tx &= ~BIT(port); 2014 } 2015 mt7530_write(priv, MT7530_PCR_P(port), val); 2016 2017 if (!priv->mirror_rx && !priv->mirror_tx) { 2018 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 2019 val &= ~MT753X_MIRROR_EN(priv->id); 2020 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 2021 } 2022 } 2023 2024 static enum dsa_tag_protocol mtk_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)2025 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 2026 enum dsa_tag_protocol mp) 2027 { 2028 return DSA_TAG_PROTO_MTK; 2029 } 2030 2031 #ifdef CONFIG_GPIOLIB 2032 static inline u32 mt7530_gpio_to_bit(unsigned int offset)2033 mt7530_gpio_to_bit(unsigned int offset) 2034 { 2035 /* Map GPIO offset to register bit 2036 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 2037 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 2038 * [10: 8] port 2 LED 0..2 as GPIO 6..8 2039 * [14:12] port 3 LED 0..2 as GPIO 9..11 2040 * [18:16] port 4 LED 0..2 as GPIO 12..14 2041 */ 2042 return BIT(offset + offset / 3); 2043 } 2044 2045 static int mt7530_gpio_get(struct gpio_chip * gc,unsigned int offset)2046 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 2047 { 2048 struct mt7530_priv *priv = gpiochip_get_data(gc); 2049 u32 bit = mt7530_gpio_to_bit(offset); 2050 2051 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 2052 } 2053 2054 static void mt7530_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)2055 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 2056 { 2057 struct mt7530_priv *priv = gpiochip_get_data(gc); 2058 u32 bit = mt7530_gpio_to_bit(offset); 2059 2060 if (value) 2061 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2062 else 2063 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2064 } 2065 2066 static int mt7530_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)2067 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 2068 { 2069 struct mt7530_priv *priv = gpiochip_get_data(gc); 2070 u32 bit = mt7530_gpio_to_bit(offset); 2071 2072 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 2073 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 2074 } 2075 2076 static int mt7530_gpio_direction_input(struct gpio_chip * gc,unsigned int offset)2077 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 2078 { 2079 struct mt7530_priv *priv = gpiochip_get_data(gc); 2080 u32 bit = mt7530_gpio_to_bit(offset); 2081 2082 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 2083 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 2084 2085 return 0; 2086 } 2087 2088 static int mt7530_gpio_direction_output(struct gpio_chip * gc,unsigned int offset,int value)2089 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 2090 { 2091 struct mt7530_priv *priv = gpiochip_get_data(gc); 2092 u32 bit = mt7530_gpio_to_bit(offset); 2093 2094 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 2095 2096 if (value) 2097 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2098 else 2099 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2100 2101 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 2102 2103 return 0; 2104 } 2105 2106 static int mt7530_setup_gpio(struct mt7530_priv * priv)2107 mt7530_setup_gpio(struct mt7530_priv *priv) 2108 { 2109 struct device *dev = priv->dev; 2110 struct gpio_chip *gc; 2111 2112 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 2113 if (!gc) 2114 return -ENOMEM; 2115 2116 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 2117 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 2118 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 2119 2120 gc->label = "mt7530"; 2121 gc->parent = dev; 2122 gc->owner = THIS_MODULE; 2123 gc->get_direction = mt7530_gpio_get_direction; 2124 gc->direction_input = mt7530_gpio_direction_input; 2125 gc->direction_output = mt7530_gpio_direction_output; 2126 gc->get = mt7530_gpio_get; 2127 gc->set = mt7530_gpio_set; 2128 gc->base = -1; 2129 gc->ngpio = 15; 2130 gc->can_sleep = true; 2131 2132 return devm_gpiochip_add_data(dev, gc, priv); 2133 } 2134 #endif /* CONFIG_GPIOLIB */ 2135 2136 static irqreturn_t mt7530_irq_thread_fn(int irq,void * dev_id)2137 mt7530_irq_thread_fn(int irq, void *dev_id) 2138 { 2139 struct mt7530_priv *priv = dev_id; 2140 bool handled = false; 2141 u32 val; 2142 int p; 2143 2144 mt7530_mutex_lock(priv); 2145 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 2146 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 2147 mt7530_mutex_unlock(priv); 2148 2149 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2150 if (BIT(p) & val) { 2151 unsigned int irq; 2152 2153 irq = irq_find_mapping(priv->irq_domain, p); 2154 handle_nested_irq(irq); 2155 handled = true; 2156 } 2157 } 2158 2159 return IRQ_RETVAL(handled); 2160 } 2161 2162 static void mt7530_irq_mask(struct irq_data * d)2163 mt7530_irq_mask(struct irq_data *d) 2164 { 2165 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2166 2167 priv->irq_enable &= ~BIT(d->hwirq); 2168 } 2169 2170 static void mt7530_irq_unmask(struct irq_data * d)2171 mt7530_irq_unmask(struct irq_data *d) 2172 { 2173 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2174 2175 priv->irq_enable |= BIT(d->hwirq); 2176 } 2177 2178 static void mt7530_irq_bus_lock(struct irq_data * d)2179 mt7530_irq_bus_lock(struct irq_data *d) 2180 { 2181 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2182 2183 mt7530_mutex_lock(priv); 2184 } 2185 2186 static void mt7530_irq_bus_sync_unlock(struct irq_data * d)2187 mt7530_irq_bus_sync_unlock(struct irq_data *d) 2188 { 2189 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2190 2191 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2192 mt7530_mutex_unlock(priv); 2193 } 2194 2195 static struct irq_chip mt7530_irq_chip = { 2196 .name = KBUILD_MODNAME, 2197 .irq_mask = mt7530_irq_mask, 2198 .irq_unmask = mt7530_irq_unmask, 2199 .irq_bus_lock = mt7530_irq_bus_lock, 2200 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 2201 }; 2202 2203 static int mt7530_irq_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)2204 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 2205 irq_hw_number_t hwirq) 2206 { 2207 irq_set_chip_data(irq, domain->host_data); 2208 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 2209 irq_set_nested_thread(irq, true); 2210 irq_set_noprobe(irq); 2211 2212 return 0; 2213 } 2214 2215 static const struct irq_domain_ops mt7530_irq_domain_ops = { 2216 .map = mt7530_irq_map, 2217 .xlate = irq_domain_xlate_onecell, 2218 }; 2219 2220 static void mt7988_irq_mask(struct irq_data * d)2221 mt7988_irq_mask(struct irq_data *d) 2222 { 2223 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2224 2225 priv->irq_enable &= ~BIT(d->hwirq); 2226 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2227 } 2228 2229 static void mt7988_irq_unmask(struct irq_data * d)2230 mt7988_irq_unmask(struct irq_data *d) 2231 { 2232 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2233 2234 priv->irq_enable |= BIT(d->hwirq); 2235 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2236 } 2237 2238 static struct irq_chip mt7988_irq_chip = { 2239 .name = KBUILD_MODNAME, 2240 .irq_mask = mt7988_irq_mask, 2241 .irq_unmask = mt7988_irq_unmask, 2242 }; 2243 2244 static int mt7988_irq_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)2245 mt7988_irq_map(struct irq_domain *domain, unsigned int irq, 2246 irq_hw_number_t hwirq) 2247 { 2248 irq_set_chip_data(irq, domain->host_data); 2249 irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq); 2250 irq_set_nested_thread(irq, true); 2251 irq_set_noprobe(irq); 2252 2253 return 0; 2254 } 2255 2256 static const struct irq_domain_ops mt7988_irq_domain_ops = { 2257 .map = mt7988_irq_map, 2258 .xlate = irq_domain_xlate_onecell, 2259 }; 2260 2261 static void mt7530_setup_mdio_irq(struct mt7530_priv * priv)2262 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2263 { 2264 struct dsa_switch *ds = priv->ds; 2265 int p; 2266 2267 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2268 if (BIT(p) & ds->phys_mii_mask) { 2269 unsigned int irq; 2270 2271 irq = irq_create_mapping(priv->irq_domain, p); 2272 ds->slave_mii_bus->irq[p] = irq; 2273 } 2274 } 2275 } 2276 2277 static int mt7530_setup_irq(struct mt7530_priv * priv)2278 mt7530_setup_irq(struct mt7530_priv *priv) 2279 { 2280 struct device *dev = priv->dev; 2281 struct device_node *np = dev->of_node; 2282 int ret; 2283 2284 if (!of_property_read_bool(np, "interrupt-controller")) { 2285 dev_info(dev, "no interrupt support\n"); 2286 return 0; 2287 } 2288 2289 priv->irq = of_irq_get(np, 0); 2290 if (priv->irq <= 0) { 2291 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2292 return priv->irq ? : -EINVAL; 2293 } 2294 2295 if (priv->id == ID_MT7988) 2296 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2297 &mt7988_irq_domain_ops, 2298 priv); 2299 else 2300 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2301 &mt7530_irq_domain_ops, 2302 priv); 2303 2304 if (!priv->irq_domain) { 2305 dev_err(dev, "failed to create IRQ domain\n"); 2306 return -ENOMEM; 2307 } 2308 2309 /* This register must be set for MT7530 to properly fire interrupts */ 2310 if (priv->id != ID_MT7531) 2311 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2312 2313 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2314 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2315 if (ret) { 2316 irq_domain_remove(priv->irq_domain); 2317 dev_err(dev, "failed to request IRQ: %d\n", ret); 2318 return ret; 2319 } 2320 2321 return 0; 2322 } 2323 2324 static void mt7530_free_mdio_irq(struct mt7530_priv * priv)2325 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2326 { 2327 int p; 2328 2329 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2330 if (BIT(p) & priv->ds->phys_mii_mask) { 2331 unsigned int irq; 2332 2333 irq = irq_find_mapping(priv->irq_domain, p); 2334 irq_dispose_mapping(irq); 2335 } 2336 } 2337 } 2338 2339 static void mt7530_free_irq_common(struct mt7530_priv * priv)2340 mt7530_free_irq_common(struct mt7530_priv *priv) 2341 { 2342 free_irq(priv->irq, priv); 2343 irq_domain_remove(priv->irq_domain); 2344 } 2345 2346 static void mt7530_free_irq(struct mt7530_priv * priv)2347 mt7530_free_irq(struct mt7530_priv *priv) 2348 { 2349 mt7530_free_mdio_irq(priv); 2350 mt7530_free_irq_common(priv); 2351 } 2352 2353 static int mt7530_setup_mdio(struct mt7530_priv * priv)2354 mt7530_setup_mdio(struct mt7530_priv *priv) 2355 { 2356 struct dsa_switch *ds = priv->ds; 2357 struct device *dev = priv->dev; 2358 struct mii_bus *bus; 2359 static int idx; 2360 int ret; 2361 2362 bus = devm_mdiobus_alloc(dev); 2363 if (!bus) 2364 return -ENOMEM; 2365 2366 ds->slave_mii_bus = bus; 2367 bus->priv = priv; 2368 bus->name = KBUILD_MODNAME "-mii"; 2369 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2370 bus->read = mt753x_phy_read_c22; 2371 bus->write = mt753x_phy_write_c22; 2372 bus->read_c45 = mt753x_phy_read_c45; 2373 bus->write_c45 = mt753x_phy_write_c45; 2374 bus->parent = dev; 2375 bus->phy_mask = ~ds->phys_mii_mask; 2376 2377 if (priv->irq) 2378 mt7530_setup_mdio_irq(priv); 2379 2380 ret = devm_mdiobus_register(dev, bus); 2381 if (ret) { 2382 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2383 if (priv->irq) 2384 mt7530_free_mdio_irq(priv); 2385 } 2386 2387 return ret; 2388 } 2389 2390 static int mt7530_setup(struct dsa_switch * ds)2391 mt7530_setup(struct dsa_switch *ds) 2392 { 2393 struct mt7530_priv *priv = ds->priv; 2394 struct device_node *dn = NULL; 2395 struct device_node *phy_node; 2396 struct device_node *mac_np; 2397 struct mt7530_dummy_poll p; 2398 phy_interface_t interface; 2399 struct dsa_port *cpu_dp; 2400 u32 id, val; 2401 int ret, i; 2402 2403 /* The parent node of master netdev which holds the common system 2404 * controller also is the container for two GMACs nodes representing 2405 * as two netdev instances. 2406 */ 2407 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2408 dn = cpu_dp->master->dev.of_node->parent; 2409 /* It doesn't matter which CPU port is found first, 2410 * their masters should share the same parent OF node 2411 */ 2412 break; 2413 } 2414 2415 if (!dn) { 2416 dev_err(ds->dev, "parent OF node of DSA master not found"); 2417 return -EINVAL; 2418 } 2419 2420 ds->assisted_learning_on_cpu_port = true; 2421 ds->mtu_enforcement_ingress = true; 2422 2423 if (priv->id == ID_MT7530) { 2424 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2425 ret = regulator_enable(priv->core_pwr); 2426 if (ret < 0) { 2427 dev_err(priv->dev, 2428 "Failed to enable core power: %d\n", ret); 2429 return ret; 2430 } 2431 2432 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2433 ret = regulator_enable(priv->io_pwr); 2434 if (ret < 0) { 2435 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2436 ret); 2437 return ret; 2438 } 2439 } 2440 2441 /* Reset whole chip through gpio pin or memory-mapped registers for 2442 * different type of hardware 2443 */ 2444 if (priv->mcm) { 2445 reset_control_assert(priv->rstc); 2446 usleep_range(5000, 5100); 2447 reset_control_deassert(priv->rstc); 2448 } else { 2449 gpiod_set_value_cansleep(priv->reset, 0); 2450 usleep_range(5000, 5100); 2451 gpiod_set_value_cansleep(priv->reset, 1); 2452 } 2453 2454 /* Waiting for MT7530 got to stable */ 2455 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2456 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2457 20, 1000000); 2458 if (ret < 0) { 2459 dev_err(priv->dev, "reset timeout\n"); 2460 return ret; 2461 } 2462 2463 id = mt7530_read(priv, MT7530_CREV); 2464 id >>= CHIP_NAME_SHIFT; 2465 if (id != MT7530_ID) { 2466 dev_err(priv->dev, "chip %x can't be supported\n", id); 2467 return -ENODEV; 2468 } 2469 2470 /* Reset the switch through internal reset */ 2471 mt7530_write(priv, MT7530_SYS_CTRL, 2472 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2473 SYS_CTRL_REG_RST); 2474 2475 /* Lower Tx driving for TRGMII path */ 2476 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2477 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2478 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2479 2480 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2481 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2482 RD_TAP_MASK, RD_TAP(16)); 2483 2484 /* Enable port 6 */ 2485 val = mt7530_read(priv, MT7530_MHWTRAP); 2486 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2487 val |= MHWTRAP_MANUAL; 2488 mt7530_write(priv, MT7530_MHWTRAP, val); 2489 2490 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2491 2492 if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ) 2493 mt7530_pll_setup(priv); 2494 2495 mt753x_trap_frames(priv); 2496 2497 /* Enable and reset MIB counters */ 2498 mt7530_mib_reset(ds); 2499 2500 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2501 /* Disable forwarding by default on all ports */ 2502 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2503 PCR_MATRIX_CLR); 2504 2505 /* Disable learning by default on all ports */ 2506 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2507 2508 if (dsa_is_cpu_port(ds, i)) { 2509 ret = mt753x_cpu_port_enable(ds, i); 2510 if (ret) 2511 return ret; 2512 } else { 2513 mt7530_port_disable(ds, i); 2514 2515 /* Set default PVID to 0 on all user ports */ 2516 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2517 G0_PORT_VID_DEF); 2518 } 2519 /* Enable consistent egress tag */ 2520 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2521 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2522 } 2523 2524 /* Allow mirroring frames received on the local port (monitor port). */ 2525 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2526 2527 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2528 ret = mt7530_setup_vlan0(priv); 2529 if (ret) 2530 return ret; 2531 2532 /* Setup port 5 */ 2533 priv->p5_intf_sel = P5_DISABLED; 2534 interface = PHY_INTERFACE_MODE_NA; 2535 2536 if (!dsa_is_unused_port(ds, 5)) { 2537 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2538 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2539 if (ret && ret != -ENODEV) 2540 return ret; 2541 } else { 2542 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2543 for_each_child_of_node(dn, mac_np) { 2544 if (!of_device_is_compatible(mac_np, 2545 "mediatek,eth-mac")) 2546 continue; 2547 2548 ret = of_property_read_u32(mac_np, "reg", &id); 2549 if (ret < 0 || id != 1) 2550 continue; 2551 2552 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2553 if (!phy_node) 2554 continue; 2555 2556 if (phy_node->parent == priv->dev->of_node->parent) { 2557 ret = of_get_phy_mode(mac_np, &interface); 2558 if (ret && ret != -ENODEV) { 2559 of_node_put(mac_np); 2560 of_node_put(phy_node); 2561 return ret; 2562 } 2563 id = of_mdio_parse_addr(ds->dev, phy_node); 2564 if (id == 0) 2565 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2566 if (id == 4) 2567 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2568 } 2569 of_node_put(mac_np); 2570 of_node_put(phy_node); 2571 break; 2572 } 2573 } 2574 2575 #ifdef CONFIG_GPIOLIB 2576 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2577 ret = mt7530_setup_gpio(priv); 2578 if (ret) 2579 return ret; 2580 } 2581 #endif /* CONFIG_GPIOLIB */ 2582 2583 mt7530_setup_port5(ds, interface); 2584 2585 /* Flush the FDB table */ 2586 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2587 if (ret < 0) 2588 return ret; 2589 2590 return 0; 2591 } 2592 2593 static int mt7531_setup_common(struct dsa_switch * ds)2594 mt7531_setup_common(struct dsa_switch *ds) 2595 { 2596 struct mt7530_priv *priv = ds->priv; 2597 int ret, i; 2598 2599 mt753x_trap_frames(priv); 2600 2601 /* Enable and reset MIB counters */ 2602 mt7530_mib_reset(ds); 2603 2604 /* Disable flooding on all ports */ 2605 mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2606 UNU_FFP_MASK); 2607 2608 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2609 /* Disable forwarding by default on all ports */ 2610 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2611 PCR_MATRIX_CLR); 2612 2613 /* Disable learning by default on all ports */ 2614 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2615 2616 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2617 2618 if (dsa_is_cpu_port(ds, i)) { 2619 ret = mt753x_cpu_port_enable(ds, i); 2620 if (ret) 2621 return ret; 2622 } else { 2623 mt7530_port_disable(ds, i); 2624 2625 /* Set default PVID to 0 on all user ports */ 2626 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2627 G0_PORT_VID_DEF); 2628 } 2629 2630 /* Enable consistent egress tag */ 2631 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2632 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2633 } 2634 2635 /* Allow mirroring frames received on the local port (monitor port). */ 2636 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2637 2638 /* Flush the FDB table */ 2639 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2640 if (ret < 0) 2641 return ret; 2642 2643 return 0; 2644 } 2645 2646 static int mt7531_setup(struct dsa_switch * ds)2647 mt7531_setup(struct dsa_switch *ds) 2648 { 2649 struct mt7530_priv *priv = ds->priv; 2650 struct mt7530_dummy_poll p; 2651 u32 val, id; 2652 int ret, i; 2653 2654 /* Reset whole chip through gpio pin or memory-mapped registers for 2655 * different type of hardware 2656 */ 2657 if (priv->mcm) { 2658 reset_control_assert(priv->rstc); 2659 usleep_range(5000, 5100); 2660 reset_control_deassert(priv->rstc); 2661 } else { 2662 gpiod_set_value_cansleep(priv->reset, 0); 2663 usleep_range(5000, 5100); 2664 gpiod_set_value_cansleep(priv->reset, 1); 2665 } 2666 2667 /* Waiting for MT7530 got to stable */ 2668 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2669 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2670 20, 1000000); 2671 if (ret < 0) { 2672 dev_err(priv->dev, "reset timeout\n"); 2673 return ret; 2674 } 2675 2676 id = mt7530_read(priv, MT7531_CREV); 2677 id >>= CHIP_NAME_SHIFT; 2678 2679 if (id != MT7531_ID) { 2680 dev_err(priv->dev, "chip %x can't be supported\n", id); 2681 return -ENODEV; 2682 } 2683 2684 /* all MACs must be forced link-down before sw reset */ 2685 for (i = 0; i < MT7530_NUM_PORTS; i++) 2686 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2687 2688 /* Reset the switch through internal reset */ 2689 mt7530_write(priv, MT7530_SYS_CTRL, 2690 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2691 SYS_CTRL_REG_RST); 2692 2693 mt7531_pll_setup(priv); 2694 2695 if (mt7531_dual_sgmii_supported(priv)) { 2696 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2697 2698 /* Let ds->slave_mii_bus be able to access external phy. */ 2699 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2700 MT7531_EXT_P_MDC_11); 2701 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2702 MT7531_EXT_P_MDIO_12); 2703 } else { 2704 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2705 } 2706 dev_dbg(ds->dev, "P5 support %s interface\n", 2707 p5_intf_modes(priv->p5_intf_sel)); 2708 2709 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2710 MT7531_GPIO0_INTERRUPT); 2711 2712 /* Let phylink decide the interface later. */ 2713 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2714 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2715 2716 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since 2717 * phy_device has not yet been created provided for 2718 * phy_[read,write]_mmd_indirect is called, we provide our own 2719 * mt7531_ind_mmd_phy_[read,write] to complete this function. 2720 */ 2721 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2722 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2723 val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE; 2724 val &= ~MT7531_PHY_PLL_OFF; 2725 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2726 CORE_PLL_GROUP4, val); 2727 2728 /* Disable EEE advertisement on the switch PHYs. */ 2729 for (i = MT753X_CTRL_PHY_ADDR; 2730 i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) { 2731 mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 2732 0); 2733 } 2734 2735 mt7531_setup_common(ds); 2736 2737 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2738 ret = mt7530_setup_vlan0(priv); 2739 if (ret) 2740 return ret; 2741 2742 ds->assisted_learning_on_cpu_port = true; 2743 ds->mtu_enforcement_ingress = true; 2744 2745 return 0; 2746 } 2747 mt7530_mac_port_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)2748 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2749 struct phylink_config *config) 2750 { 2751 switch (port) { 2752 case 0 ... 4: /* Internal phy */ 2753 __set_bit(PHY_INTERFACE_MODE_GMII, 2754 config->supported_interfaces); 2755 break; 2756 2757 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2758 phy_interface_set_rgmii(config->supported_interfaces); 2759 __set_bit(PHY_INTERFACE_MODE_MII, 2760 config->supported_interfaces); 2761 __set_bit(PHY_INTERFACE_MODE_GMII, 2762 config->supported_interfaces); 2763 break; 2764 2765 case 6: /* 1st cpu port */ 2766 __set_bit(PHY_INTERFACE_MODE_RGMII, 2767 config->supported_interfaces); 2768 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2769 config->supported_interfaces); 2770 break; 2771 } 2772 } 2773 mt7531_is_rgmii_port(struct mt7530_priv * priv,u32 port)2774 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2775 { 2776 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2777 } 2778 mt7531_mac_port_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)2779 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2780 struct phylink_config *config) 2781 { 2782 struct mt7530_priv *priv = ds->priv; 2783 2784 switch (port) { 2785 case 0 ... 4: /* Internal phy */ 2786 __set_bit(PHY_INTERFACE_MODE_GMII, 2787 config->supported_interfaces); 2788 break; 2789 2790 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2791 if (mt7531_is_rgmii_port(priv, port)) { 2792 phy_interface_set_rgmii(config->supported_interfaces); 2793 break; 2794 } 2795 fallthrough; 2796 2797 case 6: /* 1st cpu port supports sgmii/8023z only */ 2798 __set_bit(PHY_INTERFACE_MODE_SGMII, 2799 config->supported_interfaces); 2800 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2801 config->supported_interfaces); 2802 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2803 config->supported_interfaces); 2804 2805 config->mac_capabilities |= MAC_2500FD; 2806 break; 2807 } 2808 } 2809 mt7988_mac_port_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)2810 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2811 struct phylink_config *config) 2812 { 2813 phy_interface_zero(config->supported_interfaces); 2814 2815 switch (port) { 2816 case 0 ... 4: /* Internal phy */ 2817 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2818 config->supported_interfaces); 2819 break; 2820 2821 case 6: 2822 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2823 config->supported_interfaces); 2824 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2825 MAC_10000FD; 2826 } 2827 } 2828 2829 static int mt753x_pad_setup(struct dsa_switch * ds,const struct phylink_link_state * state)2830 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2831 { 2832 struct mt7530_priv *priv = ds->priv; 2833 2834 return priv->info->pad_setup(ds, state->interface); 2835 } 2836 2837 static int mt7530_mac_config(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)2838 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2839 phy_interface_t interface) 2840 { 2841 struct mt7530_priv *priv = ds->priv; 2842 2843 /* Only need to setup port5. */ 2844 if (port != 5) 2845 return 0; 2846 2847 mt7530_setup_port5(priv->ds, interface); 2848 2849 return 0; 2850 } 2851 mt7531_rgmii_setup(struct mt7530_priv * priv,u32 port,phy_interface_t interface,struct phy_device * phydev)2852 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2853 phy_interface_t interface, 2854 struct phy_device *phydev) 2855 { 2856 u32 val; 2857 2858 if (!mt7531_is_rgmii_port(priv, port)) { 2859 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2860 port); 2861 return -EINVAL; 2862 } 2863 2864 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2865 val |= GP_CLK_EN; 2866 val &= ~GP_MODE_MASK; 2867 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2868 val &= ~CLK_SKEW_IN_MASK; 2869 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2870 val &= ~CLK_SKEW_OUT_MASK; 2871 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2872 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2873 2874 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2875 if (!phydev || phy_driver_is_genphy(phydev)) { 2876 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2877 switch (interface) { 2878 case PHY_INTERFACE_MODE_RGMII: 2879 val |= TXCLK_NO_REVERSE; 2880 val |= RXCLK_NO_DELAY; 2881 break; 2882 case PHY_INTERFACE_MODE_RGMII_RXID: 2883 val |= TXCLK_NO_REVERSE; 2884 break; 2885 case PHY_INTERFACE_MODE_RGMII_TXID: 2886 val |= RXCLK_NO_DELAY; 2887 break; 2888 case PHY_INTERFACE_MODE_RGMII_ID: 2889 break; 2890 default: 2891 return -EINVAL; 2892 } 2893 } 2894 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2895 2896 return 0; 2897 } 2898 mt753x_is_mac_port(u32 port)2899 static bool mt753x_is_mac_port(u32 port) 2900 { 2901 return (port == 5 || port == 6); 2902 } 2903 2904 static int mt7988_mac_config(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)2905 mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2906 phy_interface_t interface) 2907 { 2908 if (dsa_is_cpu_port(ds, port) && 2909 interface == PHY_INTERFACE_MODE_INTERNAL) 2910 return 0; 2911 2912 return -EINVAL; 2913 } 2914 2915 static int mt7531_mac_config(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)2916 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2917 phy_interface_t interface) 2918 { 2919 struct mt7530_priv *priv = ds->priv; 2920 struct phy_device *phydev; 2921 struct dsa_port *dp; 2922 2923 if (!mt753x_is_mac_port(port)) { 2924 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2925 return -EINVAL; 2926 } 2927 2928 switch (interface) { 2929 case PHY_INTERFACE_MODE_RGMII: 2930 case PHY_INTERFACE_MODE_RGMII_ID: 2931 case PHY_INTERFACE_MODE_RGMII_RXID: 2932 case PHY_INTERFACE_MODE_RGMII_TXID: 2933 dp = dsa_to_port(ds, port); 2934 phydev = dp->slave->phydev; 2935 return mt7531_rgmii_setup(priv, port, interface, phydev); 2936 case PHY_INTERFACE_MODE_SGMII: 2937 case PHY_INTERFACE_MODE_NA: 2938 case PHY_INTERFACE_MODE_1000BASEX: 2939 case PHY_INTERFACE_MODE_2500BASEX: 2940 /* handled in SGMII PCS driver */ 2941 return 0; 2942 default: 2943 return -EINVAL; 2944 } 2945 2946 return -EINVAL; 2947 } 2948 2949 static int mt753x_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)2950 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2951 const struct phylink_link_state *state) 2952 { 2953 struct mt7530_priv *priv = ds->priv; 2954 2955 return priv->info->mac_port_config(ds, port, mode, state->interface); 2956 } 2957 2958 static struct phylink_pcs * mt753x_phylink_mac_select_pcs(struct dsa_switch * ds,int port,phy_interface_t interface)2959 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2960 phy_interface_t interface) 2961 { 2962 struct mt7530_priv *priv = ds->priv; 2963 2964 switch (interface) { 2965 case PHY_INTERFACE_MODE_TRGMII: 2966 return &priv->pcs[port].pcs; 2967 case PHY_INTERFACE_MODE_SGMII: 2968 case PHY_INTERFACE_MODE_1000BASEX: 2969 case PHY_INTERFACE_MODE_2500BASEX: 2970 return priv->ports[port].sgmii_pcs; 2971 default: 2972 return NULL; 2973 } 2974 } 2975 2976 static void mt753x_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)2977 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2978 const struct phylink_link_state *state) 2979 { 2980 struct mt7530_priv *priv = ds->priv; 2981 u32 mcr_cur, mcr_new; 2982 2983 switch (port) { 2984 case 0 ... 4: /* Internal phy */ 2985 if (state->interface != PHY_INTERFACE_MODE_GMII && 2986 state->interface != PHY_INTERFACE_MODE_INTERNAL) 2987 goto unsupported; 2988 break; 2989 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2990 if (priv->p5_interface == state->interface) 2991 break; 2992 2993 if (mt753x_mac_config(ds, port, mode, state) < 0) 2994 goto unsupported; 2995 2996 if (priv->p5_intf_sel != P5_DISABLED) 2997 priv->p5_interface = state->interface; 2998 break; 2999 case 6: /* 1st cpu port */ 3000 if (priv->p6_interface == state->interface) 3001 break; 3002 3003 mt753x_pad_setup(ds, state); 3004 3005 if (mt753x_mac_config(ds, port, mode, state) < 0) 3006 goto unsupported; 3007 3008 priv->p6_interface = state->interface; 3009 break; 3010 default: 3011 unsupported: 3012 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 3013 __func__, phy_modes(state->interface), port); 3014 return; 3015 } 3016 3017 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 3018 mcr_new = mcr_cur; 3019 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 3020 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 3021 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 3022 3023 /* Are we connected to external phy */ 3024 if (port == 5 && dsa_is_user_port(ds, 5)) 3025 mcr_new |= PMCR_EXT_PHY; 3026 3027 if (mcr_new != mcr_cur) 3028 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 3029 } 3030 mt753x_phylink_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)3031 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 3032 unsigned int mode, 3033 phy_interface_t interface) 3034 { 3035 struct mt7530_priv *priv = ds->priv; 3036 3037 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 3038 } 3039 mt753x_phylink_pcs_link_up(struct phylink_pcs * pcs,unsigned int mode,phy_interface_t interface,int speed,int duplex)3040 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, 3041 unsigned int mode, 3042 phy_interface_t interface, 3043 int speed, int duplex) 3044 { 3045 if (pcs->ops->pcs_link_up) 3046 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); 3047 } 3048 mt753x_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)3049 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 3050 unsigned int mode, 3051 phy_interface_t interface, 3052 struct phy_device *phydev, 3053 int speed, int duplex, 3054 bool tx_pause, bool rx_pause) 3055 { 3056 struct mt7530_priv *priv = ds->priv; 3057 u32 mcr; 3058 3059 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 3060 3061 /* MT753x MAC works in 1G full duplex mode for all up-clocked 3062 * variants. 3063 */ 3064 if (interface == PHY_INTERFACE_MODE_TRGMII || 3065 (phy_interface_mode_is_8023z(interface))) { 3066 speed = SPEED_1000; 3067 duplex = DUPLEX_FULL; 3068 } 3069 3070 switch (speed) { 3071 case SPEED_1000: 3072 mcr |= PMCR_FORCE_SPEED_1000; 3073 break; 3074 case SPEED_100: 3075 mcr |= PMCR_FORCE_SPEED_100; 3076 break; 3077 } 3078 if (duplex == DUPLEX_FULL) { 3079 mcr |= PMCR_FORCE_FDX; 3080 if (tx_pause) 3081 mcr |= PMCR_TX_FC_EN; 3082 if (rx_pause) 3083 mcr |= PMCR_RX_FC_EN; 3084 } 3085 3086 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 3087 switch (speed) { 3088 case SPEED_1000: 3089 mcr |= PMCR_FORCE_EEE1G; 3090 break; 3091 case SPEED_100: 3092 mcr |= PMCR_FORCE_EEE100; 3093 break; 3094 } 3095 } 3096 3097 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 3098 } 3099 3100 static int mt7531_cpu_port_config(struct dsa_switch * ds,int port)3101 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 3102 { 3103 struct mt7530_priv *priv = ds->priv; 3104 phy_interface_t interface; 3105 int speed; 3106 int ret; 3107 3108 switch (port) { 3109 case 5: 3110 if (mt7531_is_rgmii_port(priv, port)) 3111 interface = PHY_INTERFACE_MODE_RGMII; 3112 else 3113 interface = PHY_INTERFACE_MODE_2500BASEX; 3114 3115 priv->p5_interface = interface; 3116 break; 3117 case 6: 3118 interface = PHY_INTERFACE_MODE_2500BASEX; 3119 3120 priv->p6_interface = interface; 3121 break; 3122 default: 3123 return -EINVAL; 3124 } 3125 3126 if (interface == PHY_INTERFACE_MODE_2500BASEX) 3127 speed = SPEED_2500; 3128 else 3129 speed = SPEED_1000; 3130 3131 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 3132 if (ret) 3133 return ret; 3134 mt7530_write(priv, MT7530_PMCR_P(port), 3135 PMCR_CPU_PORT_SETTING(priv->id)); 3136 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, 3137 interface, speed, DUPLEX_FULL); 3138 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 3139 speed, DUPLEX_FULL, true, true); 3140 3141 return 0; 3142 } 3143 3144 static int mt7988_cpu_port_config(struct dsa_switch * ds,int port)3145 mt7988_cpu_port_config(struct dsa_switch *ds, int port) 3146 { 3147 struct mt7530_priv *priv = ds->priv; 3148 3149 mt7530_write(priv, MT7530_PMCR_P(port), 3150 PMCR_CPU_PORT_SETTING(priv->id)); 3151 3152 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, 3153 PHY_INTERFACE_MODE_INTERNAL, NULL, 3154 SPEED_10000, DUPLEX_FULL, true, true); 3155 3156 return 0; 3157 } 3158 mt753x_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)3159 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 3160 struct phylink_config *config) 3161 { 3162 struct mt7530_priv *priv = ds->priv; 3163 3164 /* This switch only supports full-duplex at 1Gbps */ 3165 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 3166 MAC_10 | MAC_100 | MAC_1000FD; 3167 3168 priv->info->mac_port_get_caps(ds, port, config); 3169 } 3170 mt753x_pcs_validate(struct phylink_pcs * pcs,unsigned long * supported,const struct phylink_link_state * state)3171 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 3172 unsigned long *supported, 3173 const struct phylink_link_state *state) 3174 { 3175 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 3176 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 3177 phy_interface_mode_is_8023z(state->interface)) 3178 phylink_clear(supported, Autoneg); 3179 3180 return 0; 3181 } 3182 mt7530_pcs_get_state(struct phylink_pcs * pcs,struct phylink_link_state * state)3183 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 3184 struct phylink_link_state *state) 3185 { 3186 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3187 int port = pcs_to_mt753x_pcs(pcs)->port; 3188 u32 pmsr; 3189 3190 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 3191 3192 state->link = (pmsr & PMSR_LINK); 3193 state->an_complete = state->link; 3194 state->duplex = !!(pmsr & PMSR_DPX); 3195 3196 switch (pmsr & PMSR_SPEED_MASK) { 3197 case PMSR_SPEED_10: 3198 state->speed = SPEED_10; 3199 break; 3200 case PMSR_SPEED_100: 3201 state->speed = SPEED_100; 3202 break; 3203 case PMSR_SPEED_1000: 3204 state->speed = SPEED_1000; 3205 break; 3206 default: 3207 state->speed = SPEED_UNKNOWN; 3208 break; 3209 } 3210 3211 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 3212 if (pmsr & PMSR_RX_FC) 3213 state->pause |= MLO_PAUSE_RX; 3214 if (pmsr & PMSR_TX_FC) 3215 state->pause |= MLO_PAUSE_TX; 3216 } 3217 mt753x_pcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)3218 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 3219 phy_interface_t interface, 3220 const unsigned long *advertising, 3221 bool permit_pause_to_mac) 3222 { 3223 return 0; 3224 } 3225 mt7530_pcs_an_restart(struct phylink_pcs * pcs)3226 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3227 { 3228 } 3229 3230 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3231 .pcs_validate = mt753x_pcs_validate, 3232 .pcs_get_state = mt7530_pcs_get_state, 3233 .pcs_config = mt753x_pcs_config, 3234 .pcs_an_restart = mt7530_pcs_an_restart, 3235 }; 3236 3237 static int mt753x_setup(struct dsa_switch * ds)3238 mt753x_setup(struct dsa_switch *ds) 3239 { 3240 struct mt7530_priv *priv = ds->priv; 3241 int i, ret; 3242 3243 /* Initialise the PCS devices */ 3244 for (i = 0; i < priv->ds->num_ports; i++) { 3245 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3246 priv->pcs[i].pcs.neg_mode = true; 3247 priv->pcs[i].priv = priv; 3248 priv->pcs[i].port = i; 3249 } 3250 3251 ret = priv->info->sw_setup(ds); 3252 if (ret) 3253 return ret; 3254 3255 ret = mt7530_setup_irq(priv); 3256 if (ret) 3257 return ret; 3258 3259 ret = mt7530_setup_mdio(priv); 3260 if (ret && priv->irq) 3261 mt7530_free_irq_common(priv); 3262 3263 if (priv->create_sgmii) { 3264 ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); 3265 if (ret && priv->irq) 3266 mt7530_free_irq(priv); 3267 } 3268 3269 return ret; 3270 } 3271 mt753x_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)3272 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3273 struct ethtool_eee *e) 3274 { 3275 struct mt7530_priv *priv = ds->priv; 3276 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3277 3278 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3279 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3280 3281 return 0; 3282 } 3283 mt753x_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)3284 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3285 struct ethtool_eee *e) 3286 { 3287 struct mt7530_priv *priv = ds->priv; 3288 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3289 3290 if (e->tx_lpi_timer > 0xFFF) 3291 return -EINVAL; 3292 3293 set = SET_LPI_THRESH(e->tx_lpi_timer); 3294 if (!e->tx_lpi_enabled) 3295 /* Force LPI Mode without a delay */ 3296 set |= LPI_MODE_EN; 3297 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3298 3299 return 0; 3300 } 3301 mt7988_pad_setup(struct dsa_switch * ds,phy_interface_t interface)3302 static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 3303 { 3304 return 0; 3305 } 3306 mt7988_setup(struct dsa_switch * ds)3307 static int mt7988_setup(struct dsa_switch *ds) 3308 { 3309 struct mt7530_priv *priv = ds->priv; 3310 3311 /* Reset the switch */ 3312 reset_control_assert(priv->rstc); 3313 usleep_range(20, 50); 3314 reset_control_deassert(priv->rstc); 3315 usleep_range(20, 50); 3316 3317 /* Reset the switch PHYs */ 3318 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3319 3320 return mt7531_setup_common(ds); 3321 } 3322 3323 const struct dsa_switch_ops mt7530_switch_ops = { 3324 .get_tag_protocol = mtk_get_tag_protocol, 3325 .setup = mt753x_setup, 3326 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3327 .get_strings = mt7530_get_strings, 3328 .get_ethtool_stats = mt7530_get_ethtool_stats, 3329 .get_sset_count = mt7530_get_sset_count, 3330 .set_ageing_time = mt7530_set_ageing_time, 3331 .port_enable = mt7530_port_enable, 3332 .port_disable = mt7530_port_disable, 3333 .port_change_mtu = mt7530_port_change_mtu, 3334 .port_max_mtu = mt7530_port_max_mtu, 3335 .port_stp_state_set = mt7530_stp_state_set, 3336 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3337 .port_bridge_flags = mt7530_port_bridge_flags, 3338 .port_bridge_join = mt7530_port_bridge_join, 3339 .port_bridge_leave = mt7530_port_bridge_leave, 3340 .port_fdb_add = mt7530_port_fdb_add, 3341 .port_fdb_del = mt7530_port_fdb_del, 3342 .port_fdb_dump = mt7530_port_fdb_dump, 3343 .port_mdb_add = mt7530_port_mdb_add, 3344 .port_mdb_del = mt7530_port_mdb_del, 3345 .port_vlan_filtering = mt7530_port_vlan_filtering, 3346 .port_vlan_add = mt7530_port_vlan_add, 3347 .port_vlan_del = mt7530_port_vlan_del, 3348 .port_mirror_add = mt753x_port_mirror_add, 3349 .port_mirror_del = mt753x_port_mirror_del, 3350 .phylink_get_caps = mt753x_phylink_get_caps, 3351 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3352 .phylink_mac_config = mt753x_phylink_mac_config, 3353 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3354 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3355 .get_mac_eee = mt753x_get_mac_eee, 3356 .set_mac_eee = mt753x_set_mac_eee, 3357 }; 3358 EXPORT_SYMBOL_GPL(mt7530_switch_ops); 3359 3360 const struct mt753x_info mt753x_table[] = { 3361 [ID_MT7621] = { 3362 .id = ID_MT7621, 3363 .pcs_ops = &mt7530_pcs_ops, 3364 .sw_setup = mt7530_setup, 3365 .phy_read_c22 = mt7530_phy_read_c22, 3366 .phy_write_c22 = mt7530_phy_write_c22, 3367 .phy_read_c45 = mt7530_phy_read_c45, 3368 .phy_write_c45 = mt7530_phy_write_c45, 3369 .pad_setup = mt7530_pad_clk_setup, 3370 .mac_port_get_caps = mt7530_mac_port_get_caps, 3371 .mac_port_config = mt7530_mac_config, 3372 }, 3373 [ID_MT7530] = { 3374 .id = ID_MT7530, 3375 .pcs_ops = &mt7530_pcs_ops, 3376 .sw_setup = mt7530_setup, 3377 .phy_read_c22 = mt7530_phy_read_c22, 3378 .phy_write_c22 = mt7530_phy_write_c22, 3379 .phy_read_c45 = mt7530_phy_read_c45, 3380 .phy_write_c45 = mt7530_phy_write_c45, 3381 .pad_setup = mt7530_pad_clk_setup, 3382 .mac_port_get_caps = mt7530_mac_port_get_caps, 3383 .mac_port_config = mt7530_mac_config, 3384 }, 3385 [ID_MT7531] = { 3386 .id = ID_MT7531, 3387 .pcs_ops = &mt7530_pcs_ops, 3388 .sw_setup = mt7531_setup, 3389 .phy_read_c22 = mt7531_ind_c22_phy_read, 3390 .phy_write_c22 = mt7531_ind_c22_phy_write, 3391 .phy_read_c45 = mt7531_ind_c45_phy_read, 3392 .phy_write_c45 = mt7531_ind_c45_phy_write, 3393 .pad_setup = mt7531_pad_setup, 3394 .cpu_port_config = mt7531_cpu_port_config, 3395 .mac_port_get_caps = mt7531_mac_port_get_caps, 3396 .mac_port_config = mt7531_mac_config, 3397 }, 3398 [ID_MT7988] = { 3399 .id = ID_MT7988, 3400 .pcs_ops = &mt7530_pcs_ops, 3401 .sw_setup = mt7988_setup, 3402 .phy_read_c22 = mt7531_ind_c22_phy_read, 3403 .phy_write_c22 = mt7531_ind_c22_phy_write, 3404 .phy_read_c45 = mt7531_ind_c45_phy_read, 3405 .phy_write_c45 = mt7531_ind_c45_phy_write, 3406 .pad_setup = mt7988_pad_setup, 3407 .cpu_port_config = mt7988_cpu_port_config, 3408 .mac_port_get_caps = mt7988_mac_port_get_caps, 3409 .mac_port_config = mt7988_mac_config, 3410 }, 3411 }; 3412 EXPORT_SYMBOL_GPL(mt753x_table); 3413 3414 int mt7530_probe_common(struct mt7530_priv * priv)3415 mt7530_probe_common(struct mt7530_priv *priv) 3416 { 3417 struct device *dev = priv->dev; 3418 3419 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3420 if (!priv->ds) 3421 return -ENOMEM; 3422 3423 priv->ds->dev = dev; 3424 priv->ds->num_ports = MT7530_NUM_PORTS; 3425 3426 /* Get the hardware identifier from the devicetree node. 3427 * We will need it for some of the clock and regulator setup. 3428 */ 3429 priv->info = of_device_get_match_data(dev); 3430 if (!priv->info) 3431 return -EINVAL; 3432 3433 /* Sanity check if these required device operations are filled 3434 * properly. 3435 */ 3436 if (!priv->info->sw_setup || !priv->info->pad_setup || 3437 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || 3438 !priv->info->mac_port_get_caps || 3439 !priv->info->mac_port_config) 3440 return -EINVAL; 3441 3442 priv->id = priv->info->id; 3443 priv->dev = dev; 3444 priv->ds->priv = priv; 3445 priv->ds->ops = &mt7530_switch_ops; 3446 mutex_init(&priv->reg_mutex); 3447 dev_set_drvdata(dev, priv); 3448 3449 return 0; 3450 } 3451 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3452 3453 void mt7530_remove_common(struct mt7530_priv * priv)3454 mt7530_remove_common(struct mt7530_priv *priv) 3455 { 3456 if (priv->irq) 3457 mt7530_free_irq(priv); 3458 3459 dsa_unregister_switch(priv->ds); 3460 3461 mutex_destroy(&priv->reg_mutex); 3462 } 3463 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3464 3465 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3466 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3467 MODULE_LICENSE("GPL"); 3468