xref: /openbmc/linux/include/linux/mlx5/mlx5_ifc.h (revision 769218209d8f00a4003dc9ee351198a473043eaf)
1  /*
2   * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3   *
4   * This software is available to you under a choice of one of two
5   * licenses.  You may choose to be licensed under the terms of the GNU
6   * General Public License (GPL) Version 2, available from the file
7   * COPYING in the main directory of this source tree, or the
8   * OpenIB.org BSD license below:
9   *
10   *     Redistribution and use in source and binary forms, with or
11   *     without modification, are permitted provided that the following
12   *     conditions are met:
13   *
14   *      - Redistributions of source code must retain the above
15   *        copyright notice, this list of conditions and the following
16   *        disclaimer.
17   *
18   *      - Redistributions in binary form must reproduce the above
19   *        copyright notice, this list of conditions and the following
20   *        disclaimer in the documentation and/or other materials
21   *        provided with the distribution.
22   *
23   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24   * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25   * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26   * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27   * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28   * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29   * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30   * SOFTWARE.
31  */
32  #ifndef MLX5_IFC_H
33  #define MLX5_IFC_H
34  
35  #include "mlx5_ifc_fpga.h"
36  
37  enum {
38  	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39  	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40  	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41  	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42  	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43  	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44  	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45  	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46  	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47  	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48  	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49  	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50  	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51  	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52  	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53  	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54  	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55  	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56  	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57  	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58  	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59  	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60  	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61  	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62  	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63  	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64  };
65  
66  enum {
67  	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
68  	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
69  	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
70  	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
71  	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
72  	MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
73  	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
74  	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
75  };
76  
77  enum {
78  	MLX5_SHARED_RESOURCE_UID = 0xffff,
79  };
80  
81  enum {
82  	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83  	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
84  };
85  
86  enum {
87  	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
88  	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
89  	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
90  	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
91  		(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
92  	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
93  };
94  
95  enum {
96  	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
97  	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
98  	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
99  	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
100  	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
101  	MLX5_OBJ_TYPE_MKEY = 0xff01,
102  	MLX5_OBJ_TYPE_QP = 0xff02,
103  	MLX5_OBJ_TYPE_PSV = 0xff03,
104  	MLX5_OBJ_TYPE_RMP = 0xff04,
105  	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
106  	MLX5_OBJ_TYPE_RQ = 0xff06,
107  	MLX5_OBJ_TYPE_SQ = 0xff07,
108  	MLX5_OBJ_TYPE_TIR = 0xff08,
109  	MLX5_OBJ_TYPE_TIS = 0xff09,
110  	MLX5_OBJ_TYPE_DCT = 0xff0a,
111  	MLX5_OBJ_TYPE_XRQ = 0xff0b,
112  	MLX5_OBJ_TYPE_RQT = 0xff0e,
113  	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
114  	MLX5_OBJ_TYPE_CQ = 0xff10,
115  };
116  
117  enum {
118  	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
119  	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
120  	MLX5_CMD_OP_INIT_HCA                      = 0x102,
121  	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
122  	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
123  	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
124  	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
125  	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
126  	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
127  	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
128  	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
129  	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
130  	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
131  	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
132  	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
133  	MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
134  	MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
135  	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
136  	MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
137  	MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
138  	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
139  	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
140  	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
141  	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
142  	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
143  	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
144  	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
145  	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
146  	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
147  	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
148  	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
149  	MLX5_CMD_OP_GEN_EQE                       = 0x304,
150  	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
151  	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
152  	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
153  	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
154  	MLX5_CMD_OP_CREATE_QP                     = 0x500,
155  	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
156  	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
157  	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
158  	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
159  	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
160  	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
161  	MLX5_CMD_OP_2ERR_QP                       = 0x507,
162  	MLX5_CMD_OP_2RST_QP                       = 0x50a,
163  	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
164  	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
165  	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
166  	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
167  	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
168  	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
169  	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
170  	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
171  	MLX5_CMD_OP_ARM_RQ                        = 0x703,
172  	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
173  	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
174  	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
175  	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
176  	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
177  	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
178  	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
179  	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
180  	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
181  	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
182  	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
183  	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
184  	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
185  	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
186  	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
187  	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
188  	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
189  	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
190  	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
191  	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
192  	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
193  	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
194  	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
195  	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
196  	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
197  	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
198  	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
199  	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
200  	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
201  	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
202  	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
203  	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
204  	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
205  	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
206  	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
207  	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
208  	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
209  	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
210  	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
211  	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
212  	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
213  	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
214  	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
215  	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
216  	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
217  	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
218  	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
219  	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
220  	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
221  	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
222  	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
223  	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
224  	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
225  	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
226  	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
227  	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
228  	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
229  	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
230  	MLX5_CMD_OP_NOP                           = 0x80d,
231  	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
232  	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
233  	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
234  	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
235  	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
236  	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
237  	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
238  	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
239  	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
240  	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
241  	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
242  	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
243  	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
244  	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
245  	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
246  	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
247  	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
248  	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
249  	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
250  	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
251  	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
252  	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
253  	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
254  	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
255  	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
256  	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
257  	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
258  	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
259  	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
260  	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
261  	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
262  	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
263  	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
264  	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
265  	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
266  	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
267  	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
268  	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
269  	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
270  	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
271  	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
272  	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
273  	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
274  	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
275  	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
276  	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
277  	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
278  	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
279  	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
280  	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
281  	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
282  	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
283  	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
284  	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
285  	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
286  	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
287  	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
288  	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
289  	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
290  	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
291  	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
292  	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
293  	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
294  	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
295  	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
296  	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
297  	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
298  	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
299  	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
300  	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
301  	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
302  	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
303  	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
304  	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
305  	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
306  	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
307  	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
308  	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
309  	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
310  	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
311  	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
312  	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
313  	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
314  	MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
315  	MLX5_CMD_OP_MAX
316  };
317  
318  /* Valid range for general commands that don't work over an object */
319  enum {
320  	MLX5_CMD_OP_GENERAL_START = 0xb00,
321  	MLX5_CMD_OP_GENERAL_END = 0xd00,
322  };
323  
324  enum {
325  	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
326  	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
327  };
328  
329  enum {
330  	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
331  };
332  
333  struct mlx5_ifc_flow_table_fields_supported_bits {
334  	u8         outer_dmac[0x1];
335  	u8         outer_smac[0x1];
336  	u8         outer_ether_type[0x1];
337  	u8         outer_ip_version[0x1];
338  	u8         outer_first_prio[0x1];
339  	u8         outer_first_cfi[0x1];
340  	u8         outer_first_vid[0x1];
341  	u8         outer_ipv4_ttl[0x1];
342  	u8         outer_second_prio[0x1];
343  	u8         outer_second_cfi[0x1];
344  	u8         outer_second_vid[0x1];
345  	u8         reserved_at_b[0x1];
346  	u8         outer_sip[0x1];
347  	u8         outer_dip[0x1];
348  	u8         outer_frag[0x1];
349  	u8         outer_ip_protocol[0x1];
350  	u8         outer_ip_ecn[0x1];
351  	u8         outer_ip_dscp[0x1];
352  	u8         outer_udp_sport[0x1];
353  	u8         outer_udp_dport[0x1];
354  	u8         outer_tcp_sport[0x1];
355  	u8         outer_tcp_dport[0x1];
356  	u8         outer_tcp_flags[0x1];
357  	u8         outer_gre_protocol[0x1];
358  	u8         outer_gre_key[0x1];
359  	u8         outer_vxlan_vni[0x1];
360  	u8         outer_geneve_vni[0x1];
361  	u8         outer_geneve_oam[0x1];
362  	u8         outer_geneve_protocol_type[0x1];
363  	u8         outer_geneve_opt_len[0x1];
364  	u8         source_vhca_port[0x1];
365  	u8         source_eswitch_port[0x1];
366  
367  	u8         inner_dmac[0x1];
368  	u8         inner_smac[0x1];
369  	u8         inner_ether_type[0x1];
370  	u8         inner_ip_version[0x1];
371  	u8         inner_first_prio[0x1];
372  	u8         inner_first_cfi[0x1];
373  	u8         inner_first_vid[0x1];
374  	u8         reserved_at_27[0x1];
375  	u8         inner_second_prio[0x1];
376  	u8         inner_second_cfi[0x1];
377  	u8         inner_second_vid[0x1];
378  	u8         reserved_at_2b[0x1];
379  	u8         inner_sip[0x1];
380  	u8         inner_dip[0x1];
381  	u8         inner_frag[0x1];
382  	u8         inner_ip_protocol[0x1];
383  	u8         inner_ip_ecn[0x1];
384  	u8         inner_ip_dscp[0x1];
385  	u8         inner_udp_sport[0x1];
386  	u8         inner_udp_dport[0x1];
387  	u8         inner_tcp_sport[0x1];
388  	u8         inner_tcp_dport[0x1];
389  	u8         inner_tcp_flags[0x1];
390  	u8         reserved_at_37[0x9];
391  
392  	u8         geneve_tlv_option_0_data[0x1];
393  	u8         geneve_tlv_option_0_exist[0x1];
394  	u8         reserved_at_42[0x3];
395  	u8         outer_first_mpls_over_udp[0x4];
396  	u8         outer_first_mpls_over_gre[0x4];
397  	u8         inner_first_mpls[0x4];
398  	u8         outer_first_mpls[0x4];
399  	u8         reserved_at_55[0x2];
400  	u8	   outer_esp_spi[0x1];
401  	u8         reserved_at_58[0x2];
402  	u8         bth_dst_qp[0x1];
403  	u8         reserved_at_5b[0x5];
404  
405  	u8         reserved_at_60[0x18];
406  	u8         metadata_reg_c_7[0x1];
407  	u8         metadata_reg_c_6[0x1];
408  	u8         metadata_reg_c_5[0x1];
409  	u8         metadata_reg_c_4[0x1];
410  	u8         metadata_reg_c_3[0x1];
411  	u8         metadata_reg_c_2[0x1];
412  	u8         metadata_reg_c_1[0x1];
413  	u8         metadata_reg_c_0[0x1];
414  };
415  
416  /* Table 2170 - Flow Table Fields Supported 2 Format */
417  struct mlx5_ifc_flow_table_fields_supported_2_bits {
418  	u8         reserved_at_0[0xe];
419  	u8         bth_opcode[0x1];
420  	u8         reserved_at_f[0x1];
421  	u8         tunnel_header_0_1[0x1];
422  	u8         reserved_at_11[0xf];
423  
424  	u8         reserved_at_20[0x60];
425  };
426  
427  struct mlx5_ifc_flow_table_prop_layout_bits {
428  	u8         ft_support[0x1];
429  	u8         reserved_at_1[0x1];
430  	u8         flow_counter[0x1];
431  	u8	   flow_modify_en[0x1];
432  	u8         modify_root[0x1];
433  	u8         identified_miss_table_mode[0x1];
434  	u8         flow_table_modify[0x1];
435  	u8         reformat[0x1];
436  	u8         decap[0x1];
437  	u8         reserved_at_9[0x1];
438  	u8         pop_vlan[0x1];
439  	u8         push_vlan[0x1];
440  	u8         reserved_at_c[0x1];
441  	u8         pop_vlan_2[0x1];
442  	u8         push_vlan_2[0x1];
443  	u8	   reformat_and_vlan_action[0x1];
444  	u8	   reserved_at_10[0x1];
445  	u8         sw_owner[0x1];
446  	u8	   reformat_l3_tunnel_to_l2[0x1];
447  	u8	   reformat_l2_to_l3_tunnel[0x1];
448  	u8	   reformat_and_modify_action[0x1];
449  	u8	   ignore_flow_level[0x1];
450  	u8         reserved_at_16[0x1];
451  	u8	   table_miss_action_domain[0x1];
452  	u8         termination_table[0x1];
453  	u8         reformat_and_fwd_to_table[0x1];
454  	u8         reserved_at_1a[0x2];
455  	u8         ipsec_encrypt[0x1];
456  	u8         ipsec_decrypt[0x1];
457  	u8         sw_owner_v2[0x1];
458  	u8         reserved_at_1f[0x1];
459  
460  	u8         termination_table_raw_traffic[0x1];
461  	u8         reserved_at_21[0x1];
462  	u8         log_max_ft_size[0x6];
463  	u8         log_max_modify_header_context[0x8];
464  	u8         max_modify_header_actions[0x8];
465  	u8         max_ft_level[0x8];
466  
467  	u8         reformat_add_esp_trasport[0x1];
468  	u8         reformat_l2_to_l3_esp_tunnel[0x1];
469  	u8         reformat_add_esp_transport_over_udp[0x1];
470  	u8         reformat_del_esp_trasport[0x1];
471  	u8         reformat_l3_esp_tunnel_to_l2[0x1];
472  	u8         reformat_del_esp_transport_over_udp[0x1];
473  	u8         execute_aso[0x1];
474  	u8         reserved_at_47[0x19];
475  
476  	u8         reserved_at_60[0x2];
477  	u8         reformat_insert[0x1];
478  	u8         reformat_remove[0x1];
479  	u8         macsec_encrypt[0x1];
480  	u8         macsec_decrypt[0x1];
481  	u8         reserved_at_66[0x2];
482  	u8         reformat_add_macsec[0x1];
483  	u8         reformat_remove_macsec[0x1];
484  	u8         reserved_at_6a[0xe];
485  	u8         log_max_ft_num[0x8];
486  
487  	u8         reserved_at_80[0x10];
488  	u8         log_max_flow_counter[0x8];
489  	u8         log_max_destination[0x8];
490  
491  	u8         reserved_at_a0[0x18];
492  	u8         log_max_flow[0x8];
493  
494  	u8         reserved_at_c0[0x40];
495  
496  	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
497  
498  	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
499  };
500  
501  struct mlx5_ifc_odp_per_transport_service_cap_bits {
502  	u8         send[0x1];
503  	u8         receive[0x1];
504  	u8         write[0x1];
505  	u8         read[0x1];
506  	u8         atomic[0x1];
507  	u8         srq_receive[0x1];
508  	u8         reserved_at_6[0x1a];
509  };
510  
511  struct mlx5_ifc_ipv4_layout_bits {
512  	u8         reserved_at_0[0x60];
513  
514  	u8         ipv4[0x20];
515  };
516  
517  struct mlx5_ifc_ipv6_layout_bits {
518  	u8         ipv6[16][0x8];
519  };
520  
521  union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
522  	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
523  	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
524  	u8         reserved_at_0[0x80];
525  };
526  
527  struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
528  	u8         smac_47_16[0x20];
529  
530  	u8         smac_15_0[0x10];
531  	u8         ethertype[0x10];
532  
533  	u8         dmac_47_16[0x20];
534  
535  	u8         dmac_15_0[0x10];
536  	u8         first_prio[0x3];
537  	u8         first_cfi[0x1];
538  	u8         first_vid[0xc];
539  
540  	u8         ip_protocol[0x8];
541  	u8         ip_dscp[0x6];
542  	u8         ip_ecn[0x2];
543  	u8         cvlan_tag[0x1];
544  	u8         svlan_tag[0x1];
545  	u8         frag[0x1];
546  	u8         ip_version[0x4];
547  	u8         tcp_flags[0x9];
548  
549  	u8         tcp_sport[0x10];
550  	u8         tcp_dport[0x10];
551  
552  	u8         reserved_at_c0[0x10];
553  	u8         ipv4_ihl[0x4];
554  	u8         reserved_at_c4[0x4];
555  
556  	u8         ttl_hoplimit[0x8];
557  
558  	u8         udp_sport[0x10];
559  	u8         udp_dport[0x10];
560  
561  	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
562  
563  	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
564  };
565  
566  struct mlx5_ifc_nvgre_key_bits {
567  	u8 hi[0x18];
568  	u8 lo[0x8];
569  };
570  
571  union mlx5_ifc_gre_key_bits {
572  	struct mlx5_ifc_nvgre_key_bits nvgre;
573  	u8 key[0x20];
574  };
575  
576  struct mlx5_ifc_fte_match_set_misc_bits {
577  	u8         gre_c_present[0x1];
578  	u8         reserved_at_1[0x1];
579  	u8         gre_k_present[0x1];
580  	u8         gre_s_present[0x1];
581  	u8         source_vhca_port[0x4];
582  	u8         source_sqn[0x18];
583  
584  	u8         source_eswitch_owner_vhca_id[0x10];
585  	u8         source_port[0x10];
586  
587  	u8         outer_second_prio[0x3];
588  	u8         outer_second_cfi[0x1];
589  	u8         outer_second_vid[0xc];
590  	u8         inner_second_prio[0x3];
591  	u8         inner_second_cfi[0x1];
592  	u8         inner_second_vid[0xc];
593  
594  	u8         outer_second_cvlan_tag[0x1];
595  	u8         inner_second_cvlan_tag[0x1];
596  	u8         outer_second_svlan_tag[0x1];
597  	u8         inner_second_svlan_tag[0x1];
598  	u8         reserved_at_64[0xc];
599  	u8         gre_protocol[0x10];
600  
601  	union mlx5_ifc_gre_key_bits gre_key;
602  
603  	u8         vxlan_vni[0x18];
604  	u8         bth_opcode[0x8];
605  
606  	u8         geneve_vni[0x18];
607  	u8         reserved_at_d8[0x6];
608  	u8         geneve_tlv_option_0_exist[0x1];
609  	u8         geneve_oam[0x1];
610  
611  	u8         reserved_at_e0[0xc];
612  	u8         outer_ipv6_flow_label[0x14];
613  
614  	u8         reserved_at_100[0xc];
615  	u8         inner_ipv6_flow_label[0x14];
616  
617  	u8         reserved_at_120[0xa];
618  	u8         geneve_opt_len[0x6];
619  	u8         geneve_protocol_type[0x10];
620  
621  	u8         reserved_at_140[0x8];
622  	u8         bth_dst_qp[0x18];
623  	u8	   inner_esp_spi[0x20];
624  	u8	   outer_esp_spi[0x20];
625  	u8         reserved_at_1a0[0x60];
626  };
627  
628  struct mlx5_ifc_fte_match_mpls_bits {
629  	u8         mpls_label[0x14];
630  	u8         mpls_exp[0x3];
631  	u8         mpls_s_bos[0x1];
632  	u8         mpls_ttl[0x8];
633  };
634  
635  struct mlx5_ifc_fte_match_set_misc2_bits {
636  	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
637  
638  	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
639  
640  	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
641  
642  	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
643  
644  	u8         metadata_reg_c_7[0x20];
645  
646  	u8         metadata_reg_c_6[0x20];
647  
648  	u8         metadata_reg_c_5[0x20];
649  
650  	u8         metadata_reg_c_4[0x20];
651  
652  	u8         metadata_reg_c_3[0x20];
653  
654  	u8         metadata_reg_c_2[0x20];
655  
656  	u8         metadata_reg_c_1[0x20];
657  
658  	u8         metadata_reg_c_0[0x20];
659  
660  	u8         metadata_reg_a[0x20];
661  
662  	u8         reserved_at_1a0[0x8];
663  
664  	u8         macsec_syndrome[0x8];
665  	u8         ipsec_syndrome[0x8];
666  	u8         reserved_at_1b8[0x8];
667  
668  	u8         reserved_at_1c0[0x40];
669  };
670  
671  struct mlx5_ifc_fte_match_set_misc3_bits {
672  	u8         inner_tcp_seq_num[0x20];
673  
674  	u8         outer_tcp_seq_num[0x20];
675  
676  	u8         inner_tcp_ack_num[0x20];
677  
678  	u8         outer_tcp_ack_num[0x20];
679  
680  	u8	   reserved_at_80[0x8];
681  	u8         outer_vxlan_gpe_vni[0x18];
682  
683  	u8         outer_vxlan_gpe_next_protocol[0x8];
684  	u8         outer_vxlan_gpe_flags[0x8];
685  	u8	   reserved_at_b0[0x10];
686  
687  	u8	   icmp_header_data[0x20];
688  
689  	u8	   icmpv6_header_data[0x20];
690  
691  	u8	   icmp_type[0x8];
692  	u8	   icmp_code[0x8];
693  	u8	   icmpv6_type[0x8];
694  	u8	   icmpv6_code[0x8];
695  
696  	u8         geneve_tlv_option_0_data[0x20];
697  
698  	u8	   gtpu_teid[0x20];
699  
700  	u8	   gtpu_msg_type[0x8];
701  	u8	   gtpu_msg_flags[0x8];
702  	u8	   reserved_at_170[0x10];
703  
704  	u8	   gtpu_dw_2[0x20];
705  
706  	u8	   gtpu_first_ext_dw_0[0x20];
707  
708  	u8	   gtpu_dw_0[0x20];
709  
710  	u8	   reserved_at_1e0[0x20];
711  };
712  
713  struct mlx5_ifc_fte_match_set_misc4_bits {
714  	u8         prog_sample_field_value_0[0x20];
715  
716  	u8         prog_sample_field_id_0[0x20];
717  
718  	u8         prog_sample_field_value_1[0x20];
719  
720  	u8         prog_sample_field_id_1[0x20];
721  
722  	u8         prog_sample_field_value_2[0x20];
723  
724  	u8         prog_sample_field_id_2[0x20];
725  
726  	u8         prog_sample_field_value_3[0x20];
727  
728  	u8         prog_sample_field_id_3[0x20];
729  
730  	u8         reserved_at_100[0x100];
731  };
732  
733  struct mlx5_ifc_fte_match_set_misc5_bits {
734  	u8         macsec_tag_0[0x20];
735  
736  	u8         macsec_tag_1[0x20];
737  
738  	u8         macsec_tag_2[0x20];
739  
740  	u8         macsec_tag_3[0x20];
741  
742  	u8         tunnel_header_0[0x20];
743  
744  	u8         tunnel_header_1[0x20];
745  
746  	u8         tunnel_header_2[0x20];
747  
748  	u8         tunnel_header_3[0x20];
749  
750  	u8         reserved_at_100[0x100];
751  };
752  
753  struct mlx5_ifc_cmd_pas_bits {
754  	u8         pa_h[0x20];
755  
756  	u8         pa_l[0x14];
757  	u8         reserved_at_34[0xc];
758  };
759  
760  struct mlx5_ifc_uint64_bits {
761  	u8         hi[0x20];
762  
763  	u8         lo[0x20];
764  };
765  
766  enum {
767  	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
768  	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
769  	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
770  	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
771  	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
772  	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
773  	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
774  	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
775  	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
776  	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
777  };
778  
779  struct mlx5_ifc_ads_bits {
780  	u8         fl[0x1];
781  	u8         free_ar[0x1];
782  	u8         reserved_at_2[0xe];
783  	u8         pkey_index[0x10];
784  
785  	u8         reserved_at_20[0x8];
786  	u8         grh[0x1];
787  	u8         mlid[0x7];
788  	u8         rlid[0x10];
789  
790  	u8         ack_timeout[0x5];
791  	u8         reserved_at_45[0x3];
792  	u8         src_addr_index[0x8];
793  	u8         reserved_at_50[0x4];
794  	u8         stat_rate[0x4];
795  	u8         hop_limit[0x8];
796  
797  	u8         reserved_at_60[0x4];
798  	u8         tclass[0x8];
799  	u8         flow_label[0x14];
800  
801  	u8         rgid_rip[16][0x8];
802  
803  	u8         reserved_at_100[0x4];
804  	u8         f_dscp[0x1];
805  	u8         f_ecn[0x1];
806  	u8         reserved_at_106[0x1];
807  	u8         f_eth_prio[0x1];
808  	u8         ecn[0x2];
809  	u8         dscp[0x6];
810  	u8         udp_sport[0x10];
811  
812  	u8         dei_cfi[0x1];
813  	u8         eth_prio[0x3];
814  	u8         sl[0x4];
815  	u8         vhca_port_num[0x8];
816  	u8         rmac_47_32[0x10];
817  
818  	u8         rmac_31_0[0x20];
819  };
820  
821  struct mlx5_ifc_flow_table_nic_cap_bits {
822  	u8         nic_rx_multi_path_tirs[0x1];
823  	u8         nic_rx_multi_path_tirs_fts[0x1];
824  	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
825  	u8	   reserved_at_3[0x4];
826  	u8	   sw_owner_reformat_supported[0x1];
827  	u8	   reserved_at_8[0x18];
828  
829  	u8	   encap_general_header[0x1];
830  	u8	   reserved_at_21[0xa];
831  	u8	   log_max_packet_reformat_context[0x5];
832  	u8	   reserved_at_30[0x6];
833  	u8	   max_encap_header_size[0xa];
834  	u8	   reserved_at_40[0x1c0];
835  
836  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
837  
838  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
839  
840  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
841  
842  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
843  
844  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
845  
846  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
847  
848  	u8         reserved_at_e00[0x700];
849  
850  	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
851  
852  	u8         reserved_at_1580[0x280];
853  
854  	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
855  
856  	u8         reserved_at_1880[0x780];
857  
858  	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
859  
860  	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
861  
862  	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
863  
864  	u8         reserved_at_20c0[0x5f40];
865  };
866  
867  struct mlx5_ifc_port_selection_cap_bits {
868  	u8         reserved_at_0[0x10];
869  	u8         port_select_flow_table[0x1];
870  	u8         reserved_at_11[0x1];
871  	u8         port_select_flow_table_bypass[0x1];
872  	u8         reserved_at_13[0xd];
873  
874  	u8         reserved_at_20[0x1e0];
875  
876  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
877  
878  	u8         reserved_at_400[0x7c00];
879  };
880  
881  enum {
882  	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
883  	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
884  	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
885  	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
886  	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
887  	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
888  	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
889  	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
890  };
891  
892  struct mlx5_ifc_flow_table_eswitch_cap_bits {
893  	u8      fdb_to_vport_reg_c_id[0x8];
894  	u8      reserved_at_8[0x5];
895  	u8      fdb_uplink_hairpin[0x1];
896  	u8      fdb_multi_path_any_table_limit_regc[0x1];
897  	u8      reserved_at_f[0x3];
898  	u8      fdb_multi_path_any_table[0x1];
899  	u8      reserved_at_13[0x2];
900  	u8      fdb_modify_header_fwd_to_table[0x1];
901  	u8      fdb_ipv4_ttl_modify[0x1];
902  	u8      flow_source[0x1];
903  	u8      reserved_at_18[0x2];
904  	u8      multi_fdb_encap[0x1];
905  	u8      egress_acl_forward_to_vport[0x1];
906  	u8      fdb_multi_path_to_table[0x1];
907  	u8      reserved_at_1d[0x3];
908  
909  	u8      reserved_at_20[0x1e0];
910  
911  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
912  
913  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
914  
915  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
916  
917  	u8      reserved_at_800[0xC00];
918  
919  	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
920  
921  	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
922  
923  	u8      reserved_at_1500[0x300];
924  
925  	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
926  
927  	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
928  
929  	u8      sw_steering_uplink_icm_address_rx[0x40];
930  
931  	u8      sw_steering_uplink_icm_address_tx[0x40];
932  
933  	u8      reserved_at_1900[0x6700];
934  };
935  
936  enum {
937  	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
938  	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
939  };
940  
941  struct mlx5_ifc_e_switch_cap_bits {
942  	u8         vport_svlan_strip[0x1];
943  	u8         vport_cvlan_strip[0x1];
944  	u8         vport_svlan_insert[0x1];
945  	u8         vport_cvlan_insert_if_not_exist[0x1];
946  	u8         vport_cvlan_insert_overwrite[0x1];
947  	u8         reserved_at_5[0x1];
948  	u8         vport_cvlan_insert_always[0x1];
949  	u8         esw_shared_ingress_acl[0x1];
950  	u8         esw_uplink_ingress_acl[0x1];
951  	u8         root_ft_on_other_esw[0x1];
952  	u8         reserved_at_a[0xf];
953  	u8         esw_functions_changed[0x1];
954  	u8         reserved_at_1a[0x1];
955  	u8         ecpf_vport_exists[0x1];
956  	u8         counter_eswitch_affinity[0x1];
957  	u8         merged_eswitch[0x1];
958  	u8         nic_vport_node_guid_modify[0x1];
959  	u8         nic_vport_port_guid_modify[0x1];
960  
961  	u8         vxlan_encap_decap[0x1];
962  	u8         nvgre_encap_decap[0x1];
963  	u8         reserved_at_22[0x1];
964  	u8         log_max_fdb_encap_uplink[0x5];
965  	u8         reserved_at_21[0x3];
966  	u8         log_max_packet_reformat_context[0x5];
967  	u8         reserved_2b[0x6];
968  	u8         max_encap_header_size[0xa];
969  
970  	u8         reserved_at_40[0xb];
971  	u8         log_max_esw_sf[0x5];
972  	u8         esw_sf_base_id[0x10];
973  
974  	u8         reserved_at_60[0x7a0];
975  
976  };
977  
978  struct mlx5_ifc_qos_cap_bits {
979  	u8         packet_pacing[0x1];
980  	u8         esw_scheduling[0x1];
981  	u8         esw_bw_share[0x1];
982  	u8         esw_rate_limit[0x1];
983  	u8         reserved_at_4[0x1];
984  	u8         packet_pacing_burst_bound[0x1];
985  	u8         packet_pacing_typical_size[0x1];
986  	u8         reserved_at_7[0x1];
987  	u8         nic_sq_scheduling[0x1];
988  	u8         nic_bw_share[0x1];
989  	u8         nic_rate_limit[0x1];
990  	u8         packet_pacing_uid[0x1];
991  	u8         log_esw_max_sched_depth[0x4];
992  	u8         reserved_at_10[0x10];
993  
994  	u8         reserved_at_20[0xb];
995  	u8         log_max_qos_nic_queue_group[0x5];
996  	u8         reserved_at_30[0x10];
997  
998  	u8         packet_pacing_max_rate[0x20];
999  
1000  	u8         packet_pacing_min_rate[0x20];
1001  
1002  	u8         reserved_at_80[0x10];
1003  	u8         packet_pacing_rate_table_size[0x10];
1004  
1005  	u8         esw_element_type[0x10];
1006  	u8         esw_tsar_type[0x10];
1007  
1008  	u8         reserved_at_c0[0x10];
1009  	u8         max_qos_para_vport[0x10];
1010  
1011  	u8         max_tsar_bw_share[0x20];
1012  
1013  	u8         nic_element_type[0x10];
1014  	u8         nic_tsar_type[0x10];
1015  
1016  	u8         reserved_at_120[0x3];
1017  	u8         log_meter_aso_granularity[0x5];
1018  	u8         reserved_at_128[0x3];
1019  	u8         log_meter_aso_max_alloc[0x5];
1020  	u8         reserved_at_130[0x3];
1021  	u8         log_max_num_meter_aso[0x5];
1022  	u8         reserved_at_138[0x8];
1023  
1024  	u8         reserved_at_140[0x6c0];
1025  };
1026  
1027  struct mlx5_ifc_debug_cap_bits {
1028  	u8         core_dump_general[0x1];
1029  	u8         core_dump_qp[0x1];
1030  	u8         reserved_at_2[0x7];
1031  	u8         resource_dump[0x1];
1032  	u8         reserved_at_a[0x16];
1033  
1034  	u8         reserved_at_20[0x2];
1035  	u8         stall_detect[0x1];
1036  	u8         reserved_at_23[0x1d];
1037  
1038  	u8         reserved_at_40[0x7c0];
1039  };
1040  
1041  struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1042  	u8         csum_cap[0x1];
1043  	u8         vlan_cap[0x1];
1044  	u8         lro_cap[0x1];
1045  	u8         lro_psh_flag[0x1];
1046  	u8         lro_time_stamp[0x1];
1047  	u8         reserved_at_5[0x2];
1048  	u8         wqe_vlan_insert[0x1];
1049  	u8         self_lb_en_modifiable[0x1];
1050  	u8         reserved_at_9[0x2];
1051  	u8         max_lso_cap[0x5];
1052  	u8         multi_pkt_send_wqe[0x2];
1053  	u8	   wqe_inline_mode[0x2];
1054  	u8         rss_ind_tbl_cap[0x4];
1055  	u8         reg_umr_sq[0x1];
1056  	u8         scatter_fcs[0x1];
1057  	u8         enhanced_multi_pkt_send_wqe[0x1];
1058  	u8         tunnel_lso_const_out_ip_id[0x1];
1059  	u8         tunnel_lro_gre[0x1];
1060  	u8         tunnel_lro_vxlan[0x1];
1061  	u8         tunnel_stateless_gre[0x1];
1062  	u8         tunnel_stateless_vxlan[0x1];
1063  
1064  	u8         swp[0x1];
1065  	u8         swp_csum[0x1];
1066  	u8         swp_lso[0x1];
1067  	u8         cqe_checksum_full[0x1];
1068  	u8         tunnel_stateless_geneve_tx[0x1];
1069  	u8         tunnel_stateless_mpls_over_udp[0x1];
1070  	u8         tunnel_stateless_mpls_over_gre[0x1];
1071  	u8         tunnel_stateless_vxlan_gpe[0x1];
1072  	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1073  	u8         tunnel_stateless_ip_over_ip[0x1];
1074  	u8         insert_trailer[0x1];
1075  	u8         reserved_at_2b[0x1];
1076  	u8         tunnel_stateless_ip_over_ip_rx[0x1];
1077  	u8         tunnel_stateless_ip_over_ip_tx[0x1];
1078  	u8         reserved_at_2e[0x2];
1079  	u8         max_vxlan_udp_ports[0x8];
1080  	u8         reserved_at_38[0x6];
1081  	u8         max_geneve_opt_len[0x1];
1082  	u8         tunnel_stateless_geneve_rx[0x1];
1083  
1084  	u8         reserved_at_40[0x10];
1085  	u8         lro_min_mss_size[0x10];
1086  
1087  	u8         reserved_at_60[0x120];
1088  
1089  	u8         lro_timer_supported_periods[4][0x20];
1090  
1091  	u8         reserved_at_200[0x600];
1092  };
1093  
1094  enum {
1095  	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1096  	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1097  	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1098  };
1099  
1100  struct mlx5_ifc_roce_cap_bits {
1101  	u8         roce_apm[0x1];
1102  	u8         reserved_at_1[0x3];
1103  	u8         sw_r_roce_src_udp_port[0x1];
1104  	u8         fl_rc_qp_when_roce_disabled[0x1];
1105  	u8         fl_rc_qp_when_roce_enabled[0x1];
1106  	u8         roce_cc_general[0x1];
1107  	u8	   qp_ooo_transmit_default[0x1];
1108  	u8         reserved_at_9[0x15];
1109  	u8	   qp_ts_format[0x2];
1110  
1111  	u8         reserved_at_20[0x60];
1112  
1113  	u8         reserved_at_80[0xc];
1114  	u8         l3_type[0x4];
1115  	u8         reserved_at_90[0x8];
1116  	u8         roce_version[0x8];
1117  
1118  	u8         reserved_at_a0[0x10];
1119  	u8         r_roce_dest_udp_port[0x10];
1120  
1121  	u8         r_roce_max_src_udp_port[0x10];
1122  	u8         r_roce_min_src_udp_port[0x10];
1123  
1124  	u8         reserved_at_e0[0x10];
1125  	u8         roce_address_table_size[0x10];
1126  
1127  	u8         reserved_at_100[0x700];
1128  };
1129  
1130  struct mlx5_ifc_sync_steering_in_bits {
1131  	u8         opcode[0x10];
1132  	u8         uid[0x10];
1133  
1134  	u8         reserved_at_20[0x10];
1135  	u8         op_mod[0x10];
1136  
1137  	u8         reserved_at_40[0xc0];
1138  };
1139  
1140  struct mlx5_ifc_sync_steering_out_bits {
1141  	u8         status[0x8];
1142  	u8         reserved_at_8[0x18];
1143  
1144  	u8         syndrome[0x20];
1145  
1146  	u8         reserved_at_40[0x40];
1147  };
1148  
1149  struct mlx5_ifc_sync_crypto_in_bits {
1150  	u8         opcode[0x10];
1151  	u8         uid[0x10];
1152  
1153  	u8         reserved_at_20[0x10];
1154  	u8         op_mod[0x10];
1155  
1156  	u8         reserved_at_40[0x20];
1157  
1158  	u8         reserved_at_60[0x10];
1159  	u8         crypto_type[0x10];
1160  
1161  	u8         reserved_at_80[0x80];
1162  };
1163  
1164  struct mlx5_ifc_sync_crypto_out_bits {
1165  	u8         status[0x8];
1166  	u8         reserved_at_8[0x18];
1167  
1168  	u8         syndrome[0x20];
1169  
1170  	u8         reserved_at_40[0x40];
1171  };
1172  
1173  struct mlx5_ifc_device_mem_cap_bits {
1174  	u8         memic[0x1];
1175  	u8         reserved_at_1[0x1f];
1176  
1177  	u8         reserved_at_20[0xb];
1178  	u8         log_min_memic_alloc_size[0x5];
1179  	u8         reserved_at_30[0x8];
1180  	u8	   log_max_memic_addr_alignment[0x8];
1181  
1182  	u8         memic_bar_start_addr[0x40];
1183  
1184  	u8         memic_bar_size[0x20];
1185  
1186  	u8         max_memic_size[0x20];
1187  
1188  	u8         steering_sw_icm_start_address[0x40];
1189  
1190  	u8         reserved_at_100[0x8];
1191  	u8         log_header_modify_sw_icm_size[0x8];
1192  	u8         reserved_at_110[0x2];
1193  	u8         log_sw_icm_alloc_granularity[0x6];
1194  	u8         log_steering_sw_icm_size[0x8];
1195  
1196  	u8         reserved_at_120[0x18];
1197  	u8         log_header_modify_pattern_sw_icm_size[0x8];
1198  
1199  	u8         header_modify_sw_icm_start_address[0x40];
1200  
1201  	u8         reserved_at_180[0x40];
1202  
1203  	u8         header_modify_pattern_sw_icm_start_address[0x40];
1204  
1205  	u8         memic_operations[0x20];
1206  
1207  	u8         reserved_at_220[0x5e0];
1208  };
1209  
1210  struct mlx5_ifc_device_event_cap_bits {
1211  	u8         user_affiliated_events[4][0x40];
1212  
1213  	u8         user_unaffiliated_events[4][0x40];
1214  };
1215  
1216  struct mlx5_ifc_virtio_emulation_cap_bits {
1217  	u8         desc_tunnel_offload_type[0x1];
1218  	u8         eth_frame_offload_type[0x1];
1219  	u8         virtio_version_1_0[0x1];
1220  	u8         device_features_bits_mask[0xd];
1221  	u8         event_mode[0x8];
1222  	u8         virtio_queue_type[0x8];
1223  
1224  	u8         max_tunnel_desc[0x10];
1225  	u8         reserved_at_30[0x3];
1226  	u8         log_doorbell_stride[0x5];
1227  	u8         reserved_at_38[0x3];
1228  	u8         log_doorbell_bar_size[0x5];
1229  
1230  	u8         doorbell_bar_offset[0x40];
1231  
1232  	u8         max_emulated_devices[0x8];
1233  	u8         max_num_virtio_queues[0x18];
1234  
1235  	u8         reserved_at_a0[0x60];
1236  
1237  	u8         umem_1_buffer_param_a[0x20];
1238  
1239  	u8         umem_1_buffer_param_b[0x20];
1240  
1241  	u8         umem_2_buffer_param_a[0x20];
1242  
1243  	u8         umem_2_buffer_param_b[0x20];
1244  
1245  	u8         umem_3_buffer_param_a[0x20];
1246  
1247  	u8         umem_3_buffer_param_b[0x20];
1248  
1249  	u8         reserved_at_1c0[0x640];
1250  };
1251  
1252  enum {
1253  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1254  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1255  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1256  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1257  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1258  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1259  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1260  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1261  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1262  };
1263  
1264  enum {
1265  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1266  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1267  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1268  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1269  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1270  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1271  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1272  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1273  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1274  };
1275  
1276  struct mlx5_ifc_atomic_caps_bits {
1277  	u8         reserved_at_0[0x40];
1278  
1279  	u8         atomic_req_8B_endianness_mode[0x2];
1280  	u8         reserved_at_42[0x4];
1281  	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1282  
1283  	u8         reserved_at_47[0x19];
1284  
1285  	u8         reserved_at_60[0x20];
1286  
1287  	u8         reserved_at_80[0x10];
1288  	u8         atomic_operations[0x10];
1289  
1290  	u8         reserved_at_a0[0x10];
1291  	u8         atomic_size_qp[0x10];
1292  
1293  	u8         reserved_at_c0[0x10];
1294  	u8         atomic_size_dc[0x10];
1295  
1296  	u8         reserved_at_e0[0x720];
1297  };
1298  
1299  struct mlx5_ifc_odp_cap_bits {
1300  	u8         reserved_at_0[0x40];
1301  
1302  	u8         sig[0x1];
1303  	u8         reserved_at_41[0x1f];
1304  
1305  	u8         reserved_at_60[0x20];
1306  
1307  	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1308  
1309  	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1310  
1311  	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1312  
1313  	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1314  
1315  	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1316  
1317  	u8         reserved_at_120[0x6E0];
1318  };
1319  
1320  struct mlx5_ifc_tls_cap_bits {
1321  	u8         tls_1_2_aes_gcm_128[0x1];
1322  	u8         tls_1_3_aes_gcm_128[0x1];
1323  	u8         tls_1_2_aes_gcm_256[0x1];
1324  	u8         tls_1_3_aes_gcm_256[0x1];
1325  	u8         reserved_at_4[0x1c];
1326  
1327  	u8         reserved_at_20[0x7e0];
1328  };
1329  
1330  struct mlx5_ifc_ipsec_cap_bits {
1331  	u8         ipsec_full_offload[0x1];
1332  	u8         ipsec_crypto_offload[0x1];
1333  	u8         ipsec_esn[0x1];
1334  	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1335  	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1336  	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1337  	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1338  	u8         reserved_at_7[0x4];
1339  	u8         log_max_ipsec_offload[0x5];
1340  	u8         reserved_at_10[0x10];
1341  
1342  	u8         min_log_ipsec_full_replay_window[0x8];
1343  	u8         max_log_ipsec_full_replay_window[0x8];
1344  	u8         reserved_at_30[0x7d0];
1345  };
1346  
1347  struct mlx5_ifc_macsec_cap_bits {
1348  	u8    macsec_epn[0x1];
1349  	u8    reserved_at_1[0x2];
1350  	u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1351  	u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1352  	u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1353  	u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1354  	u8    reserved_at_7[0x4];
1355  	u8    log_max_macsec_offload[0x5];
1356  	u8    reserved_at_10[0x10];
1357  
1358  	u8    min_log_macsec_full_replay_window[0x8];
1359  	u8    max_log_macsec_full_replay_window[0x8];
1360  	u8    reserved_at_30[0x10];
1361  
1362  	u8    reserved_at_40[0x7c0];
1363  };
1364  
1365  enum {
1366  	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1367  	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1368  	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1369  	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1370  };
1371  
1372  enum {
1373  	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1374  	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1375  };
1376  
1377  enum {
1378  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1379  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1380  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1381  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1382  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1383  };
1384  
1385  enum {
1386  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1387  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1388  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1389  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1390  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1391  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1392  };
1393  
1394  enum {
1395  	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1396  	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1397  };
1398  
1399  enum {
1400  	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1401  	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1402  	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1403  };
1404  
1405  enum {
1406  	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1407  	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1408  };
1409  
1410  enum {
1411  	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1412  	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1413  	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1414  };
1415  
1416  enum {
1417  	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1418  	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1419  	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1420  	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1421  	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1422  	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1423  	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1424  	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1425  	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1426  	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1427  	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1428  	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1429  };
1430  
1431  enum {
1432  	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1433  	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1434  };
1435  
1436  #define MLX5_FC_BULK_SIZE_FACTOR 128
1437  
1438  enum mlx5_fc_bulk_alloc_bitmask {
1439  	MLX5_FC_BULK_128   = (1 << 0),
1440  	MLX5_FC_BULK_256   = (1 << 1),
1441  	MLX5_FC_BULK_512   = (1 << 2),
1442  	MLX5_FC_BULK_1024  = (1 << 3),
1443  	MLX5_FC_BULK_2048  = (1 << 4),
1444  	MLX5_FC_BULK_4096  = (1 << 5),
1445  	MLX5_FC_BULK_8192  = (1 << 6),
1446  	MLX5_FC_BULK_16384 = (1 << 7),
1447  };
1448  
1449  #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1450  
1451  #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1452  
1453  enum {
1454  	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1455  	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1456  	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1457  };
1458  
1459  struct mlx5_ifc_cmd_hca_cap_bits {
1460  	u8         reserved_at_0[0x10];
1461  	u8         shared_object_to_user_object_allowed[0x1];
1462  	u8         reserved_at_13[0xe];
1463  	u8         vhca_resource_manager[0x1];
1464  
1465  	u8         hca_cap_2[0x1];
1466  	u8         create_lag_when_not_master_up[0x1];
1467  	u8         dtor[0x1];
1468  	u8         event_on_vhca_state_teardown_request[0x1];
1469  	u8         event_on_vhca_state_in_use[0x1];
1470  	u8         event_on_vhca_state_active[0x1];
1471  	u8         event_on_vhca_state_allocated[0x1];
1472  	u8         event_on_vhca_state_invalid[0x1];
1473  	u8         reserved_at_28[0x8];
1474  	u8         vhca_id[0x10];
1475  
1476  	u8         reserved_at_40[0x40];
1477  
1478  	u8         log_max_srq_sz[0x8];
1479  	u8         log_max_qp_sz[0x8];
1480  	u8         event_cap[0x1];
1481  	u8         reserved_at_91[0x2];
1482  	u8         isolate_vl_tc_new[0x1];
1483  	u8         reserved_at_94[0x4];
1484  	u8         prio_tag_required[0x1];
1485  	u8         reserved_at_99[0x2];
1486  	u8         log_max_qp[0x5];
1487  
1488  	u8         reserved_at_a0[0x3];
1489  	u8	   ece_support[0x1];
1490  	u8	   reserved_at_a4[0x5];
1491  	u8         reg_c_preserve[0x1];
1492  	u8         reserved_at_aa[0x1];
1493  	u8         log_max_srq[0x5];
1494  	u8         reserved_at_b0[0x1];
1495  	u8         uplink_follow[0x1];
1496  	u8         ts_cqe_to_dest_cqn[0x1];
1497  	u8         reserved_at_b3[0x6];
1498  	u8         go_back_n[0x1];
1499  	u8         shampo[0x1];
1500  	u8         reserved_at_bb[0x5];
1501  
1502  	u8         max_sgl_for_optimized_performance[0x8];
1503  	u8         log_max_cq_sz[0x8];
1504  	u8         relaxed_ordering_write_umr[0x1];
1505  	u8         relaxed_ordering_read_umr[0x1];
1506  	u8         reserved_at_d2[0x7];
1507  	u8         virtio_net_device_emualtion_manager[0x1];
1508  	u8         virtio_blk_device_emualtion_manager[0x1];
1509  	u8         log_max_cq[0x5];
1510  
1511  	u8         log_max_eq_sz[0x8];
1512  	u8         relaxed_ordering_write[0x1];
1513  	u8         relaxed_ordering_read_pci_enabled[0x1];
1514  	u8         log_max_mkey[0x6];
1515  	u8         reserved_at_f0[0x6];
1516  	u8	   terminate_scatter_list_mkey[0x1];
1517  	u8	   repeated_mkey[0x1];
1518  	u8         dump_fill_mkey[0x1];
1519  	u8         reserved_at_f9[0x2];
1520  	u8         fast_teardown[0x1];
1521  	u8         log_max_eq[0x4];
1522  
1523  	u8         max_indirection[0x8];
1524  	u8         fixed_buffer_size[0x1];
1525  	u8         log_max_mrw_sz[0x7];
1526  	u8         force_teardown[0x1];
1527  	u8         reserved_at_111[0x1];
1528  	u8         log_max_bsf_list_size[0x6];
1529  	u8         umr_extended_translation_offset[0x1];
1530  	u8         null_mkey[0x1];
1531  	u8         log_max_klm_list_size[0x6];
1532  
1533  	u8         reserved_at_120[0x2];
1534  	u8	   qpc_extension[0x1];
1535  	u8	   reserved_at_123[0x7];
1536  	u8         log_max_ra_req_dc[0x6];
1537  	u8         reserved_at_130[0x2];
1538  	u8         eth_wqe_too_small[0x1];
1539  	u8         reserved_at_133[0x6];
1540  	u8         vnic_env_cq_overrun[0x1];
1541  	u8         log_max_ra_res_dc[0x6];
1542  
1543  	u8         reserved_at_140[0x5];
1544  	u8         release_all_pages[0x1];
1545  	u8         must_not_use[0x1];
1546  	u8         reserved_at_147[0x2];
1547  	u8         roce_accl[0x1];
1548  	u8         log_max_ra_req_qp[0x6];
1549  	u8         reserved_at_150[0xa];
1550  	u8         log_max_ra_res_qp[0x6];
1551  
1552  	u8         end_pad[0x1];
1553  	u8         cc_query_allowed[0x1];
1554  	u8         cc_modify_allowed[0x1];
1555  	u8         start_pad[0x1];
1556  	u8         cache_line_128byte[0x1];
1557  	u8         reserved_at_165[0x4];
1558  	u8         rts2rts_qp_counters_set_id[0x1];
1559  	u8         reserved_at_16a[0x2];
1560  	u8         vnic_env_int_rq_oob[0x1];
1561  	u8         sbcam_reg[0x1];
1562  	u8         reserved_at_16e[0x1];
1563  	u8         qcam_reg[0x1];
1564  	u8         gid_table_size[0x10];
1565  
1566  	u8         out_of_seq_cnt[0x1];
1567  	u8         vport_counters[0x1];
1568  	u8         retransmission_q_counters[0x1];
1569  	u8         debug[0x1];
1570  	u8         modify_rq_counter_set_id[0x1];
1571  	u8         rq_delay_drop[0x1];
1572  	u8         max_qp_cnt[0xa];
1573  	u8         pkey_table_size[0x10];
1574  
1575  	u8         vport_group_manager[0x1];
1576  	u8         vhca_group_manager[0x1];
1577  	u8         ib_virt[0x1];
1578  	u8         eth_virt[0x1];
1579  	u8         vnic_env_queue_counters[0x1];
1580  	u8         ets[0x1];
1581  	u8         nic_flow_table[0x1];
1582  	u8         eswitch_manager[0x1];
1583  	u8         device_memory[0x1];
1584  	u8         mcam_reg[0x1];
1585  	u8         pcam_reg[0x1];
1586  	u8         local_ca_ack_delay[0x5];
1587  	u8         port_module_event[0x1];
1588  	u8         enhanced_error_q_counters[0x1];
1589  	u8         ports_check[0x1];
1590  	u8         reserved_at_1b3[0x1];
1591  	u8         disable_link_up[0x1];
1592  	u8         beacon_led[0x1];
1593  	u8         port_type[0x2];
1594  	u8         num_ports[0x8];
1595  
1596  	u8         reserved_at_1c0[0x1];
1597  	u8         pps[0x1];
1598  	u8         pps_modify[0x1];
1599  	u8         log_max_msg[0x5];
1600  	u8         reserved_at_1c8[0x4];
1601  	u8         max_tc[0x4];
1602  	u8         temp_warn_event[0x1];
1603  	u8         dcbx[0x1];
1604  	u8         general_notification_event[0x1];
1605  	u8         reserved_at_1d3[0x2];
1606  	u8         fpga[0x1];
1607  	u8         rol_s[0x1];
1608  	u8         rol_g[0x1];
1609  	u8         reserved_at_1d8[0x1];
1610  	u8         wol_s[0x1];
1611  	u8         wol_g[0x1];
1612  	u8         wol_a[0x1];
1613  	u8         wol_b[0x1];
1614  	u8         wol_m[0x1];
1615  	u8         wol_u[0x1];
1616  	u8         wol_p[0x1];
1617  
1618  	u8         stat_rate_support[0x10];
1619  	u8         reserved_at_1f0[0x1];
1620  	u8         pci_sync_for_fw_update_event[0x1];
1621  	u8         reserved_at_1f2[0x6];
1622  	u8         init2_lag_tx_port_affinity[0x1];
1623  	u8         reserved_at_1fa[0x3];
1624  	u8         cqe_version[0x4];
1625  
1626  	u8         compact_address_vector[0x1];
1627  	u8         striding_rq[0x1];
1628  	u8         reserved_at_202[0x1];
1629  	u8         ipoib_enhanced_offloads[0x1];
1630  	u8         ipoib_basic_offloads[0x1];
1631  	u8         reserved_at_205[0x1];
1632  	u8         repeated_block_disabled[0x1];
1633  	u8         umr_modify_entity_size_disabled[0x1];
1634  	u8         umr_modify_atomic_disabled[0x1];
1635  	u8         umr_indirect_mkey_disabled[0x1];
1636  	u8         umr_fence[0x2];
1637  	u8         dc_req_scat_data_cqe[0x1];
1638  	u8         reserved_at_20d[0x2];
1639  	u8         drain_sigerr[0x1];
1640  	u8         cmdif_checksum[0x2];
1641  	u8         sigerr_cqe[0x1];
1642  	u8         reserved_at_213[0x1];
1643  	u8         wq_signature[0x1];
1644  	u8         sctr_data_cqe[0x1];
1645  	u8         reserved_at_216[0x1];
1646  	u8         sho[0x1];
1647  	u8         tph[0x1];
1648  	u8         rf[0x1];
1649  	u8         dct[0x1];
1650  	u8         qos[0x1];
1651  	u8         eth_net_offloads[0x1];
1652  	u8         roce[0x1];
1653  	u8         atomic[0x1];
1654  	u8         reserved_at_21f[0x1];
1655  
1656  	u8         cq_oi[0x1];
1657  	u8         cq_resize[0x1];
1658  	u8         cq_moderation[0x1];
1659  	u8         reserved_at_223[0x3];
1660  	u8         cq_eq_remap[0x1];
1661  	u8         pg[0x1];
1662  	u8         block_lb_mc[0x1];
1663  	u8         reserved_at_229[0x1];
1664  	u8         scqe_break_moderation[0x1];
1665  	u8         cq_period_start_from_cqe[0x1];
1666  	u8         cd[0x1];
1667  	u8         reserved_at_22d[0x1];
1668  	u8         apm[0x1];
1669  	u8         vector_calc[0x1];
1670  	u8         umr_ptr_rlky[0x1];
1671  	u8	   imaicl[0x1];
1672  	u8	   qp_packet_based[0x1];
1673  	u8         reserved_at_233[0x3];
1674  	u8         qkv[0x1];
1675  	u8         pkv[0x1];
1676  	u8         set_deth_sqpn[0x1];
1677  	u8         reserved_at_239[0x3];
1678  	u8         xrc[0x1];
1679  	u8         ud[0x1];
1680  	u8         uc[0x1];
1681  	u8         rc[0x1];
1682  
1683  	u8         uar_4k[0x1];
1684  	u8         reserved_at_241[0x7];
1685  	u8         fl_rc_qp_when_roce_disabled[0x1];
1686  	u8         regexp_params[0x1];
1687  	u8         uar_sz[0x6];
1688  	u8         port_selection_cap[0x1];
1689  	u8         reserved_at_251[0x1];
1690  	u8         umem_uid_0[0x1];
1691  	u8         reserved_at_253[0x5];
1692  	u8         log_pg_sz[0x8];
1693  
1694  	u8         bf[0x1];
1695  	u8         driver_version[0x1];
1696  	u8         pad_tx_eth_packet[0x1];
1697  	u8         reserved_at_263[0x3];
1698  	u8         mkey_by_name[0x1];
1699  	u8         reserved_at_267[0x4];
1700  
1701  	u8         log_bf_reg_size[0x5];
1702  
1703  	u8         reserved_at_270[0x3];
1704  	u8	   qp_error_syndrome[0x1];
1705  	u8	   reserved_at_274[0x2];
1706  	u8         lag_dct[0x2];
1707  	u8         lag_tx_port_affinity[0x1];
1708  	u8         lag_native_fdb_selection[0x1];
1709  	u8         reserved_at_27a[0x1];
1710  	u8         lag_master[0x1];
1711  	u8         num_lag_ports[0x4];
1712  
1713  	u8         reserved_at_280[0x10];
1714  	u8         max_wqe_sz_sq[0x10];
1715  
1716  	u8         reserved_at_2a0[0x10];
1717  	u8         max_wqe_sz_rq[0x10];
1718  
1719  	u8         max_flow_counter_31_16[0x10];
1720  	u8         max_wqe_sz_sq_dc[0x10];
1721  
1722  	u8         reserved_at_2e0[0x7];
1723  	u8         max_qp_mcg[0x19];
1724  
1725  	u8         reserved_at_300[0x10];
1726  	u8         flow_counter_bulk_alloc[0x8];
1727  	u8         log_max_mcg[0x8];
1728  
1729  	u8         reserved_at_320[0x3];
1730  	u8         log_max_transport_domain[0x5];
1731  	u8         reserved_at_328[0x2];
1732  	u8	   relaxed_ordering_read[0x1];
1733  	u8         log_max_pd[0x5];
1734  	u8         reserved_at_330[0x6];
1735  	u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1736  	u8         vnic_env_cnt_steering_fail[0x1];
1737  	u8         vport_counter_local_loopback[0x1];
1738  	u8         q_counter_aggregation[0x1];
1739  	u8         q_counter_other_vport[0x1];
1740  	u8         log_max_xrcd[0x5];
1741  
1742  	u8         nic_receive_steering_discard[0x1];
1743  	u8         receive_discard_vport_down[0x1];
1744  	u8         transmit_discard_vport_down[0x1];
1745  	u8         eq_overrun_count[0x1];
1746  	u8         reserved_at_344[0x1];
1747  	u8         invalid_command_count[0x1];
1748  	u8         quota_exceeded_count[0x1];
1749  	u8         reserved_at_347[0x1];
1750  	u8         log_max_flow_counter_bulk[0x8];
1751  	u8         max_flow_counter_15_0[0x10];
1752  
1753  
1754  	u8         reserved_at_360[0x3];
1755  	u8         log_max_rq[0x5];
1756  	u8         reserved_at_368[0x3];
1757  	u8         log_max_sq[0x5];
1758  	u8         reserved_at_370[0x3];
1759  	u8         log_max_tir[0x5];
1760  	u8         reserved_at_378[0x3];
1761  	u8         log_max_tis[0x5];
1762  
1763  	u8         basic_cyclic_rcv_wqe[0x1];
1764  	u8         reserved_at_381[0x2];
1765  	u8         log_max_rmp[0x5];
1766  	u8         reserved_at_388[0x3];
1767  	u8         log_max_rqt[0x5];
1768  	u8         reserved_at_390[0x3];
1769  	u8         log_max_rqt_size[0x5];
1770  	u8         reserved_at_398[0x3];
1771  	u8         log_max_tis_per_sq[0x5];
1772  
1773  	u8         ext_stride_num_range[0x1];
1774  	u8         roce_rw_supported[0x1];
1775  	u8         log_max_current_uc_list_wr_supported[0x1];
1776  	u8         log_max_stride_sz_rq[0x5];
1777  	u8         reserved_at_3a8[0x3];
1778  	u8         log_min_stride_sz_rq[0x5];
1779  	u8         reserved_at_3b0[0x3];
1780  	u8         log_max_stride_sz_sq[0x5];
1781  	u8         reserved_at_3b8[0x3];
1782  	u8         log_min_stride_sz_sq[0x5];
1783  
1784  	u8         hairpin[0x1];
1785  	u8         reserved_at_3c1[0x2];
1786  	u8         log_max_hairpin_queues[0x5];
1787  	u8         reserved_at_3c8[0x3];
1788  	u8         log_max_hairpin_wq_data_sz[0x5];
1789  	u8         reserved_at_3d0[0x3];
1790  	u8         log_max_hairpin_num_packets[0x5];
1791  	u8         reserved_at_3d8[0x3];
1792  	u8         log_max_wq_sz[0x5];
1793  
1794  	u8         nic_vport_change_event[0x1];
1795  	u8         disable_local_lb_uc[0x1];
1796  	u8         disable_local_lb_mc[0x1];
1797  	u8         log_min_hairpin_wq_data_sz[0x5];
1798  	u8         reserved_at_3e8[0x2];
1799  	u8         vhca_state[0x1];
1800  	u8         log_max_vlan_list[0x5];
1801  	u8         reserved_at_3f0[0x3];
1802  	u8         log_max_current_mc_list[0x5];
1803  	u8         reserved_at_3f8[0x3];
1804  	u8         log_max_current_uc_list[0x5];
1805  
1806  	u8         general_obj_types[0x40];
1807  
1808  	u8         sq_ts_format[0x2];
1809  	u8         rq_ts_format[0x2];
1810  	u8         steering_format_version[0x4];
1811  	u8         create_qp_start_hint[0x18];
1812  
1813  	u8         reserved_at_460[0x1];
1814  	u8         ats[0x1];
1815  	u8         reserved_at_462[0x1];
1816  	u8         log_max_uctx[0x5];
1817  	u8         reserved_at_468[0x1];
1818  	u8         crypto[0x1];
1819  	u8         ipsec_offload[0x1];
1820  	u8         log_max_umem[0x5];
1821  	u8         max_num_eqs[0x10];
1822  
1823  	u8         reserved_at_480[0x1];
1824  	u8         tls_tx[0x1];
1825  	u8         tls_rx[0x1];
1826  	u8         log_max_l2_table[0x5];
1827  	u8         reserved_at_488[0x8];
1828  	u8         log_uar_page_sz[0x10];
1829  
1830  	u8         reserved_at_4a0[0x20];
1831  	u8         device_frequency_mhz[0x20];
1832  	u8         device_frequency_khz[0x20];
1833  
1834  	u8         reserved_at_500[0x20];
1835  	u8	   num_of_uars_per_page[0x20];
1836  
1837  	u8         flex_parser_protocols[0x20];
1838  
1839  	u8         max_geneve_tlv_options[0x8];
1840  	u8         reserved_at_568[0x3];
1841  	u8         max_geneve_tlv_option_data_len[0x5];
1842  	u8         reserved_at_570[0x9];
1843  	u8         adv_virtualization[0x1];
1844  	u8         reserved_at_57a[0x6];
1845  
1846  	u8	   reserved_at_580[0xb];
1847  	u8	   log_max_dci_stream_channels[0x5];
1848  	u8	   reserved_at_590[0x3];
1849  	u8	   log_max_dci_errored_streams[0x5];
1850  	u8	   reserved_at_598[0x8];
1851  
1852  	u8         reserved_at_5a0[0x10];
1853  	u8         enhanced_cqe_compression[0x1];
1854  	u8         reserved_at_5b1[0x2];
1855  	u8         log_max_dek[0x5];
1856  	u8         reserved_at_5b8[0x4];
1857  	u8         mini_cqe_resp_stride_index[0x1];
1858  	u8         cqe_128_always[0x1];
1859  	u8         cqe_compression_128[0x1];
1860  	u8         cqe_compression[0x1];
1861  
1862  	u8         cqe_compression_timeout[0x10];
1863  	u8         cqe_compression_max_num[0x10];
1864  
1865  	u8         reserved_at_5e0[0x8];
1866  	u8         flex_parser_id_gtpu_dw_0[0x4];
1867  	u8         reserved_at_5ec[0x4];
1868  	u8         tag_matching[0x1];
1869  	u8         rndv_offload_rc[0x1];
1870  	u8         rndv_offload_dc[0x1];
1871  	u8         log_tag_matching_list_sz[0x5];
1872  	u8         reserved_at_5f8[0x3];
1873  	u8         log_max_xrq[0x5];
1874  
1875  	u8	   affiliate_nic_vport_criteria[0x8];
1876  	u8	   native_port_num[0x8];
1877  	u8	   num_vhca_ports[0x8];
1878  	u8         flex_parser_id_gtpu_teid[0x4];
1879  	u8         reserved_at_61c[0x2];
1880  	u8	   sw_owner_id[0x1];
1881  	u8         reserved_at_61f[0x1];
1882  
1883  	u8         max_num_of_monitor_counters[0x10];
1884  	u8         num_ppcnt_monitor_counters[0x10];
1885  
1886  	u8         max_num_sf[0x10];
1887  	u8         num_q_monitor_counters[0x10];
1888  
1889  	u8         reserved_at_660[0x20];
1890  
1891  	u8         sf[0x1];
1892  	u8         sf_set_partition[0x1];
1893  	u8         reserved_at_682[0x1];
1894  	u8         log_max_sf[0x5];
1895  	u8         apu[0x1];
1896  	u8         reserved_at_689[0x4];
1897  	u8         migration[0x1];
1898  	u8         reserved_at_68e[0x2];
1899  	u8         log_min_sf_size[0x8];
1900  	u8         max_num_sf_partitions[0x8];
1901  
1902  	u8         uctx_cap[0x20];
1903  
1904  	u8         reserved_at_6c0[0x4];
1905  	u8         flex_parser_id_geneve_tlv_option_0[0x4];
1906  	u8         flex_parser_id_icmp_dw1[0x4];
1907  	u8         flex_parser_id_icmp_dw0[0x4];
1908  	u8         flex_parser_id_icmpv6_dw1[0x4];
1909  	u8         flex_parser_id_icmpv6_dw0[0x4];
1910  	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1911  	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1912  
1913  	u8         max_num_match_definer[0x10];
1914  	u8	   sf_base_id[0x10];
1915  
1916  	u8         flex_parser_id_gtpu_dw_2[0x4];
1917  	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1918  	u8	   num_total_dynamic_vf_msix[0x18];
1919  	u8	   reserved_at_720[0x14];
1920  	u8	   dynamic_msix_table_size[0xc];
1921  	u8	   reserved_at_740[0xc];
1922  	u8	   min_dynamic_vf_msix_table_size[0x4];
1923  	u8	   reserved_at_750[0x4];
1924  	u8	   max_dynamic_vf_msix_table_size[0xc];
1925  
1926  	u8         reserved_at_760[0x3];
1927  	u8         log_max_num_header_modify_argument[0x5];
1928  	u8         reserved_at_768[0x4];
1929  	u8         log_header_modify_argument_granularity[0x4];
1930  	u8         reserved_at_770[0x3];
1931  	u8         log_header_modify_argument_max_alloc[0x5];
1932  	u8         reserved_at_778[0x8];
1933  
1934  	u8	   vhca_tunnel_commands[0x40];
1935  	u8         match_definer_format_supported[0x40];
1936  };
1937  
1938  struct mlx5_ifc_cmd_hca_cap_2_bits {
1939  	u8	   reserved_at_0[0x80];
1940  
1941  	u8         migratable[0x1];
1942  	u8         reserved_at_81[0x1f];
1943  
1944  	u8	   max_reformat_insert_size[0x8];
1945  	u8	   max_reformat_insert_offset[0x8];
1946  	u8	   max_reformat_remove_size[0x8];
1947  	u8	   max_reformat_remove_offset[0x8];
1948  
1949  	u8	   reserved_at_c0[0x8];
1950  	u8	   migration_multi_load[0x1];
1951  	u8	   migration_tracking_state[0x1];
1952  	u8	   reserved_at_ca[0x16];
1953  
1954  	u8	   reserved_at_e0[0xc0];
1955  
1956  	u8	   flow_table_type_2_type[0x8];
1957  	u8	   reserved_at_1a8[0x3];
1958  	u8	   log_min_mkey_entity_size[0x5];
1959  	u8	   reserved_at_1b0[0x10];
1960  
1961  	u8	   reserved_at_1c0[0x60];
1962  
1963  	u8	   reserved_at_220[0x1];
1964  	u8	   sw_vhca_id_valid[0x1];
1965  	u8	   sw_vhca_id[0xe];
1966  	u8	   reserved_at_230[0x10];
1967  
1968  	u8	   reserved_at_240[0xb];
1969  	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
1970  	u8	   reserved_at_250[0x10];
1971  
1972  	u8	   reserved_at_260[0x120];
1973  	u8	   reserved_at_380[0x10];
1974  	u8	   ec_vf_vport_base[0x10];
1975  	u8	   reserved_at_3a0[0x460];
1976  };
1977  
1978  enum mlx5_ifc_flow_destination_type {
1979  	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1980  	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1981  	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1982  	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1983  	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
1984  	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
1985  };
1986  
1987  enum mlx5_flow_table_miss_action {
1988  	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1989  	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1990  	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1991  };
1992  
1993  struct mlx5_ifc_dest_format_struct_bits {
1994  	u8         destination_type[0x8];
1995  	u8         destination_id[0x18];
1996  
1997  	u8         destination_eswitch_owner_vhca_id_valid[0x1];
1998  	u8         packet_reformat[0x1];
1999  	u8         reserved_at_22[0x6];
2000  	u8         destination_table_type[0x8];
2001  	u8         destination_eswitch_owner_vhca_id[0x10];
2002  };
2003  
2004  struct mlx5_ifc_flow_counter_list_bits {
2005  	u8         flow_counter_id[0x20];
2006  
2007  	u8         reserved_at_20[0x20];
2008  };
2009  
2010  struct mlx5_ifc_extended_dest_format_bits {
2011  	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2012  
2013  	u8         packet_reformat_id[0x20];
2014  
2015  	u8         reserved_at_60[0x20];
2016  };
2017  
2018  union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
2019  	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2020  	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2021  };
2022  
2023  struct mlx5_ifc_fte_match_param_bits {
2024  	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2025  
2026  	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2027  
2028  	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2029  
2030  	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2031  
2032  	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2033  
2034  	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2035  
2036  	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2037  
2038  	u8         reserved_at_e00[0x200];
2039  };
2040  
2041  enum {
2042  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2043  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2044  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2045  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2046  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2047  };
2048  
2049  struct mlx5_ifc_rx_hash_field_select_bits {
2050  	u8         l3_prot_type[0x1];
2051  	u8         l4_prot_type[0x1];
2052  	u8         selected_fields[0x1e];
2053  };
2054  
2055  enum {
2056  	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2057  	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2058  };
2059  
2060  enum {
2061  	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2062  	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2063  };
2064  
2065  struct mlx5_ifc_wq_bits {
2066  	u8         wq_type[0x4];
2067  	u8         wq_signature[0x1];
2068  	u8         end_padding_mode[0x2];
2069  	u8         cd_slave[0x1];
2070  	u8         reserved_at_8[0x18];
2071  
2072  	u8         hds_skip_first_sge[0x1];
2073  	u8         log2_hds_buf_size[0x3];
2074  	u8         reserved_at_24[0x7];
2075  	u8         page_offset[0x5];
2076  	u8         lwm[0x10];
2077  
2078  	u8         reserved_at_40[0x8];
2079  	u8         pd[0x18];
2080  
2081  	u8         reserved_at_60[0x8];
2082  	u8         uar_page[0x18];
2083  
2084  	u8         dbr_addr[0x40];
2085  
2086  	u8         hw_counter[0x20];
2087  
2088  	u8         sw_counter[0x20];
2089  
2090  	u8         reserved_at_100[0xc];
2091  	u8         log_wq_stride[0x4];
2092  	u8         reserved_at_110[0x3];
2093  	u8         log_wq_pg_sz[0x5];
2094  	u8         reserved_at_118[0x3];
2095  	u8         log_wq_sz[0x5];
2096  
2097  	u8         dbr_umem_valid[0x1];
2098  	u8         wq_umem_valid[0x1];
2099  	u8         reserved_at_122[0x1];
2100  	u8         log_hairpin_num_packets[0x5];
2101  	u8         reserved_at_128[0x3];
2102  	u8         log_hairpin_data_sz[0x5];
2103  
2104  	u8         reserved_at_130[0x4];
2105  	u8         log_wqe_num_of_strides[0x4];
2106  	u8         two_byte_shift_en[0x1];
2107  	u8         reserved_at_139[0x4];
2108  	u8         log_wqe_stride_size[0x3];
2109  
2110  	u8         reserved_at_140[0x80];
2111  
2112  	u8         headers_mkey[0x20];
2113  
2114  	u8         shampo_enable[0x1];
2115  	u8         reserved_at_1e1[0x4];
2116  	u8         log_reservation_size[0x3];
2117  	u8         reserved_at_1e8[0x5];
2118  	u8         log_max_num_of_packets_per_reservation[0x3];
2119  	u8         reserved_at_1f0[0x6];
2120  	u8         log_headers_entry_size[0x2];
2121  	u8         reserved_at_1f8[0x4];
2122  	u8         log_headers_buffer_entry_num[0x4];
2123  
2124  	u8         reserved_at_200[0x400];
2125  
2126  	struct mlx5_ifc_cmd_pas_bits pas[];
2127  };
2128  
2129  struct mlx5_ifc_rq_num_bits {
2130  	u8         reserved_at_0[0x8];
2131  	u8         rq_num[0x18];
2132  };
2133  
2134  struct mlx5_ifc_mac_address_layout_bits {
2135  	u8         reserved_at_0[0x10];
2136  	u8         mac_addr_47_32[0x10];
2137  
2138  	u8         mac_addr_31_0[0x20];
2139  };
2140  
2141  struct mlx5_ifc_vlan_layout_bits {
2142  	u8         reserved_at_0[0x14];
2143  	u8         vlan[0x0c];
2144  
2145  	u8         reserved_at_20[0x20];
2146  };
2147  
2148  struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2149  	u8         reserved_at_0[0xa0];
2150  
2151  	u8         min_time_between_cnps[0x20];
2152  
2153  	u8         reserved_at_c0[0x12];
2154  	u8         cnp_dscp[0x6];
2155  	u8         reserved_at_d8[0x4];
2156  	u8         cnp_prio_mode[0x1];
2157  	u8         cnp_802p_prio[0x3];
2158  
2159  	u8         reserved_at_e0[0x720];
2160  };
2161  
2162  struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2163  	u8         reserved_at_0[0x60];
2164  
2165  	u8         reserved_at_60[0x4];
2166  	u8         clamp_tgt_rate[0x1];
2167  	u8         reserved_at_65[0x3];
2168  	u8         clamp_tgt_rate_after_time_inc[0x1];
2169  	u8         reserved_at_69[0x17];
2170  
2171  	u8         reserved_at_80[0x20];
2172  
2173  	u8         rpg_time_reset[0x20];
2174  
2175  	u8         rpg_byte_reset[0x20];
2176  
2177  	u8         rpg_threshold[0x20];
2178  
2179  	u8         rpg_max_rate[0x20];
2180  
2181  	u8         rpg_ai_rate[0x20];
2182  
2183  	u8         rpg_hai_rate[0x20];
2184  
2185  	u8         rpg_gd[0x20];
2186  
2187  	u8         rpg_min_dec_fac[0x20];
2188  
2189  	u8         rpg_min_rate[0x20];
2190  
2191  	u8         reserved_at_1c0[0xe0];
2192  
2193  	u8         rate_to_set_on_first_cnp[0x20];
2194  
2195  	u8         dce_tcp_g[0x20];
2196  
2197  	u8         dce_tcp_rtt[0x20];
2198  
2199  	u8         rate_reduce_monitor_period[0x20];
2200  
2201  	u8         reserved_at_320[0x20];
2202  
2203  	u8         initial_alpha_value[0x20];
2204  
2205  	u8         reserved_at_360[0x4a0];
2206  };
2207  
2208  struct mlx5_ifc_cong_control_r_roce_general_bits {
2209  	u8         reserved_at_0[0x80];
2210  
2211  	u8         reserved_at_80[0x10];
2212  	u8         rtt_resp_dscp_valid[0x1];
2213  	u8         reserved_at_91[0x9];
2214  	u8         rtt_resp_dscp[0x6];
2215  
2216  	u8         reserved_at_a0[0x760];
2217  };
2218  
2219  struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2220  	u8         reserved_at_0[0x80];
2221  
2222  	u8         rppp_max_rps[0x20];
2223  
2224  	u8         rpg_time_reset[0x20];
2225  
2226  	u8         rpg_byte_reset[0x20];
2227  
2228  	u8         rpg_threshold[0x20];
2229  
2230  	u8         rpg_max_rate[0x20];
2231  
2232  	u8         rpg_ai_rate[0x20];
2233  
2234  	u8         rpg_hai_rate[0x20];
2235  
2236  	u8         rpg_gd[0x20];
2237  
2238  	u8         rpg_min_dec_fac[0x20];
2239  
2240  	u8         rpg_min_rate[0x20];
2241  
2242  	u8         reserved_at_1c0[0x640];
2243  };
2244  
2245  enum {
2246  	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2247  	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2248  	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2249  };
2250  
2251  struct mlx5_ifc_resize_field_select_bits {
2252  	u8         resize_field_select[0x20];
2253  };
2254  
2255  struct mlx5_ifc_resource_dump_bits {
2256  	u8         more_dump[0x1];
2257  	u8         inline_dump[0x1];
2258  	u8         reserved_at_2[0xa];
2259  	u8         seq_num[0x4];
2260  	u8         segment_type[0x10];
2261  
2262  	u8         reserved_at_20[0x10];
2263  	u8         vhca_id[0x10];
2264  
2265  	u8         index1[0x20];
2266  
2267  	u8         index2[0x20];
2268  
2269  	u8         num_of_obj1[0x10];
2270  	u8         num_of_obj2[0x10];
2271  
2272  	u8         reserved_at_a0[0x20];
2273  
2274  	u8         device_opaque[0x40];
2275  
2276  	u8         mkey[0x20];
2277  
2278  	u8         size[0x20];
2279  
2280  	u8         address[0x40];
2281  
2282  	u8         inline_data[52][0x20];
2283  };
2284  
2285  struct mlx5_ifc_resource_dump_menu_record_bits {
2286  	u8         reserved_at_0[0x4];
2287  	u8         num_of_obj2_supports_active[0x1];
2288  	u8         num_of_obj2_supports_all[0x1];
2289  	u8         must_have_num_of_obj2[0x1];
2290  	u8         support_num_of_obj2[0x1];
2291  	u8         num_of_obj1_supports_active[0x1];
2292  	u8         num_of_obj1_supports_all[0x1];
2293  	u8         must_have_num_of_obj1[0x1];
2294  	u8         support_num_of_obj1[0x1];
2295  	u8         must_have_index2[0x1];
2296  	u8         support_index2[0x1];
2297  	u8         must_have_index1[0x1];
2298  	u8         support_index1[0x1];
2299  	u8         segment_type[0x10];
2300  
2301  	u8         segment_name[4][0x20];
2302  
2303  	u8         index1_name[4][0x20];
2304  
2305  	u8         index2_name[4][0x20];
2306  };
2307  
2308  struct mlx5_ifc_resource_dump_segment_header_bits {
2309  	u8         length_dw[0x10];
2310  	u8         segment_type[0x10];
2311  };
2312  
2313  struct mlx5_ifc_resource_dump_command_segment_bits {
2314  	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2315  
2316  	u8         segment_called[0x10];
2317  	u8         vhca_id[0x10];
2318  
2319  	u8         index1[0x20];
2320  
2321  	u8         index2[0x20];
2322  
2323  	u8         num_of_obj1[0x10];
2324  	u8         num_of_obj2[0x10];
2325  };
2326  
2327  struct mlx5_ifc_resource_dump_error_segment_bits {
2328  	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2329  
2330  	u8         reserved_at_20[0x10];
2331  	u8         syndrome_id[0x10];
2332  
2333  	u8         reserved_at_40[0x40];
2334  
2335  	u8         error[8][0x20];
2336  };
2337  
2338  struct mlx5_ifc_resource_dump_info_segment_bits {
2339  	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2340  
2341  	u8         reserved_at_20[0x18];
2342  	u8         dump_version[0x8];
2343  
2344  	u8         hw_version[0x20];
2345  
2346  	u8         fw_version[0x20];
2347  };
2348  
2349  struct mlx5_ifc_resource_dump_menu_segment_bits {
2350  	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2351  
2352  	u8         reserved_at_20[0x10];
2353  	u8         num_of_records[0x10];
2354  
2355  	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2356  };
2357  
2358  struct mlx5_ifc_resource_dump_resource_segment_bits {
2359  	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2360  
2361  	u8         reserved_at_20[0x20];
2362  
2363  	u8         index1[0x20];
2364  
2365  	u8         index2[0x20];
2366  
2367  	u8         payload[][0x20];
2368  };
2369  
2370  struct mlx5_ifc_resource_dump_terminate_segment_bits {
2371  	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2372  };
2373  
2374  struct mlx5_ifc_menu_resource_dump_response_bits {
2375  	struct mlx5_ifc_resource_dump_info_segment_bits info;
2376  	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2377  	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2378  	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2379  };
2380  
2381  enum {
2382  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2383  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2384  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2385  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2386  };
2387  
2388  struct mlx5_ifc_modify_field_select_bits {
2389  	u8         modify_field_select[0x20];
2390  };
2391  
2392  struct mlx5_ifc_field_select_r_roce_np_bits {
2393  	u8         field_select_r_roce_np[0x20];
2394  };
2395  
2396  struct mlx5_ifc_field_select_r_roce_rp_bits {
2397  	u8         field_select_r_roce_rp[0x20];
2398  };
2399  
2400  enum {
2401  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2402  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2403  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2404  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2405  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2406  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2407  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2408  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2409  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2410  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2411  };
2412  
2413  struct mlx5_ifc_field_select_802_1qau_rp_bits {
2414  	u8         field_select_8021qaurp[0x20];
2415  };
2416  
2417  struct mlx5_ifc_phys_layer_cntrs_bits {
2418  	u8         time_since_last_clear_high[0x20];
2419  
2420  	u8         time_since_last_clear_low[0x20];
2421  
2422  	u8         symbol_errors_high[0x20];
2423  
2424  	u8         symbol_errors_low[0x20];
2425  
2426  	u8         sync_headers_errors_high[0x20];
2427  
2428  	u8         sync_headers_errors_low[0x20];
2429  
2430  	u8         edpl_bip_errors_lane0_high[0x20];
2431  
2432  	u8         edpl_bip_errors_lane0_low[0x20];
2433  
2434  	u8         edpl_bip_errors_lane1_high[0x20];
2435  
2436  	u8         edpl_bip_errors_lane1_low[0x20];
2437  
2438  	u8         edpl_bip_errors_lane2_high[0x20];
2439  
2440  	u8         edpl_bip_errors_lane2_low[0x20];
2441  
2442  	u8         edpl_bip_errors_lane3_high[0x20];
2443  
2444  	u8         edpl_bip_errors_lane3_low[0x20];
2445  
2446  	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2447  
2448  	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2449  
2450  	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2451  
2452  	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2453  
2454  	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2455  
2456  	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2457  
2458  	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2459  
2460  	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2461  
2462  	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2463  
2464  	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2465  
2466  	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2467  
2468  	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2469  
2470  	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2471  
2472  	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2473  
2474  	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2475  
2476  	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2477  
2478  	u8         rs_fec_corrected_blocks_high[0x20];
2479  
2480  	u8         rs_fec_corrected_blocks_low[0x20];
2481  
2482  	u8         rs_fec_uncorrectable_blocks_high[0x20];
2483  
2484  	u8         rs_fec_uncorrectable_blocks_low[0x20];
2485  
2486  	u8         rs_fec_no_errors_blocks_high[0x20];
2487  
2488  	u8         rs_fec_no_errors_blocks_low[0x20];
2489  
2490  	u8         rs_fec_single_error_blocks_high[0x20];
2491  
2492  	u8         rs_fec_single_error_blocks_low[0x20];
2493  
2494  	u8         rs_fec_corrected_symbols_total_high[0x20];
2495  
2496  	u8         rs_fec_corrected_symbols_total_low[0x20];
2497  
2498  	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2499  
2500  	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2501  
2502  	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2503  
2504  	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2505  
2506  	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2507  
2508  	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2509  
2510  	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2511  
2512  	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2513  
2514  	u8         link_down_events[0x20];
2515  
2516  	u8         successful_recovery_events[0x20];
2517  
2518  	u8         reserved_at_640[0x180];
2519  };
2520  
2521  struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2522  	u8         time_since_last_clear_high[0x20];
2523  
2524  	u8         time_since_last_clear_low[0x20];
2525  
2526  	u8         phy_received_bits_high[0x20];
2527  
2528  	u8         phy_received_bits_low[0x20];
2529  
2530  	u8         phy_symbol_errors_high[0x20];
2531  
2532  	u8         phy_symbol_errors_low[0x20];
2533  
2534  	u8         phy_corrected_bits_high[0x20];
2535  
2536  	u8         phy_corrected_bits_low[0x20];
2537  
2538  	u8         phy_corrected_bits_lane0_high[0x20];
2539  
2540  	u8         phy_corrected_bits_lane0_low[0x20];
2541  
2542  	u8         phy_corrected_bits_lane1_high[0x20];
2543  
2544  	u8         phy_corrected_bits_lane1_low[0x20];
2545  
2546  	u8         phy_corrected_bits_lane2_high[0x20];
2547  
2548  	u8         phy_corrected_bits_lane2_low[0x20];
2549  
2550  	u8         phy_corrected_bits_lane3_high[0x20];
2551  
2552  	u8         phy_corrected_bits_lane3_low[0x20];
2553  
2554  	u8         reserved_at_200[0x5c0];
2555  };
2556  
2557  struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2558  	u8	   symbol_error_counter[0x10];
2559  
2560  	u8         link_error_recovery_counter[0x8];
2561  
2562  	u8         link_downed_counter[0x8];
2563  
2564  	u8         port_rcv_errors[0x10];
2565  
2566  	u8         port_rcv_remote_physical_errors[0x10];
2567  
2568  	u8         port_rcv_switch_relay_errors[0x10];
2569  
2570  	u8         port_xmit_discards[0x10];
2571  
2572  	u8         port_xmit_constraint_errors[0x8];
2573  
2574  	u8         port_rcv_constraint_errors[0x8];
2575  
2576  	u8         reserved_at_70[0x8];
2577  
2578  	u8         link_overrun_errors[0x8];
2579  
2580  	u8	   reserved_at_80[0x10];
2581  
2582  	u8         vl_15_dropped[0x10];
2583  
2584  	u8	   reserved_at_a0[0x80];
2585  
2586  	u8         port_xmit_wait[0x20];
2587  };
2588  
2589  struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2590  	u8         transmit_queue_high[0x20];
2591  
2592  	u8         transmit_queue_low[0x20];
2593  
2594  	u8         no_buffer_discard_uc_high[0x20];
2595  
2596  	u8         no_buffer_discard_uc_low[0x20];
2597  
2598  	u8         reserved_at_80[0x740];
2599  };
2600  
2601  struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2602  	u8         wred_discard_high[0x20];
2603  
2604  	u8         wred_discard_low[0x20];
2605  
2606  	u8         ecn_marked_tc_high[0x20];
2607  
2608  	u8         ecn_marked_tc_low[0x20];
2609  
2610  	u8         reserved_at_80[0x740];
2611  };
2612  
2613  struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2614  	u8         rx_octets_high[0x20];
2615  
2616  	u8         rx_octets_low[0x20];
2617  
2618  	u8         reserved_at_40[0xc0];
2619  
2620  	u8         rx_frames_high[0x20];
2621  
2622  	u8         rx_frames_low[0x20];
2623  
2624  	u8         tx_octets_high[0x20];
2625  
2626  	u8         tx_octets_low[0x20];
2627  
2628  	u8         reserved_at_180[0xc0];
2629  
2630  	u8         tx_frames_high[0x20];
2631  
2632  	u8         tx_frames_low[0x20];
2633  
2634  	u8         rx_pause_high[0x20];
2635  
2636  	u8         rx_pause_low[0x20];
2637  
2638  	u8         rx_pause_duration_high[0x20];
2639  
2640  	u8         rx_pause_duration_low[0x20];
2641  
2642  	u8         tx_pause_high[0x20];
2643  
2644  	u8         tx_pause_low[0x20];
2645  
2646  	u8         tx_pause_duration_high[0x20];
2647  
2648  	u8         tx_pause_duration_low[0x20];
2649  
2650  	u8         rx_pause_transition_high[0x20];
2651  
2652  	u8         rx_pause_transition_low[0x20];
2653  
2654  	u8         rx_discards_high[0x20];
2655  
2656  	u8         rx_discards_low[0x20];
2657  
2658  	u8         device_stall_minor_watermark_cnt_high[0x20];
2659  
2660  	u8         device_stall_minor_watermark_cnt_low[0x20];
2661  
2662  	u8         device_stall_critical_watermark_cnt_high[0x20];
2663  
2664  	u8         device_stall_critical_watermark_cnt_low[0x20];
2665  
2666  	u8         reserved_at_480[0x340];
2667  };
2668  
2669  struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2670  	u8         port_transmit_wait_high[0x20];
2671  
2672  	u8         port_transmit_wait_low[0x20];
2673  
2674  	u8         reserved_at_40[0x100];
2675  
2676  	u8         rx_buffer_almost_full_high[0x20];
2677  
2678  	u8         rx_buffer_almost_full_low[0x20];
2679  
2680  	u8         rx_buffer_full_high[0x20];
2681  
2682  	u8         rx_buffer_full_low[0x20];
2683  
2684  	u8         rx_icrc_encapsulated_high[0x20];
2685  
2686  	u8         rx_icrc_encapsulated_low[0x20];
2687  
2688  	u8         reserved_at_200[0x5c0];
2689  };
2690  
2691  struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2692  	u8         dot3stats_alignment_errors_high[0x20];
2693  
2694  	u8         dot3stats_alignment_errors_low[0x20];
2695  
2696  	u8         dot3stats_fcs_errors_high[0x20];
2697  
2698  	u8         dot3stats_fcs_errors_low[0x20];
2699  
2700  	u8         dot3stats_single_collision_frames_high[0x20];
2701  
2702  	u8         dot3stats_single_collision_frames_low[0x20];
2703  
2704  	u8         dot3stats_multiple_collision_frames_high[0x20];
2705  
2706  	u8         dot3stats_multiple_collision_frames_low[0x20];
2707  
2708  	u8         dot3stats_sqe_test_errors_high[0x20];
2709  
2710  	u8         dot3stats_sqe_test_errors_low[0x20];
2711  
2712  	u8         dot3stats_deferred_transmissions_high[0x20];
2713  
2714  	u8         dot3stats_deferred_transmissions_low[0x20];
2715  
2716  	u8         dot3stats_late_collisions_high[0x20];
2717  
2718  	u8         dot3stats_late_collisions_low[0x20];
2719  
2720  	u8         dot3stats_excessive_collisions_high[0x20];
2721  
2722  	u8         dot3stats_excessive_collisions_low[0x20];
2723  
2724  	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2725  
2726  	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2727  
2728  	u8         dot3stats_carrier_sense_errors_high[0x20];
2729  
2730  	u8         dot3stats_carrier_sense_errors_low[0x20];
2731  
2732  	u8         dot3stats_frame_too_longs_high[0x20];
2733  
2734  	u8         dot3stats_frame_too_longs_low[0x20];
2735  
2736  	u8         dot3stats_internal_mac_receive_errors_high[0x20];
2737  
2738  	u8         dot3stats_internal_mac_receive_errors_low[0x20];
2739  
2740  	u8         dot3stats_symbol_errors_high[0x20];
2741  
2742  	u8         dot3stats_symbol_errors_low[0x20];
2743  
2744  	u8         dot3control_in_unknown_opcodes_high[0x20];
2745  
2746  	u8         dot3control_in_unknown_opcodes_low[0x20];
2747  
2748  	u8         dot3in_pause_frames_high[0x20];
2749  
2750  	u8         dot3in_pause_frames_low[0x20];
2751  
2752  	u8         dot3out_pause_frames_high[0x20];
2753  
2754  	u8         dot3out_pause_frames_low[0x20];
2755  
2756  	u8         reserved_at_400[0x3c0];
2757  };
2758  
2759  struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2760  	u8         ether_stats_drop_events_high[0x20];
2761  
2762  	u8         ether_stats_drop_events_low[0x20];
2763  
2764  	u8         ether_stats_octets_high[0x20];
2765  
2766  	u8         ether_stats_octets_low[0x20];
2767  
2768  	u8         ether_stats_pkts_high[0x20];
2769  
2770  	u8         ether_stats_pkts_low[0x20];
2771  
2772  	u8         ether_stats_broadcast_pkts_high[0x20];
2773  
2774  	u8         ether_stats_broadcast_pkts_low[0x20];
2775  
2776  	u8         ether_stats_multicast_pkts_high[0x20];
2777  
2778  	u8         ether_stats_multicast_pkts_low[0x20];
2779  
2780  	u8         ether_stats_crc_align_errors_high[0x20];
2781  
2782  	u8         ether_stats_crc_align_errors_low[0x20];
2783  
2784  	u8         ether_stats_undersize_pkts_high[0x20];
2785  
2786  	u8         ether_stats_undersize_pkts_low[0x20];
2787  
2788  	u8         ether_stats_oversize_pkts_high[0x20];
2789  
2790  	u8         ether_stats_oversize_pkts_low[0x20];
2791  
2792  	u8         ether_stats_fragments_high[0x20];
2793  
2794  	u8         ether_stats_fragments_low[0x20];
2795  
2796  	u8         ether_stats_jabbers_high[0x20];
2797  
2798  	u8         ether_stats_jabbers_low[0x20];
2799  
2800  	u8         ether_stats_collisions_high[0x20];
2801  
2802  	u8         ether_stats_collisions_low[0x20];
2803  
2804  	u8         ether_stats_pkts64octets_high[0x20];
2805  
2806  	u8         ether_stats_pkts64octets_low[0x20];
2807  
2808  	u8         ether_stats_pkts65to127octets_high[0x20];
2809  
2810  	u8         ether_stats_pkts65to127octets_low[0x20];
2811  
2812  	u8         ether_stats_pkts128to255octets_high[0x20];
2813  
2814  	u8         ether_stats_pkts128to255octets_low[0x20];
2815  
2816  	u8         ether_stats_pkts256to511octets_high[0x20];
2817  
2818  	u8         ether_stats_pkts256to511octets_low[0x20];
2819  
2820  	u8         ether_stats_pkts512to1023octets_high[0x20];
2821  
2822  	u8         ether_stats_pkts512to1023octets_low[0x20];
2823  
2824  	u8         ether_stats_pkts1024to1518octets_high[0x20];
2825  
2826  	u8         ether_stats_pkts1024to1518octets_low[0x20];
2827  
2828  	u8         ether_stats_pkts1519to2047octets_high[0x20];
2829  
2830  	u8         ether_stats_pkts1519to2047octets_low[0x20];
2831  
2832  	u8         ether_stats_pkts2048to4095octets_high[0x20];
2833  
2834  	u8         ether_stats_pkts2048to4095octets_low[0x20];
2835  
2836  	u8         ether_stats_pkts4096to8191octets_high[0x20];
2837  
2838  	u8         ether_stats_pkts4096to8191octets_low[0x20];
2839  
2840  	u8         ether_stats_pkts8192to10239octets_high[0x20];
2841  
2842  	u8         ether_stats_pkts8192to10239octets_low[0x20];
2843  
2844  	u8         reserved_at_540[0x280];
2845  };
2846  
2847  struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2848  	u8         if_in_octets_high[0x20];
2849  
2850  	u8         if_in_octets_low[0x20];
2851  
2852  	u8         if_in_ucast_pkts_high[0x20];
2853  
2854  	u8         if_in_ucast_pkts_low[0x20];
2855  
2856  	u8         if_in_discards_high[0x20];
2857  
2858  	u8         if_in_discards_low[0x20];
2859  
2860  	u8         if_in_errors_high[0x20];
2861  
2862  	u8         if_in_errors_low[0x20];
2863  
2864  	u8         if_in_unknown_protos_high[0x20];
2865  
2866  	u8         if_in_unknown_protos_low[0x20];
2867  
2868  	u8         if_out_octets_high[0x20];
2869  
2870  	u8         if_out_octets_low[0x20];
2871  
2872  	u8         if_out_ucast_pkts_high[0x20];
2873  
2874  	u8         if_out_ucast_pkts_low[0x20];
2875  
2876  	u8         if_out_discards_high[0x20];
2877  
2878  	u8         if_out_discards_low[0x20];
2879  
2880  	u8         if_out_errors_high[0x20];
2881  
2882  	u8         if_out_errors_low[0x20];
2883  
2884  	u8         if_in_multicast_pkts_high[0x20];
2885  
2886  	u8         if_in_multicast_pkts_low[0x20];
2887  
2888  	u8         if_in_broadcast_pkts_high[0x20];
2889  
2890  	u8         if_in_broadcast_pkts_low[0x20];
2891  
2892  	u8         if_out_multicast_pkts_high[0x20];
2893  
2894  	u8         if_out_multicast_pkts_low[0x20];
2895  
2896  	u8         if_out_broadcast_pkts_high[0x20];
2897  
2898  	u8         if_out_broadcast_pkts_low[0x20];
2899  
2900  	u8         reserved_at_340[0x480];
2901  };
2902  
2903  struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2904  	u8         a_frames_transmitted_ok_high[0x20];
2905  
2906  	u8         a_frames_transmitted_ok_low[0x20];
2907  
2908  	u8         a_frames_received_ok_high[0x20];
2909  
2910  	u8         a_frames_received_ok_low[0x20];
2911  
2912  	u8         a_frame_check_sequence_errors_high[0x20];
2913  
2914  	u8         a_frame_check_sequence_errors_low[0x20];
2915  
2916  	u8         a_alignment_errors_high[0x20];
2917  
2918  	u8         a_alignment_errors_low[0x20];
2919  
2920  	u8         a_octets_transmitted_ok_high[0x20];
2921  
2922  	u8         a_octets_transmitted_ok_low[0x20];
2923  
2924  	u8         a_octets_received_ok_high[0x20];
2925  
2926  	u8         a_octets_received_ok_low[0x20];
2927  
2928  	u8         a_multicast_frames_xmitted_ok_high[0x20];
2929  
2930  	u8         a_multicast_frames_xmitted_ok_low[0x20];
2931  
2932  	u8         a_broadcast_frames_xmitted_ok_high[0x20];
2933  
2934  	u8         a_broadcast_frames_xmitted_ok_low[0x20];
2935  
2936  	u8         a_multicast_frames_received_ok_high[0x20];
2937  
2938  	u8         a_multicast_frames_received_ok_low[0x20];
2939  
2940  	u8         a_broadcast_frames_received_ok_high[0x20];
2941  
2942  	u8         a_broadcast_frames_received_ok_low[0x20];
2943  
2944  	u8         a_in_range_length_errors_high[0x20];
2945  
2946  	u8         a_in_range_length_errors_low[0x20];
2947  
2948  	u8         a_out_of_range_length_field_high[0x20];
2949  
2950  	u8         a_out_of_range_length_field_low[0x20];
2951  
2952  	u8         a_frame_too_long_errors_high[0x20];
2953  
2954  	u8         a_frame_too_long_errors_low[0x20];
2955  
2956  	u8         a_symbol_error_during_carrier_high[0x20];
2957  
2958  	u8         a_symbol_error_during_carrier_low[0x20];
2959  
2960  	u8         a_mac_control_frames_transmitted_high[0x20];
2961  
2962  	u8         a_mac_control_frames_transmitted_low[0x20];
2963  
2964  	u8         a_mac_control_frames_received_high[0x20];
2965  
2966  	u8         a_mac_control_frames_received_low[0x20];
2967  
2968  	u8         a_unsupported_opcodes_received_high[0x20];
2969  
2970  	u8         a_unsupported_opcodes_received_low[0x20];
2971  
2972  	u8         a_pause_mac_ctrl_frames_received_high[0x20];
2973  
2974  	u8         a_pause_mac_ctrl_frames_received_low[0x20];
2975  
2976  	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2977  
2978  	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2979  
2980  	u8         reserved_at_4c0[0x300];
2981  };
2982  
2983  struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2984  	u8         life_time_counter_high[0x20];
2985  
2986  	u8         life_time_counter_low[0x20];
2987  
2988  	u8         rx_errors[0x20];
2989  
2990  	u8         tx_errors[0x20];
2991  
2992  	u8         l0_to_recovery_eieos[0x20];
2993  
2994  	u8         l0_to_recovery_ts[0x20];
2995  
2996  	u8         l0_to_recovery_framing[0x20];
2997  
2998  	u8         l0_to_recovery_retrain[0x20];
2999  
3000  	u8         crc_error_dllp[0x20];
3001  
3002  	u8         crc_error_tlp[0x20];
3003  
3004  	u8         tx_overflow_buffer_pkt_high[0x20];
3005  
3006  	u8         tx_overflow_buffer_pkt_low[0x20];
3007  
3008  	u8         outbound_stalled_reads[0x20];
3009  
3010  	u8         outbound_stalled_writes[0x20];
3011  
3012  	u8         outbound_stalled_reads_events[0x20];
3013  
3014  	u8         outbound_stalled_writes_events[0x20];
3015  
3016  	u8         reserved_at_200[0x5c0];
3017  };
3018  
3019  struct mlx5_ifc_cmd_inter_comp_event_bits {
3020  	u8         command_completion_vector[0x20];
3021  
3022  	u8         reserved_at_20[0xc0];
3023  };
3024  
3025  struct mlx5_ifc_stall_vl_event_bits {
3026  	u8         reserved_at_0[0x18];
3027  	u8         port_num[0x1];
3028  	u8         reserved_at_19[0x3];
3029  	u8         vl[0x4];
3030  
3031  	u8         reserved_at_20[0xa0];
3032  };
3033  
3034  struct mlx5_ifc_db_bf_congestion_event_bits {
3035  	u8         event_subtype[0x8];
3036  	u8         reserved_at_8[0x8];
3037  	u8         congestion_level[0x8];
3038  	u8         reserved_at_18[0x8];
3039  
3040  	u8         reserved_at_20[0xa0];
3041  };
3042  
3043  struct mlx5_ifc_gpio_event_bits {
3044  	u8         reserved_at_0[0x60];
3045  
3046  	u8         gpio_event_hi[0x20];
3047  
3048  	u8         gpio_event_lo[0x20];
3049  
3050  	u8         reserved_at_a0[0x40];
3051  };
3052  
3053  struct mlx5_ifc_port_state_change_event_bits {
3054  	u8         reserved_at_0[0x40];
3055  
3056  	u8         port_num[0x4];
3057  	u8         reserved_at_44[0x1c];
3058  
3059  	u8         reserved_at_60[0x80];
3060  };
3061  
3062  struct mlx5_ifc_dropped_packet_logged_bits {
3063  	u8         reserved_at_0[0xe0];
3064  };
3065  
3066  struct mlx5_ifc_default_timeout_bits {
3067  	u8         to_multiplier[0x3];
3068  	u8         reserved_at_3[0x9];
3069  	u8         to_value[0x14];
3070  };
3071  
3072  struct mlx5_ifc_dtor_reg_bits {
3073  	u8         reserved_at_0[0x20];
3074  
3075  	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3076  
3077  	u8         reserved_at_40[0x60];
3078  
3079  	struct mlx5_ifc_default_timeout_bits health_poll_to;
3080  
3081  	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3082  
3083  	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3084  
3085  	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3086  
3087  	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3088  
3089  	struct mlx5_ifc_default_timeout_bits tear_down_to;
3090  
3091  	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3092  
3093  	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3094  
3095  	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3096  
3097  	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3098  
3099  	u8         reserved_at_1c0[0x20];
3100  };
3101  
3102  enum {
3103  	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3104  	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3105  };
3106  
3107  struct mlx5_ifc_cq_error_bits {
3108  	u8         reserved_at_0[0x8];
3109  	u8         cqn[0x18];
3110  
3111  	u8         reserved_at_20[0x20];
3112  
3113  	u8         reserved_at_40[0x18];
3114  	u8         syndrome[0x8];
3115  
3116  	u8         reserved_at_60[0x80];
3117  };
3118  
3119  struct mlx5_ifc_rdma_page_fault_event_bits {
3120  	u8         bytes_committed[0x20];
3121  
3122  	u8         r_key[0x20];
3123  
3124  	u8         reserved_at_40[0x10];
3125  	u8         packet_len[0x10];
3126  
3127  	u8         rdma_op_len[0x20];
3128  
3129  	u8         rdma_va[0x40];
3130  
3131  	u8         reserved_at_c0[0x5];
3132  	u8         rdma[0x1];
3133  	u8         write[0x1];
3134  	u8         requestor[0x1];
3135  	u8         qp_number[0x18];
3136  };
3137  
3138  struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3139  	u8         bytes_committed[0x20];
3140  
3141  	u8         reserved_at_20[0x10];
3142  	u8         wqe_index[0x10];
3143  
3144  	u8         reserved_at_40[0x10];
3145  	u8         len[0x10];
3146  
3147  	u8         reserved_at_60[0x60];
3148  
3149  	u8         reserved_at_c0[0x5];
3150  	u8         rdma[0x1];
3151  	u8         write_read[0x1];
3152  	u8         requestor[0x1];
3153  	u8         qpn[0x18];
3154  };
3155  
3156  struct mlx5_ifc_qp_events_bits {
3157  	u8         reserved_at_0[0xa0];
3158  
3159  	u8         type[0x8];
3160  	u8         reserved_at_a8[0x18];
3161  
3162  	u8         reserved_at_c0[0x8];
3163  	u8         qpn_rqn_sqn[0x18];
3164  };
3165  
3166  struct mlx5_ifc_dct_events_bits {
3167  	u8         reserved_at_0[0xc0];
3168  
3169  	u8         reserved_at_c0[0x8];
3170  	u8         dct_number[0x18];
3171  };
3172  
3173  struct mlx5_ifc_comp_event_bits {
3174  	u8         reserved_at_0[0xc0];
3175  
3176  	u8         reserved_at_c0[0x8];
3177  	u8         cq_number[0x18];
3178  };
3179  
3180  enum {
3181  	MLX5_QPC_STATE_RST        = 0x0,
3182  	MLX5_QPC_STATE_INIT       = 0x1,
3183  	MLX5_QPC_STATE_RTR        = 0x2,
3184  	MLX5_QPC_STATE_RTS        = 0x3,
3185  	MLX5_QPC_STATE_SQER       = 0x4,
3186  	MLX5_QPC_STATE_ERR        = 0x6,
3187  	MLX5_QPC_STATE_SQD        = 0x7,
3188  	MLX5_QPC_STATE_SUSPENDED  = 0x9,
3189  };
3190  
3191  enum {
3192  	MLX5_QPC_ST_RC            = 0x0,
3193  	MLX5_QPC_ST_UC            = 0x1,
3194  	MLX5_QPC_ST_UD            = 0x2,
3195  	MLX5_QPC_ST_XRC           = 0x3,
3196  	MLX5_QPC_ST_DCI           = 0x5,
3197  	MLX5_QPC_ST_QP0           = 0x7,
3198  	MLX5_QPC_ST_QP1           = 0x8,
3199  	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3200  	MLX5_QPC_ST_REG_UMR       = 0xc,
3201  };
3202  
3203  enum {
3204  	MLX5_QPC_PM_STATE_ARMED     = 0x0,
3205  	MLX5_QPC_PM_STATE_REARM     = 0x1,
3206  	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3207  	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3208  };
3209  
3210  enum {
3211  	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3212  };
3213  
3214  enum {
3215  	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3216  	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3217  };
3218  
3219  enum {
3220  	MLX5_QPC_MTU_256_BYTES        = 0x1,
3221  	MLX5_QPC_MTU_512_BYTES        = 0x2,
3222  	MLX5_QPC_MTU_1K_BYTES         = 0x3,
3223  	MLX5_QPC_MTU_2K_BYTES         = 0x4,
3224  	MLX5_QPC_MTU_4K_BYTES         = 0x5,
3225  	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3226  };
3227  
3228  enum {
3229  	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3230  	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3231  	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3232  	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3233  	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3234  	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3235  	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3236  	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3237  };
3238  
3239  enum {
3240  	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3241  	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3242  	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3243  };
3244  
3245  enum {
3246  	MLX5_QPC_CS_RES_DISABLE    = 0x0,
3247  	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3248  	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3249  };
3250  
3251  enum {
3252  	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3253  	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3254  	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3255  };
3256  
3257  struct mlx5_ifc_qpc_bits {
3258  	u8         state[0x4];
3259  	u8         lag_tx_port_affinity[0x4];
3260  	u8         st[0x8];
3261  	u8         reserved_at_10[0x2];
3262  	u8	   isolate_vl_tc[0x1];
3263  	u8         pm_state[0x2];
3264  	u8         reserved_at_15[0x1];
3265  	u8         req_e2e_credit_mode[0x2];
3266  	u8         offload_type[0x4];
3267  	u8         end_padding_mode[0x2];
3268  	u8         reserved_at_1e[0x2];
3269  
3270  	u8         wq_signature[0x1];
3271  	u8         block_lb_mc[0x1];
3272  	u8         atomic_like_write_en[0x1];
3273  	u8         latency_sensitive[0x1];
3274  	u8         reserved_at_24[0x1];
3275  	u8         drain_sigerr[0x1];
3276  	u8         reserved_at_26[0x2];
3277  	u8         pd[0x18];
3278  
3279  	u8         mtu[0x3];
3280  	u8         log_msg_max[0x5];
3281  	u8         reserved_at_48[0x1];
3282  	u8         log_rq_size[0x4];
3283  	u8         log_rq_stride[0x3];
3284  	u8         no_sq[0x1];
3285  	u8         log_sq_size[0x4];
3286  	u8         reserved_at_55[0x1];
3287  	u8	   retry_mode[0x2];
3288  	u8	   ts_format[0x2];
3289  	u8         reserved_at_5a[0x1];
3290  	u8         rlky[0x1];
3291  	u8         ulp_stateless_offload_mode[0x4];
3292  
3293  	u8         counter_set_id[0x8];
3294  	u8         uar_page[0x18];
3295  
3296  	u8         reserved_at_80[0x8];
3297  	u8         user_index[0x18];
3298  
3299  	u8         reserved_at_a0[0x3];
3300  	u8         log_page_size[0x5];
3301  	u8         remote_qpn[0x18];
3302  
3303  	struct mlx5_ifc_ads_bits primary_address_path;
3304  
3305  	struct mlx5_ifc_ads_bits secondary_address_path;
3306  
3307  	u8         log_ack_req_freq[0x4];
3308  	u8         reserved_at_384[0x4];
3309  	u8         log_sra_max[0x3];
3310  	u8         reserved_at_38b[0x2];
3311  	u8         retry_count[0x3];
3312  	u8         rnr_retry[0x3];
3313  	u8         reserved_at_393[0x1];
3314  	u8         fre[0x1];
3315  	u8         cur_rnr_retry[0x3];
3316  	u8         cur_retry_count[0x3];
3317  	u8         reserved_at_39b[0x5];
3318  
3319  	u8         reserved_at_3a0[0x20];
3320  
3321  	u8         reserved_at_3c0[0x8];
3322  	u8         next_send_psn[0x18];
3323  
3324  	u8         reserved_at_3e0[0x3];
3325  	u8	   log_num_dci_stream_channels[0x5];
3326  	u8         cqn_snd[0x18];
3327  
3328  	u8         reserved_at_400[0x3];
3329  	u8	   log_num_dci_errored_streams[0x5];
3330  	u8         deth_sqpn[0x18];
3331  
3332  	u8         reserved_at_420[0x20];
3333  
3334  	u8         reserved_at_440[0x8];
3335  	u8         last_acked_psn[0x18];
3336  
3337  	u8         reserved_at_460[0x8];
3338  	u8         ssn[0x18];
3339  
3340  	u8         reserved_at_480[0x8];
3341  	u8         log_rra_max[0x3];
3342  	u8         reserved_at_48b[0x1];
3343  	u8         atomic_mode[0x4];
3344  	u8         rre[0x1];
3345  	u8         rwe[0x1];
3346  	u8         rae[0x1];
3347  	u8         reserved_at_493[0x1];
3348  	u8         page_offset[0x6];
3349  	u8         reserved_at_49a[0x3];
3350  	u8         cd_slave_receive[0x1];
3351  	u8         cd_slave_send[0x1];
3352  	u8         cd_master[0x1];
3353  
3354  	u8         reserved_at_4a0[0x3];
3355  	u8         min_rnr_nak[0x5];
3356  	u8         next_rcv_psn[0x18];
3357  
3358  	u8         reserved_at_4c0[0x8];
3359  	u8         xrcd[0x18];
3360  
3361  	u8         reserved_at_4e0[0x8];
3362  	u8         cqn_rcv[0x18];
3363  
3364  	u8         dbr_addr[0x40];
3365  
3366  	u8         q_key[0x20];
3367  
3368  	u8         reserved_at_560[0x5];
3369  	u8         rq_type[0x3];
3370  	u8         srqn_rmpn_xrqn[0x18];
3371  
3372  	u8         reserved_at_580[0x8];
3373  	u8         rmsn[0x18];
3374  
3375  	u8         hw_sq_wqebb_counter[0x10];
3376  	u8         sw_sq_wqebb_counter[0x10];
3377  
3378  	u8         hw_rq_counter[0x20];
3379  
3380  	u8         sw_rq_counter[0x20];
3381  
3382  	u8         reserved_at_600[0x20];
3383  
3384  	u8         reserved_at_620[0xf];
3385  	u8         cgs[0x1];
3386  	u8         cs_req[0x8];
3387  	u8         cs_res[0x8];
3388  
3389  	u8         dc_access_key[0x40];
3390  
3391  	u8         reserved_at_680[0x3];
3392  	u8         dbr_umem_valid[0x1];
3393  
3394  	u8         reserved_at_684[0xbc];
3395  };
3396  
3397  struct mlx5_ifc_roce_addr_layout_bits {
3398  	u8         source_l3_address[16][0x8];
3399  
3400  	u8         reserved_at_80[0x3];
3401  	u8         vlan_valid[0x1];
3402  	u8         vlan_id[0xc];
3403  	u8         source_mac_47_32[0x10];
3404  
3405  	u8         source_mac_31_0[0x20];
3406  
3407  	u8         reserved_at_c0[0x14];
3408  	u8         roce_l3_type[0x4];
3409  	u8         roce_version[0x8];
3410  
3411  	u8         reserved_at_e0[0x20];
3412  };
3413  
3414  struct mlx5_ifc_crypto_cap_bits {
3415  	u8    reserved_at_0[0x3];
3416  	u8    synchronize_dek[0x1];
3417  	u8    int_kek_manual[0x1];
3418  	u8    int_kek_auto[0x1];
3419  	u8    reserved_at_6[0x1a];
3420  
3421  	u8    reserved_at_20[0x3];
3422  	u8    log_dek_max_alloc[0x5];
3423  	u8    reserved_at_28[0x3];
3424  	u8    log_max_num_deks[0x5];
3425  	u8    reserved_at_30[0x10];
3426  
3427  	u8    reserved_at_40[0x20];
3428  
3429  	u8    reserved_at_60[0x3];
3430  	u8    log_dek_granularity[0x5];
3431  	u8    reserved_at_68[0x3];
3432  	u8    log_max_num_int_kek[0x5];
3433  	u8    sw_wrapped_dek[0x10];
3434  
3435  	u8    reserved_at_80[0x780];
3436  };
3437  
3438  union mlx5_ifc_hca_cap_union_bits {
3439  	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3440  	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3441  	struct mlx5_ifc_odp_cap_bits odp_cap;
3442  	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3443  	struct mlx5_ifc_roce_cap_bits roce_cap;
3444  	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3445  	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3446  	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3447  	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3448  	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3449  	struct mlx5_ifc_qos_cap_bits qos_cap;
3450  	struct mlx5_ifc_debug_cap_bits debug_cap;
3451  	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3452  	struct mlx5_ifc_tls_cap_bits tls_cap;
3453  	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3454  	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3455  	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3456  	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3457  	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3458  	u8         reserved_at_0[0x8000];
3459  };
3460  
3461  enum {
3462  	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3463  	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3464  	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3465  	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3466  	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3467  	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3468  	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3469  	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3470  	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3471  	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3472  	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3473  	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3474  	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3475  	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3476  };
3477  
3478  enum {
3479  	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3480  	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3481  	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3482  };
3483  
3484  enum {
3485  	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3486  	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3487  };
3488  
3489  struct mlx5_ifc_vlan_bits {
3490  	u8         ethtype[0x10];
3491  	u8         prio[0x3];
3492  	u8         cfi[0x1];
3493  	u8         vid[0xc];
3494  };
3495  
3496  enum {
3497  	MLX5_FLOW_METER_COLOR_RED	= 0x0,
3498  	MLX5_FLOW_METER_COLOR_YELLOW	= 0x1,
3499  	MLX5_FLOW_METER_COLOR_GREEN	= 0x2,
3500  	MLX5_FLOW_METER_COLOR_UNDEFINED	= 0x3,
3501  };
3502  
3503  enum {
3504  	MLX5_EXE_ASO_FLOW_METER		= 0x2,
3505  };
3506  
3507  struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3508  	u8        return_reg_id[0x4];
3509  	u8        aso_type[0x4];
3510  	u8        reserved_at_8[0x14];
3511  	u8        action[0x1];
3512  	u8        init_color[0x2];
3513  	u8        meter_id[0x1];
3514  };
3515  
3516  union mlx5_ifc_exe_aso_ctrl {
3517  	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3518  };
3519  
3520  struct mlx5_ifc_execute_aso_bits {
3521  	u8        valid[0x1];
3522  	u8        reserved_at_1[0x7];
3523  	u8        aso_object_id[0x18];
3524  
3525  	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3526  };
3527  
3528  struct mlx5_ifc_flow_context_bits {
3529  	struct mlx5_ifc_vlan_bits push_vlan;
3530  
3531  	u8         group_id[0x20];
3532  
3533  	u8         reserved_at_40[0x8];
3534  	u8         flow_tag[0x18];
3535  
3536  	u8         reserved_at_60[0x10];
3537  	u8         action[0x10];
3538  
3539  	u8         extended_destination[0x1];
3540  	u8         uplink_hairpin_en[0x1];
3541  	u8         flow_source[0x2];
3542  	u8         encrypt_decrypt_type[0x4];
3543  	u8         destination_list_size[0x18];
3544  
3545  	u8         reserved_at_a0[0x8];
3546  	u8         flow_counter_list_size[0x18];
3547  
3548  	u8         packet_reformat_id[0x20];
3549  
3550  	u8         modify_header_id[0x20];
3551  
3552  	struct mlx5_ifc_vlan_bits push_vlan_2;
3553  
3554  	u8         encrypt_decrypt_obj_id[0x20];
3555  	u8         reserved_at_140[0xc0];
3556  
3557  	struct mlx5_ifc_fte_match_param_bits match_value;
3558  
3559  	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3560  
3561  	u8         reserved_at_1300[0x500];
3562  
3563  	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3564  };
3565  
3566  enum {
3567  	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3568  	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3569  };
3570  
3571  struct mlx5_ifc_xrc_srqc_bits {
3572  	u8         state[0x4];
3573  	u8         log_xrc_srq_size[0x4];
3574  	u8         reserved_at_8[0x18];
3575  
3576  	u8         wq_signature[0x1];
3577  	u8         cont_srq[0x1];
3578  	u8         reserved_at_22[0x1];
3579  	u8         rlky[0x1];
3580  	u8         basic_cyclic_rcv_wqe[0x1];
3581  	u8         log_rq_stride[0x3];
3582  	u8         xrcd[0x18];
3583  
3584  	u8         page_offset[0x6];
3585  	u8         reserved_at_46[0x1];
3586  	u8         dbr_umem_valid[0x1];
3587  	u8         cqn[0x18];
3588  
3589  	u8         reserved_at_60[0x20];
3590  
3591  	u8         user_index_equal_xrc_srqn[0x1];
3592  	u8         reserved_at_81[0x1];
3593  	u8         log_page_size[0x6];
3594  	u8         user_index[0x18];
3595  
3596  	u8         reserved_at_a0[0x20];
3597  
3598  	u8         reserved_at_c0[0x8];
3599  	u8         pd[0x18];
3600  
3601  	u8         lwm[0x10];
3602  	u8         wqe_cnt[0x10];
3603  
3604  	u8         reserved_at_100[0x40];
3605  
3606  	u8         db_record_addr_h[0x20];
3607  
3608  	u8         db_record_addr_l[0x1e];
3609  	u8         reserved_at_17e[0x2];
3610  
3611  	u8         reserved_at_180[0x80];
3612  };
3613  
3614  struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3615  	u8         counter_error_queues[0x20];
3616  
3617  	u8         total_error_queues[0x20];
3618  
3619  	u8         send_queue_priority_update_flow[0x20];
3620  
3621  	u8         reserved_at_60[0x20];
3622  
3623  	u8         nic_receive_steering_discard[0x40];
3624  
3625  	u8         receive_discard_vport_down[0x40];
3626  
3627  	u8         transmit_discard_vport_down[0x40];
3628  
3629  	u8         async_eq_overrun[0x20];
3630  
3631  	u8         comp_eq_overrun[0x20];
3632  
3633  	u8         reserved_at_180[0x20];
3634  
3635  	u8         invalid_command[0x20];
3636  
3637  	u8         quota_exceeded_command[0x20];
3638  
3639  	u8         internal_rq_out_of_buffer[0x20];
3640  
3641  	u8         cq_overrun[0x20];
3642  
3643  	u8         eth_wqe_too_small[0x20];
3644  
3645  	u8         reserved_at_220[0xc0];
3646  
3647  	u8         generated_pkt_steering_fail[0x40];
3648  
3649  	u8         handled_pkt_steering_fail[0x40];
3650  
3651  	u8         reserved_at_360[0xc80];
3652  };
3653  
3654  struct mlx5_ifc_traffic_counter_bits {
3655  	u8         packets[0x40];
3656  
3657  	u8         octets[0x40];
3658  };
3659  
3660  struct mlx5_ifc_tisc_bits {
3661  	u8         strict_lag_tx_port_affinity[0x1];
3662  	u8         tls_en[0x1];
3663  	u8         reserved_at_2[0x2];
3664  	u8         lag_tx_port_affinity[0x04];
3665  
3666  	u8         reserved_at_8[0x4];
3667  	u8         prio[0x4];
3668  	u8         reserved_at_10[0x10];
3669  
3670  	u8         reserved_at_20[0x100];
3671  
3672  	u8         reserved_at_120[0x8];
3673  	u8         transport_domain[0x18];
3674  
3675  	u8         reserved_at_140[0x8];
3676  	u8         underlay_qpn[0x18];
3677  
3678  	u8         reserved_at_160[0x8];
3679  	u8         pd[0x18];
3680  
3681  	u8         reserved_at_180[0x380];
3682  };
3683  
3684  enum {
3685  	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3686  	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3687  };
3688  
3689  enum {
3690  	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3691  	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3692  };
3693  
3694  enum {
3695  	MLX5_RX_HASH_FN_NONE           = 0x0,
3696  	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3697  	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3698  };
3699  
3700  enum {
3701  	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3702  	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3703  };
3704  
3705  struct mlx5_ifc_tirc_bits {
3706  	u8         reserved_at_0[0x20];
3707  
3708  	u8         disp_type[0x4];
3709  	u8         tls_en[0x1];
3710  	u8         reserved_at_25[0x1b];
3711  
3712  	u8         reserved_at_40[0x40];
3713  
3714  	u8         reserved_at_80[0x4];
3715  	u8         lro_timeout_period_usecs[0x10];
3716  	u8         packet_merge_mask[0x4];
3717  	u8         lro_max_ip_payload_size[0x8];
3718  
3719  	u8         reserved_at_a0[0x40];
3720  
3721  	u8         reserved_at_e0[0x8];
3722  	u8         inline_rqn[0x18];
3723  
3724  	u8         rx_hash_symmetric[0x1];
3725  	u8         reserved_at_101[0x1];
3726  	u8         tunneled_offload_en[0x1];
3727  	u8         reserved_at_103[0x5];
3728  	u8         indirect_table[0x18];
3729  
3730  	u8         rx_hash_fn[0x4];
3731  	u8         reserved_at_124[0x2];
3732  	u8         self_lb_block[0x2];
3733  	u8         transport_domain[0x18];
3734  
3735  	u8         rx_hash_toeplitz_key[10][0x20];
3736  
3737  	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3738  
3739  	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3740  
3741  	u8         reserved_at_2c0[0x4c0];
3742  };
3743  
3744  enum {
3745  	MLX5_SRQC_STATE_GOOD   = 0x0,
3746  	MLX5_SRQC_STATE_ERROR  = 0x1,
3747  };
3748  
3749  struct mlx5_ifc_srqc_bits {
3750  	u8         state[0x4];
3751  	u8         log_srq_size[0x4];
3752  	u8         reserved_at_8[0x18];
3753  
3754  	u8         wq_signature[0x1];
3755  	u8         cont_srq[0x1];
3756  	u8         reserved_at_22[0x1];
3757  	u8         rlky[0x1];
3758  	u8         reserved_at_24[0x1];
3759  	u8         log_rq_stride[0x3];
3760  	u8         xrcd[0x18];
3761  
3762  	u8         page_offset[0x6];
3763  	u8         reserved_at_46[0x2];
3764  	u8         cqn[0x18];
3765  
3766  	u8         reserved_at_60[0x20];
3767  
3768  	u8         reserved_at_80[0x2];
3769  	u8         log_page_size[0x6];
3770  	u8         reserved_at_88[0x18];
3771  
3772  	u8         reserved_at_a0[0x20];
3773  
3774  	u8         reserved_at_c0[0x8];
3775  	u8         pd[0x18];
3776  
3777  	u8         lwm[0x10];
3778  	u8         wqe_cnt[0x10];
3779  
3780  	u8         reserved_at_100[0x40];
3781  
3782  	u8         dbr_addr[0x40];
3783  
3784  	u8         reserved_at_180[0x80];
3785  };
3786  
3787  enum {
3788  	MLX5_SQC_STATE_RST  = 0x0,
3789  	MLX5_SQC_STATE_RDY  = 0x1,
3790  	MLX5_SQC_STATE_ERR  = 0x3,
3791  };
3792  
3793  struct mlx5_ifc_sqc_bits {
3794  	u8         rlky[0x1];
3795  	u8         cd_master[0x1];
3796  	u8         fre[0x1];
3797  	u8         flush_in_error_en[0x1];
3798  	u8         allow_multi_pkt_send_wqe[0x1];
3799  	u8	   min_wqe_inline_mode[0x3];
3800  	u8         state[0x4];
3801  	u8         reg_umr[0x1];
3802  	u8         allow_swp[0x1];
3803  	u8         hairpin[0x1];
3804  	u8         reserved_at_f[0xb];
3805  	u8	   ts_format[0x2];
3806  	u8	   reserved_at_1c[0x4];
3807  
3808  	u8         reserved_at_20[0x8];
3809  	u8         user_index[0x18];
3810  
3811  	u8         reserved_at_40[0x8];
3812  	u8         cqn[0x18];
3813  
3814  	u8         reserved_at_60[0x8];
3815  	u8         hairpin_peer_rq[0x18];
3816  
3817  	u8         reserved_at_80[0x10];
3818  	u8         hairpin_peer_vhca[0x10];
3819  
3820  	u8         reserved_at_a0[0x20];
3821  
3822  	u8         reserved_at_c0[0x8];
3823  	u8         ts_cqe_to_dest_cqn[0x18];
3824  
3825  	u8         reserved_at_e0[0x10];
3826  	u8         packet_pacing_rate_limit_index[0x10];
3827  	u8         tis_lst_sz[0x10];
3828  	u8         qos_queue_group_id[0x10];
3829  
3830  	u8         reserved_at_120[0x40];
3831  
3832  	u8         reserved_at_160[0x8];
3833  	u8         tis_num_0[0x18];
3834  
3835  	struct mlx5_ifc_wq_bits wq;
3836  };
3837  
3838  enum {
3839  	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3840  	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3841  	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3842  	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3843  	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3844  };
3845  
3846  enum {
3847  	ELEMENT_TYPE_CAP_MASK_TSAR		= 1 << 0,
3848  	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
3849  	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
3850  	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
3851  	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,
3852  };
3853  
3854  struct mlx5_ifc_scheduling_context_bits {
3855  	u8         element_type[0x8];
3856  	u8         reserved_at_8[0x18];
3857  
3858  	u8         element_attributes[0x20];
3859  
3860  	u8         parent_element_id[0x20];
3861  
3862  	u8         reserved_at_60[0x40];
3863  
3864  	u8         bw_share[0x20];
3865  
3866  	u8         max_average_bw[0x20];
3867  
3868  	u8         reserved_at_e0[0x120];
3869  };
3870  
3871  struct mlx5_ifc_rqtc_bits {
3872  	u8    reserved_at_0[0xa0];
3873  
3874  	u8    reserved_at_a0[0x5];
3875  	u8    list_q_type[0x3];
3876  	u8    reserved_at_a8[0x8];
3877  	u8    rqt_max_size[0x10];
3878  
3879  	u8    rq_vhca_id_format[0x1];
3880  	u8    reserved_at_c1[0xf];
3881  	u8    rqt_actual_size[0x10];
3882  
3883  	u8    reserved_at_e0[0x6a0];
3884  
3885  	struct mlx5_ifc_rq_num_bits rq_num[];
3886  };
3887  
3888  enum {
3889  	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3890  	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3891  };
3892  
3893  enum {
3894  	MLX5_RQC_STATE_RST  = 0x0,
3895  	MLX5_RQC_STATE_RDY  = 0x1,
3896  	MLX5_RQC_STATE_ERR  = 0x3,
3897  };
3898  
3899  enum {
3900  	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
3901  	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
3902  	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
3903  };
3904  
3905  enum {
3906  	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
3907  	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
3908  	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
3909  };
3910  
3911  struct mlx5_ifc_rqc_bits {
3912  	u8         rlky[0x1];
3913  	u8	   delay_drop_en[0x1];
3914  	u8         scatter_fcs[0x1];
3915  	u8         vsd[0x1];
3916  	u8         mem_rq_type[0x4];
3917  	u8         state[0x4];
3918  	u8         reserved_at_c[0x1];
3919  	u8         flush_in_error_en[0x1];
3920  	u8         hairpin[0x1];
3921  	u8         reserved_at_f[0xb];
3922  	u8	   ts_format[0x2];
3923  	u8	   reserved_at_1c[0x4];
3924  
3925  	u8         reserved_at_20[0x8];
3926  	u8         user_index[0x18];
3927  
3928  	u8         reserved_at_40[0x8];
3929  	u8         cqn[0x18];
3930  
3931  	u8         counter_set_id[0x8];
3932  	u8         reserved_at_68[0x18];
3933  
3934  	u8         reserved_at_80[0x8];
3935  	u8         rmpn[0x18];
3936  
3937  	u8         reserved_at_a0[0x8];
3938  	u8         hairpin_peer_sq[0x18];
3939  
3940  	u8         reserved_at_c0[0x10];
3941  	u8         hairpin_peer_vhca[0x10];
3942  
3943  	u8         reserved_at_e0[0x46];
3944  	u8         shampo_no_match_alignment_granularity[0x2];
3945  	u8         reserved_at_128[0x6];
3946  	u8         shampo_match_criteria_type[0x2];
3947  	u8         reservation_timeout[0x10];
3948  
3949  	u8         reserved_at_140[0x40];
3950  
3951  	struct mlx5_ifc_wq_bits wq;
3952  };
3953  
3954  enum {
3955  	MLX5_RMPC_STATE_RDY  = 0x1,
3956  	MLX5_RMPC_STATE_ERR  = 0x3,
3957  };
3958  
3959  struct mlx5_ifc_rmpc_bits {
3960  	u8         reserved_at_0[0x8];
3961  	u8         state[0x4];
3962  	u8         reserved_at_c[0x14];
3963  
3964  	u8         basic_cyclic_rcv_wqe[0x1];
3965  	u8         reserved_at_21[0x1f];
3966  
3967  	u8         reserved_at_40[0x140];
3968  
3969  	struct mlx5_ifc_wq_bits wq;
3970  };
3971  
3972  enum {
3973  	VHCA_ID_TYPE_HW = 0,
3974  	VHCA_ID_TYPE_SW = 1,
3975  };
3976  
3977  struct mlx5_ifc_nic_vport_context_bits {
3978  	u8         reserved_at_0[0x5];
3979  	u8         min_wqe_inline_mode[0x3];
3980  	u8         reserved_at_8[0x15];
3981  	u8         disable_mc_local_lb[0x1];
3982  	u8         disable_uc_local_lb[0x1];
3983  	u8         roce_en[0x1];
3984  
3985  	u8         arm_change_event[0x1];
3986  	u8         reserved_at_21[0x1a];
3987  	u8         event_on_mtu[0x1];
3988  	u8         event_on_promisc_change[0x1];
3989  	u8         event_on_vlan_change[0x1];
3990  	u8         event_on_mc_address_change[0x1];
3991  	u8         event_on_uc_address_change[0x1];
3992  
3993  	u8         vhca_id_type[0x1];
3994  	u8         reserved_at_41[0xb];
3995  	u8	   affiliation_criteria[0x4];
3996  	u8	   affiliated_vhca_id[0x10];
3997  
3998  	u8	   reserved_at_60[0xd0];
3999  
4000  	u8         mtu[0x10];
4001  
4002  	u8         system_image_guid[0x40];
4003  	u8         port_guid[0x40];
4004  	u8         node_guid[0x40];
4005  
4006  	u8         reserved_at_200[0x140];
4007  	u8         qkey_violation_counter[0x10];
4008  	u8         reserved_at_350[0x430];
4009  
4010  	u8         promisc_uc[0x1];
4011  	u8         promisc_mc[0x1];
4012  	u8         promisc_all[0x1];
4013  	u8         reserved_at_783[0x2];
4014  	u8         allowed_list_type[0x3];
4015  	u8         reserved_at_788[0xc];
4016  	u8         allowed_list_size[0xc];
4017  
4018  	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4019  
4020  	u8         reserved_at_7e0[0x20];
4021  
4022  	u8         current_uc_mac_address[][0x40];
4023  };
4024  
4025  enum {
4026  	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4027  	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4028  	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4029  	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4030  	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4031  	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4032  };
4033  
4034  struct mlx5_ifc_mkc_bits {
4035  	u8         reserved_at_0[0x1];
4036  	u8         free[0x1];
4037  	u8         reserved_at_2[0x1];
4038  	u8         access_mode_4_2[0x3];
4039  	u8         reserved_at_6[0x7];
4040  	u8         relaxed_ordering_write[0x1];
4041  	u8         reserved_at_e[0x1];
4042  	u8         small_fence_on_rdma_read_response[0x1];
4043  	u8         umr_en[0x1];
4044  	u8         a[0x1];
4045  	u8         rw[0x1];
4046  	u8         rr[0x1];
4047  	u8         lw[0x1];
4048  	u8         lr[0x1];
4049  	u8         access_mode_1_0[0x2];
4050  	u8         reserved_at_18[0x2];
4051  	u8         ma_translation_mode[0x2];
4052  	u8         reserved_at_1c[0x4];
4053  
4054  	u8         qpn[0x18];
4055  	u8         mkey_7_0[0x8];
4056  
4057  	u8         reserved_at_40[0x20];
4058  
4059  	u8         length64[0x1];
4060  	u8         bsf_en[0x1];
4061  	u8         sync_umr[0x1];
4062  	u8         reserved_at_63[0x2];
4063  	u8         expected_sigerr_count[0x1];
4064  	u8         reserved_at_66[0x1];
4065  	u8         en_rinval[0x1];
4066  	u8         pd[0x18];
4067  
4068  	u8         start_addr[0x40];
4069  
4070  	u8         len[0x40];
4071  
4072  	u8         bsf_octword_size[0x20];
4073  
4074  	u8         reserved_at_120[0x80];
4075  
4076  	u8         translations_octword_size[0x20];
4077  
4078  	u8         reserved_at_1c0[0x19];
4079  	u8         relaxed_ordering_read[0x1];
4080  	u8         reserved_at_1d9[0x1];
4081  	u8         log_page_size[0x5];
4082  
4083  	u8         reserved_at_1e0[0x20];
4084  };
4085  
4086  struct mlx5_ifc_pkey_bits {
4087  	u8         reserved_at_0[0x10];
4088  	u8         pkey[0x10];
4089  };
4090  
4091  struct mlx5_ifc_array128_auto_bits {
4092  	u8         array128_auto[16][0x8];
4093  };
4094  
4095  struct mlx5_ifc_hca_vport_context_bits {
4096  	u8         field_select[0x20];
4097  
4098  	u8         reserved_at_20[0xe0];
4099  
4100  	u8         sm_virt_aware[0x1];
4101  	u8         has_smi[0x1];
4102  	u8         has_raw[0x1];
4103  	u8         grh_required[0x1];
4104  	u8         reserved_at_104[0xc];
4105  	u8         port_physical_state[0x4];
4106  	u8         vport_state_policy[0x4];
4107  	u8         port_state[0x4];
4108  	u8         vport_state[0x4];
4109  
4110  	u8         reserved_at_120[0x20];
4111  
4112  	u8         system_image_guid[0x40];
4113  
4114  	u8         port_guid[0x40];
4115  
4116  	u8         node_guid[0x40];
4117  
4118  	u8         cap_mask1[0x20];
4119  
4120  	u8         cap_mask1_field_select[0x20];
4121  
4122  	u8         cap_mask2[0x20];
4123  
4124  	u8         cap_mask2_field_select[0x20];
4125  
4126  	u8         reserved_at_280[0x80];
4127  
4128  	u8         lid[0x10];
4129  	u8         reserved_at_310[0x4];
4130  	u8         init_type_reply[0x4];
4131  	u8         lmc[0x3];
4132  	u8         subnet_timeout[0x5];
4133  
4134  	u8         sm_lid[0x10];
4135  	u8         sm_sl[0x4];
4136  	u8         reserved_at_334[0xc];
4137  
4138  	u8         qkey_violation_counter[0x10];
4139  	u8         pkey_violation_counter[0x10];
4140  
4141  	u8         reserved_at_360[0xca0];
4142  };
4143  
4144  struct mlx5_ifc_esw_vport_context_bits {
4145  	u8         fdb_to_vport_reg_c[0x1];
4146  	u8         reserved_at_1[0x2];
4147  	u8         vport_svlan_strip[0x1];
4148  	u8         vport_cvlan_strip[0x1];
4149  	u8         vport_svlan_insert[0x1];
4150  	u8         vport_cvlan_insert[0x2];
4151  	u8         fdb_to_vport_reg_c_id[0x8];
4152  	u8         reserved_at_10[0x10];
4153  
4154  	u8         reserved_at_20[0x20];
4155  
4156  	u8         svlan_cfi[0x1];
4157  	u8         svlan_pcp[0x3];
4158  	u8         svlan_id[0xc];
4159  	u8         cvlan_cfi[0x1];
4160  	u8         cvlan_pcp[0x3];
4161  	u8         cvlan_id[0xc];
4162  
4163  	u8         reserved_at_60[0x720];
4164  
4165  	u8         sw_steering_vport_icm_address_rx[0x40];
4166  
4167  	u8         sw_steering_vport_icm_address_tx[0x40];
4168  };
4169  
4170  enum {
4171  	MLX5_EQC_STATUS_OK                = 0x0,
4172  	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4173  };
4174  
4175  enum {
4176  	MLX5_EQC_ST_ARMED  = 0x9,
4177  	MLX5_EQC_ST_FIRED  = 0xa,
4178  };
4179  
4180  struct mlx5_ifc_eqc_bits {
4181  	u8         status[0x4];
4182  	u8         reserved_at_4[0x9];
4183  	u8         ec[0x1];
4184  	u8         oi[0x1];
4185  	u8         reserved_at_f[0x5];
4186  	u8         st[0x4];
4187  	u8         reserved_at_18[0x8];
4188  
4189  	u8         reserved_at_20[0x20];
4190  
4191  	u8         reserved_at_40[0x14];
4192  	u8         page_offset[0x6];
4193  	u8         reserved_at_5a[0x6];
4194  
4195  	u8         reserved_at_60[0x3];
4196  	u8         log_eq_size[0x5];
4197  	u8         uar_page[0x18];
4198  
4199  	u8         reserved_at_80[0x20];
4200  
4201  	u8         reserved_at_a0[0x14];
4202  	u8         intr[0xc];
4203  
4204  	u8         reserved_at_c0[0x3];
4205  	u8         log_page_size[0x5];
4206  	u8         reserved_at_c8[0x18];
4207  
4208  	u8         reserved_at_e0[0x60];
4209  
4210  	u8         reserved_at_140[0x8];
4211  	u8         consumer_counter[0x18];
4212  
4213  	u8         reserved_at_160[0x8];
4214  	u8         producer_counter[0x18];
4215  
4216  	u8         reserved_at_180[0x80];
4217  };
4218  
4219  enum {
4220  	MLX5_DCTC_STATE_ACTIVE    = 0x0,
4221  	MLX5_DCTC_STATE_DRAINING  = 0x1,
4222  	MLX5_DCTC_STATE_DRAINED   = 0x2,
4223  };
4224  
4225  enum {
4226  	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4227  	MLX5_DCTC_CS_RES_NA         = 0x1,
4228  	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4229  };
4230  
4231  enum {
4232  	MLX5_DCTC_MTU_256_BYTES  = 0x1,
4233  	MLX5_DCTC_MTU_512_BYTES  = 0x2,
4234  	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4235  	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4236  	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4237  };
4238  
4239  struct mlx5_ifc_dctc_bits {
4240  	u8         reserved_at_0[0x4];
4241  	u8         state[0x4];
4242  	u8         reserved_at_8[0x18];
4243  
4244  	u8         reserved_at_20[0x8];
4245  	u8         user_index[0x18];
4246  
4247  	u8         reserved_at_40[0x8];
4248  	u8         cqn[0x18];
4249  
4250  	u8         counter_set_id[0x8];
4251  	u8         atomic_mode[0x4];
4252  	u8         rre[0x1];
4253  	u8         rwe[0x1];
4254  	u8         rae[0x1];
4255  	u8         atomic_like_write_en[0x1];
4256  	u8         latency_sensitive[0x1];
4257  	u8         rlky[0x1];
4258  	u8         free_ar[0x1];
4259  	u8         reserved_at_73[0xd];
4260  
4261  	u8         reserved_at_80[0x8];
4262  	u8         cs_res[0x8];
4263  	u8         reserved_at_90[0x3];
4264  	u8         min_rnr_nak[0x5];
4265  	u8         reserved_at_98[0x8];
4266  
4267  	u8         reserved_at_a0[0x8];
4268  	u8         srqn_xrqn[0x18];
4269  
4270  	u8         reserved_at_c0[0x8];
4271  	u8         pd[0x18];
4272  
4273  	u8         tclass[0x8];
4274  	u8         reserved_at_e8[0x4];
4275  	u8         flow_label[0x14];
4276  
4277  	u8         dc_access_key[0x40];
4278  
4279  	u8         reserved_at_140[0x5];
4280  	u8         mtu[0x3];
4281  	u8         port[0x8];
4282  	u8         pkey_index[0x10];
4283  
4284  	u8         reserved_at_160[0x8];
4285  	u8         my_addr_index[0x8];
4286  	u8         reserved_at_170[0x8];
4287  	u8         hop_limit[0x8];
4288  
4289  	u8         dc_access_key_violation_count[0x20];
4290  
4291  	u8         reserved_at_1a0[0x14];
4292  	u8         dei_cfi[0x1];
4293  	u8         eth_prio[0x3];
4294  	u8         ecn[0x2];
4295  	u8         dscp[0x6];
4296  
4297  	u8         reserved_at_1c0[0x20];
4298  	u8         ece[0x20];
4299  };
4300  
4301  enum {
4302  	MLX5_CQC_STATUS_OK             = 0x0,
4303  	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4304  	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4305  };
4306  
4307  enum {
4308  	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4309  	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4310  };
4311  
4312  enum {
4313  	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4314  	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4315  	MLX5_CQC_ST_FIRED                                 = 0xa,
4316  };
4317  
4318  enum {
4319  	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4320  	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4321  	MLX5_CQ_PERIOD_NUM_MODES
4322  };
4323  
4324  struct mlx5_ifc_cqc_bits {
4325  	u8         status[0x4];
4326  	u8         reserved_at_4[0x2];
4327  	u8         dbr_umem_valid[0x1];
4328  	u8         apu_cq[0x1];
4329  	u8         cqe_sz[0x3];
4330  	u8         cc[0x1];
4331  	u8         reserved_at_c[0x1];
4332  	u8         scqe_break_moderation_en[0x1];
4333  	u8         oi[0x1];
4334  	u8         cq_period_mode[0x2];
4335  	u8         cqe_comp_en[0x1];
4336  	u8         mini_cqe_res_format[0x2];
4337  	u8         st[0x4];
4338  	u8         reserved_at_18[0x6];
4339  	u8         cqe_compression_layout[0x2];
4340  
4341  	u8         reserved_at_20[0x20];
4342  
4343  	u8         reserved_at_40[0x14];
4344  	u8         page_offset[0x6];
4345  	u8         reserved_at_5a[0x6];
4346  
4347  	u8         reserved_at_60[0x3];
4348  	u8         log_cq_size[0x5];
4349  	u8         uar_page[0x18];
4350  
4351  	u8         reserved_at_80[0x4];
4352  	u8         cq_period[0xc];
4353  	u8         cq_max_count[0x10];
4354  
4355  	u8         c_eqn_or_apu_element[0x20];
4356  
4357  	u8         reserved_at_c0[0x3];
4358  	u8         log_page_size[0x5];
4359  	u8         reserved_at_c8[0x18];
4360  
4361  	u8         reserved_at_e0[0x20];
4362  
4363  	u8         reserved_at_100[0x8];
4364  	u8         last_notified_index[0x18];
4365  
4366  	u8         reserved_at_120[0x8];
4367  	u8         last_solicit_index[0x18];
4368  
4369  	u8         reserved_at_140[0x8];
4370  	u8         consumer_counter[0x18];
4371  
4372  	u8         reserved_at_160[0x8];
4373  	u8         producer_counter[0x18];
4374  
4375  	u8         reserved_at_180[0x40];
4376  
4377  	u8         dbr_addr[0x40];
4378  };
4379  
4380  union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4381  	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4382  	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4383  	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4384  	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4385  	u8         reserved_at_0[0x800];
4386  };
4387  
4388  struct mlx5_ifc_query_adapter_param_block_bits {
4389  	u8         reserved_at_0[0xc0];
4390  
4391  	u8         reserved_at_c0[0x8];
4392  	u8         ieee_vendor_id[0x18];
4393  
4394  	u8         reserved_at_e0[0x10];
4395  	u8         vsd_vendor_id[0x10];
4396  
4397  	u8         vsd[208][0x8];
4398  
4399  	u8         vsd_contd_psid[16][0x8];
4400  };
4401  
4402  enum {
4403  	MLX5_XRQC_STATE_GOOD   = 0x0,
4404  	MLX5_XRQC_STATE_ERROR  = 0x1,
4405  };
4406  
4407  enum {
4408  	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4409  	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4410  };
4411  
4412  enum {
4413  	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4414  };
4415  
4416  struct mlx5_ifc_tag_matching_topology_context_bits {
4417  	u8         log_matching_list_sz[0x4];
4418  	u8         reserved_at_4[0xc];
4419  	u8         append_next_index[0x10];
4420  
4421  	u8         sw_phase_cnt[0x10];
4422  	u8         hw_phase_cnt[0x10];
4423  
4424  	u8         reserved_at_40[0x40];
4425  };
4426  
4427  struct mlx5_ifc_xrqc_bits {
4428  	u8         state[0x4];
4429  	u8         rlkey[0x1];
4430  	u8         reserved_at_5[0xf];
4431  	u8         topology[0x4];
4432  	u8         reserved_at_18[0x4];
4433  	u8         offload[0x4];
4434  
4435  	u8         reserved_at_20[0x8];
4436  	u8         user_index[0x18];
4437  
4438  	u8         reserved_at_40[0x8];
4439  	u8         cqn[0x18];
4440  
4441  	u8         reserved_at_60[0xa0];
4442  
4443  	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4444  
4445  	u8         reserved_at_180[0x280];
4446  
4447  	struct mlx5_ifc_wq_bits wq;
4448  };
4449  
4450  union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4451  	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4452  	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4453  	u8         reserved_at_0[0x20];
4454  };
4455  
4456  union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4457  	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4458  	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4459  	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4460  	u8         reserved_at_0[0x20];
4461  };
4462  
4463  union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4464  	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4465  	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4466  	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4467  	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4468  	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4469  	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4470  	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4471  	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4472  	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4473  	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4474  	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4475  	u8         reserved_at_0[0x7c0];
4476  };
4477  
4478  union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4479  	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4480  	u8         reserved_at_0[0x7c0];
4481  };
4482  
4483  union mlx5_ifc_event_auto_bits {
4484  	struct mlx5_ifc_comp_event_bits comp_event;
4485  	struct mlx5_ifc_dct_events_bits dct_events;
4486  	struct mlx5_ifc_qp_events_bits qp_events;
4487  	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4488  	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4489  	struct mlx5_ifc_cq_error_bits cq_error;
4490  	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4491  	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4492  	struct mlx5_ifc_gpio_event_bits gpio_event;
4493  	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4494  	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4495  	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4496  	u8         reserved_at_0[0xe0];
4497  };
4498  
4499  struct mlx5_ifc_health_buffer_bits {
4500  	u8         reserved_at_0[0x100];
4501  
4502  	u8         assert_existptr[0x20];
4503  
4504  	u8         assert_callra[0x20];
4505  
4506  	u8         reserved_at_140[0x20];
4507  
4508  	u8         time[0x20];
4509  
4510  	u8         fw_version[0x20];
4511  
4512  	u8         hw_id[0x20];
4513  
4514  	u8         rfr[0x1];
4515  	u8         reserved_at_1c1[0x3];
4516  	u8         valid[0x1];
4517  	u8         severity[0x3];
4518  	u8         reserved_at_1c8[0x18];
4519  
4520  	u8         irisc_index[0x8];
4521  	u8         synd[0x8];
4522  	u8         ext_synd[0x10];
4523  };
4524  
4525  struct mlx5_ifc_register_loopback_control_bits {
4526  	u8         no_lb[0x1];
4527  	u8         reserved_at_1[0x7];
4528  	u8         port[0x8];
4529  	u8         reserved_at_10[0x10];
4530  
4531  	u8         reserved_at_20[0x60];
4532  };
4533  
4534  struct mlx5_ifc_vport_tc_element_bits {
4535  	u8         traffic_class[0x4];
4536  	u8         reserved_at_4[0xc];
4537  	u8         vport_number[0x10];
4538  };
4539  
4540  struct mlx5_ifc_vport_element_bits {
4541  	u8         reserved_at_0[0x10];
4542  	u8         vport_number[0x10];
4543  };
4544  
4545  enum {
4546  	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4547  	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4548  	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4549  };
4550  
4551  enum {
4552  	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,
4553  	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,
4554  	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,
4555  };
4556  
4557  struct mlx5_ifc_tsar_element_bits {
4558  	u8         reserved_at_0[0x8];
4559  	u8         tsar_type[0x8];
4560  	u8         reserved_at_10[0x10];
4561  };
4562  
4563  enum {
4564  	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4565  	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4566  };
4567  
4568  struct mlx5_ifc_teardown_hca_out_bits {
4569  	u8         status[0x8];
4570  	u8         reserved_at_8[0x18];
4571  
4572  	u8         syndrome[0x20];
4573  
4574  	u8         reserved_at_40[0x3f];
4575  
4576  	u8         state[0x1];
4577  };
4578  
4579  enum {
4580  	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4581  	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4582  	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4583  };
4584  
4585  struct mlx5_ifc_teardown_hca_in_bits {
4586  	u8         opcode[0x10];
4587  	u8         reserved_at_10[0x10];
4588  
4589  	u8         reserved_at_20[0x10];
4590  	u8         op_mod[0x10];
4591  
4592  	u8         reserved_at_40[0x10];
4593  	u8         profile[0x10];
4594  
4595  	u8         reserved_at_60[0x20];
4596  };
4597  
4598  struct mlx5_ifc_sqerr2rts_qp_out_bits {
4599  	u8         status[0x8];
4600  	u8         reserved_at_8[0x18];
4601  
4602  	u8         syndrome[0x20];
4603  
4604  	u8         reserved_at_40[0x40];
4605  };
4606  
4607  struct mlx5_ifc_sqerr2rts_qp_in_bits {
4608  	u8         opcode[0x10];
4609  	u8         uid[0x10];
4610  
4611  	u8         reserved_at_20[0x10];
4612  	u8         op_mod[0x10];
4613  
4614  	u8         reserved_at_40[0x8];
4615  	u8         qpn[0x18];
4616  
4617  	u8         reserved_at_60[0x20];
4618  
4619  	u8         opt_param_mask[0x20];
4620  
4621  	u8         reserved_at_a0[0x20];
4622  
4623  	struct mlx5_ifc_qpc_bits qpc;
4624  
4625  	u8         reserved_at_800[0x80];
4626  };
4627  
4628  struct mlx5_ifc_sqd2rts_qp_out_bits {
4629  	u8         status[0x8];
4630  	u8         reserved_at_8[0x18];
4631  
4632  	u8         syndrome[0x20];
4633  
4634  	u8         reserved_at_40[0x40];
4635  };
4636  
4637  struct mlx5_ifc_sqd2rts_qp_in_bits {
4638  	u8         opcode[0x10];
4639  	u8         uid[0x10];
4640  
4641  	u8         reserved_at_20[0x10];
4642  	u8         op_mod[0x10];
4643  
4644  	u8         reserved_at_40[0x8];
4645  	u8         qpn[0x18];
4646  
4647  	u8         reserved_at_60[0x20];
4648  
4649  	u8         opt_param_mask[0x20];
4650  
4651  	u8         reserved_at_a0[0x20];
4652  
4653  	struct mlx5_ifc_qpc_bits qpc;
4654  
4655  	u8         reserved_at_800[0x80];
4656  };
4657  
4658  struct mlx5_ifc_set_roce_address_out_bits {
4659  	u8         status[0x8];
4660  	u8         reserved_at_8[0x18];
4661  
4662  	u8         syndrome[0x20];
4663  
4664  	u8         reserved_at_40[0x40];
4665  };
4666  
4667  struct mlx5_ifc_set_roce_address_in_bits {
4668  	u8         opcode[0x10];
4669  	u8         reserved_at_10[0x10];
4670  
4671  	u8         reserved_at_20[0x10];
4672  	u8         op_mod[0x10];
4673  
4674  	u8         roce_address_index[0x10];
4675  	u8         reserved_at_50[0xc];
4676  	u8	   vhca_port_num[0x4];
4677  
4678  	u8         reserved_at_60[0x20];
4679  
4680  	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4681  };
4682  
4683  struct mlx5_ifc_set_mad_demux_out_bits {
4684  	u8         status[0x8];
4685  	u8         reserved_at_8[0x18];
4686  
4687  	u8         syndrome[0x20];
4688  
4689  	u8         reserved_at_40[0x40];
4690  };
4691  
4692  enum {
4693  	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4694  	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4695  };
4696  
4697  struct mlx5_ifc_set_mad_demux_in_bits {
4698  	u8         opcode[0x10];
4699  	u8         reserved_at_10[0x10];
4700  
4701  	u8         reserved_at_20[0x10];
4702  	u8         op_mod[0x10];
4703  
4704  	u8         reserved_at_40[0x20];
4705  
4706  	u8         reserved_at_60[0x6];
4707  	u8         demux_mode[0x2];
4708  	u8         reserved_at_68[0x18];
4709  };
4710  
4711  struct mlx5_ifc_set_l2_table_entry_out_bits {
4712  	u8         status[0x8];
4713  	u8         reserved_at_8[0x18];
4714  
4715  	u8         syndrome[0x20];
4716  
4717  	u8         reserved_at_40[0x40];
4718  };
4719  
4720  struct mlx5_ifc_set_l2_table_entry_in_bits {
4721  	u8         opcode[0x10];
4722  	u8         reserved_at_10[0x10];
4723  
4724  	u8         reserved_at_20[0x10];
4725  	u8         op_mod[0x10];
4726  
4727  	u8         reserved_at_40[0x60];
4728  
4729  	u8         reserved_at_a0[0x8];
4730  	u8         table_index[0x18];
4731  
4732  	u8         reserved_at_c0[0x20];
4733  
4734  	u8         reserved_at_e0[0x13];
4735  	u8         vlan_valid[0x1];
4736  	u8         vlan[0xc];
4737  
4738  	struct mlx5_ifc_mac_address_layout_bits mac_address;
4739  
4740  	u8         reserved_at_140[0xc0];
4741  };
4742  
4743  struct mlx5_ifc_set_issi_out_bits {
4744  	u8         status[0x8];
4745  	u8         reserved_at_8[0x18];
4746  
4747  	u8         syndrome[0x20];
4748  
4749  	u8         reserved_at_40[0x40];
4750  };
4751  
4752  struct mlx5_ifc_set_issi_in_bits {
4753  	u8         opcode[0x10];
4754  	u8         reserved_at_10[0x10];
4755  
4756  	u8         reserved_at_20[0x10];
4757  	u8         op_mod[0x10];
4758  
4759  	u8         reserved_at_40[0x10];
4760  	u8         current_issi[0x10];
4761  
4762  	u8         reserved_at_60[0x20];
4763  };
4764  
4765  struct mlx5_ifc_set_hca_cap_out_bits {
4766  	u8         status[0x8];
4767  	u8         reserved_at_8[0x18];
4768  
4769  	u8         syndrome[0x20];
4770  
4771  	u8         reserved_at_40[0x40];
4772  };
4773  
4774  struct mlx5_ifc_set_hca_cap_in_bits {
4775  	u8         opcode[0x10];
4776  	u8         reserved_at_10[0x10];
4777  
4778  	u8         reserved_at_20[0x10];
4779  	u8         op_mod[0x10];
4780  
4781  	u8         other_function[0x1];
4782  	u8         ec_vf_function[0x1];
4783  	u8         reserved_at_42[0xe];
4784  	u8         function_id[0x10];
4785  
4786  	u8         reserved_at_60[0x20];
4787  
4788  	union mlx5_ifc_hca_cap_union_bits capability;
4789  };
4790  
4791  enum {
4792  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4793  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4794  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4795  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4796  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4797  };
4798  
4799  struct mlx5_ifc_set_fte_out_bits {
4800  	u8         status[0x8];
4801  	u8         reserved_at_8[0x18];
4802  
4803  	u8         syndrome[0x20];
4804  
4805  	u8         reserved_at_40[0x40];
4806  };
4807  
4808  struct mlx5_ifc_set_fte_in_bits {
4809  	u8         opcode[0x10];
4810  	u8         reserved_at_10[0x10];
4811  
4812  	u8         reserved_at_20[0x10];
4813  	u8         op_mod[0x10];
4814  
4815  	u8         other_vport[0x1];
4816  	u8         reserved_at_41[0xf];
4817  	u8         vport_number[0x10];
4818  
4819  	u8         reserved_at_60[0x20];
4820  
4821  	u8         table_type[0x8];
4822  	u8         reserved_at_88[0x18];
4823  
4824  	u8         reserved_at_a0[0x8];
4825  	u8         table_id[0x18];
4826  
4827  	u8         ignore_flow_level[0x1];
4828  	u8         reserved_at_c1[0x17];
4829  	u8         modify_enable_mask[0x8];
4830  
4831  	u8         reserved_at_e0[0x20];
4832  
4833  	u8         flow_index[0x20];
4834  
4835  	u8         reserved_at_120[0xe0];
4836  
4837  	struct mlx5_ifc_flow_context_bits flow_context;
4838  };
4839  
4840  struct mlx5_ifc_rts2rts_qp_out_bits {
4841  	u8         status[0x8];
4842  	u8         reserved_at_8[0x18];
4843  
4844  	u8         syndrome[0x20];
4845  
4846  	u8         reserved_at_40[0x20];
4847  	u8         ece[0x20];
4848  };
4849  
4850  struct mlx5_ifc_rts2rts_qp_in_bits {
4851  	u8         opcode[0x10];
4852  	u8         uid[0x10];
4853  
4854  	u8         reserved_at_20[0x10];
4855  	u8         op_mod[0x10];
4856  
4857  	u8         reserved_at_40[0x8];
4858  	u8         qpn[0x18];
4859  
4860  	u8         reserved_at_60[0x20];
4861  
4862  	u8         opt_param_mask[0x20];
4863  
4864  	u8         ece[0x20];
4865  
4866  	struct mlx5_ifc_qpc_bits qpc;
4867  
4868  	u8         reserved_at_800[0x80];
4869  };
4870  
4871  struct mlx5_ifc_rtr2rts_qp_out_bits {
4872  	u8         status[0x8];
4873  	u8         reserved_at_8[0x18];
4874  
4875  	u8         syndrome[0x20];
4876  
4877  	u8         reserved_at_40[0x20];
4878  	u8         ece[0x20];
4879  };
4880  
4881  struct mlx5_ifc_rtr2rts_qp_in_bits {
4882  	u8         opcode[0x10];
4883  	u8         uid[0x10];
4884  
4885  	u8         reserved_at_20[0x10];
4886  	u8         op_mod[0x10];
4887  
4888  	u8         reserved_at_40[0x8];
4889  	u8         qpn[0x18];
4890  
4891  	u8         reserved_at_60[0x20];
4892  
4893  	u8         opt_param_mask[0x20];
4894  
4895  	u8         ece[0x20];
4896  
4897  	struct mlx5_ifc_qpc_bits qpc;
4898  
4899  	u8         reserved_at_800[0x80];
4900  };
4901  
4902  struct mlx5_ifc_rst2init_qp_out_bits {
4903  	u8         status[0x8];
4904  	u8         reserved_at_8[0x18];
4905  
4906  	u8         syndrome[0x20];
4907  
4908  	u8         reserved_at_40[0x20];
4909  	u8         ece[0x20];
4910  };
4911  
4912  struct mlx5_ifc_rst2init_qp_in_bits {
4913  	u8         opcode[0x10];
4914  	u8         uid[0x10];
4915  
4916  	u8         reserved_at_20[0x10];
4917  	u8         op_mod[0x10];
4918  
4919  	u8         reserved_at_40[0x8];
4920  	u8         qpn[0x18];
4921  
4922  	u8         reserved_at_60[0x20];
4923  
4924  	u8         opt_param_mask[0x20];
4925  
4926  	u8         ece[0x20];
4927  
4928  	struct mlx5_ifc_qpc_bits qpc;
4929  
4930  	u8         reserved_at_800[0x80];
4931  };
4932  
4933  struct mlx5_ifc_query_xrq_out_bits {
4934  	u8         status[0x8];
4935  	u8         reserved_at_8[0x18];
4936  
4937  	u8         syndrome[0x20];
4938  
4939  	u8         reserved_at_40[0x40];
4940  
4941  	struct mlx5_ifc_xrqc_bits xrq_context;
4942  };
4943  
4944  struct mlx5_ifc_query_xrq_in_bits {
4945  	u8         opcode[0x10];
4946  	u8         reserved_at_10[0x10];
4947  
4948  	u8         reserved_at_20[0x10];
4949  	u8         op_mod[0x10];
4950  
4951  	u8         reserved_at_40[0x8];
4952  	u8         xrqn[0x18];
4953  
4954  	u8         reserved_at_60[0x20];
4955  };
4956  
4957  struct mlx5_ifc_query_xrc_srq_out_bits {
4958  	u8         status[0x8];
4959  	u8         reserved_at_8[0x18];
4960  
4961  	u8         syndrome[0x20];
4962  
4963  	u8         reserved_at_40[0x40];
4964  
4965  	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4966  
4967  	u8         reserved_at_280[0x600];
4968  
4969  	u8         pas[][0x40];
4970  };
4971  
4972  struct mlx5_ifc_query_xrc_srq_in_bits {
4973  	u8         opcode[0x10];
4974  	u8         reserved_at_10[0x10];
4975  
4976  	u8         reserved_at_20[0x10];
4977  	u8         op_mod[0x10];
4978  
4979  	u8         reserved_at_40[0x8];
4980  	u8         xrc_srqn[0x18];
4981  
4982  	u8         reserved_at_60[0x20];
4983  };
4984  
4985  enum {
4986  	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4987  	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4988  };
4989  
4990  struct mlx5_ifc_query_vport_state_out_bits {
4991  	u8         status[0x8];
4992  	u8         reserved_at_8[0x18];
4993  
4994  	u8         syndrome[0x20];
4995  
4996  	u8         reserved_at_40[0x20];
4997  
4998  	u8         reserved_at_60[0x18];
4999  	u8         admin_state[0x4];
5000  	u8         state[0x4];
5001  };
5002  
5003  enum {
5004  	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
5005  	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
5006  	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
5007  };
5008  
5009  struct mlx5_ifc_arm_monitor_counter_in_bits {
5010  	u8         opcode[0x10];
5011  	u8         uid[0x10];
5012  
5013  	u8         reserved_at_20[0x10];
5014  	u8         op_mod[0x10];
5015  
5016  	u8         reserved_at_40[0x20];
5017  
5018  	u8         reserved_at_60[0x20];
5019  };
5020  
5021  struct mlx5_ifc_arm_monitor_counter_out_bits {
5022  	u8         status[0x8];
5023  	u8         reserved_at_8[0x18];
5024  
5025  	u8         syndrome[0x20];
5026  
5027  	u8         reserved_at_40[0x40];
5028  };
5029  
5030  enum {
5031  	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5032  	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5033  };
5034  
5035  enum mlx5_monitor_counter_ppcnt {
5036  	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5037  	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5038  	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5039  	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5040  	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5041  	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5042  };
5043  
5044  enum {
5045  	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5046  };
5047  
5048  struct mlx5_ifc_monitor_counter_output_bits {
5049  	u8         reserved_at_0[0x4];
5050  	u8         type[0x4];
5051  	u8         reserved_at_8[0x8];
5052  	u8         counter[0x10];
5053  
5054  	u8         counter_group_id[0x20];
5055  };
5056  
5057  #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5058  #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5059  #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5060  					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5061  
5062  struct mlx5_ifc_set_monitor_counter_in_bits {
5063  	u8         opcode[0x10];
5064  	u8         uid[0x10];
5065  
5066  	u8         reserved_at_20[0x10];
5067  	u8         op_mod[0x10];
5068  
5069  	u8         reserved_at_40[0x10];
5070  	u8         num_of_counters[0x10];
5071  
5072  	u8         reserved_at_60[0x20];
5073  
5074  	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5075  };
5076  
5077  struct mlx5_ifc_set_monitor_counter_out_bits {
5078  	u8         status[0x8];
5079  	u8         reserved_at_8[0x18];
5080  
5081  	u8         syndrome[0x20];
5082  
5083  	u8         reserved_at_40[0x40];
5084  };
5085  
5086  struct mlx5_ifc_query_vport_state_in_bits {
5087  	u8         opcode[0x10];
5088  	u8         reserved_at_10[0x10];
5089  
5090  	u8         reserved_at_20[0x10];
5091  	u8         op_mod[0x10];
5092  
5093  	u8         other_vport[0x1];
5094  	u8         reserved_at_41[0xf];
5095  	u8         vport_number[0x10];
5096  
5097  	u8         reserved_at_60[0x20];
5098  };
5099  
5100  struct mlx5_ifc_query_vnic_env_out_bits {
5101  	u8         status[0x8];
5102  	u8         reserved_at_8[0x18];
5103  
5104  	u8         syndrome[0x20];
5105  
5106  	u8         reserved_at_40[0x40];
5107  
5108  	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5109  };
5110  
5111  enum {
5112  	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5113  };
5114  
5115  struct mlx5_ifc_query_vnic_env_in_bits {
5116  	u8         opcode[0x10];
5117  	u8         reserved_at_10[0x10];
5118  
5119  	u8         reserved_at_20[0x10];
5120  	u8         op_mod[0x10];
5121  
5122  	u8         other_vport[0x1];
5123  	u8         reserved_at_41[0xf];
5124  	u8         vport_number[0x10];
5125  
5126  	u8         reserved_at_60[0x20];
5127  };
5128  
5129  struct mlx5_ifc_query_vport_counter_out_bits {
5130  	u8         status[0x8];
5131  	u8         reserved_at_8[0x18];
5132  
5133  	u8         syndrome[0x20];
5134  
5135  	u8         reserved_at_40[0x40];
5136  
5137  	struct mlx5_ifc_traffic_counter_bits received_errors;
5138  
5139  	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5140  
5141  	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5142  
5143  	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5144  
5145  	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5146  
5147  	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5148  
5149  	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5150  
5151  	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5152  
5153  	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5154  
5155  	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5156  
5157  	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5158  
5159  	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5160  
5161  	struct mlx5_ifc_traffic_counter_bits local_loopback;
5162  
5163  	u8         reserved_at_700[0x980];
5164  };
5165  
5166  enum {
5167  	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5168  };
5169  
5170  struct mlx5_ifc_query_vport_counter_in_bits {
5171  	u8         opcode[0x10];
5172  	u8         reserved_at_10[0x10];
5173  
5174  	u8         reserved_at_20[0x10];
5175  	u8         op_mod[0x10];
5176  
5177  	u8         other_vport[0x1];
5178  	u8         reserved_at_41[0xb];
5179  	u8	   port_num[0x4];
5180  	u8         vport_number[0x10];
5181  
5182  	u8         reserved_at_60[0x60];
5183  
5184  	u8         clear[0x1];
5185  	u8         reserved_at_c1[0x1f];
5186  
5187  	u8         reserved_at_e0[0x20];
5188  };
5189  
5190  struct mlx5_ifc_query_tis_out_bits {
5191  	u8         status[0x8];
5192  	u8         reserved_at_8[0x18];
5193  
5194  	u8         syndrome[0x20];
5195  
5196  	u8         reserved_at_40[0x40];
5197  
5198  	struct mlx5_ifc_tisc_bits tis_context;
5199  };
5200  
5201  struct mlx5_ifc_query_tis_in_bits {
5202  	u8         opcode[0x10];
5203  	u8         reserved_at_10[0x10];
5204  
5205  	u8         reserved_at_20[0x10];
5206  	u8         op_mod[0x10];
5207  
5208  	u8         reserved_at_40[0x8];
5209  	u8         tisn[0x18];
5210  
5211  	u8         reserved_at_60[0x20];
5212  };
5213  
5214  struct mlx5_ifc_query_tir_out_bits {
5215  	u8         status[0x8];
5216  	u8         reserved_at_8[0x18];
5217  
5218  	u8         syndrome[0x20];
5219  
5220  	u8         reserved_at_40[0xc0];
5221  
5222  	struct mlx5_ifc_tirc_bits tir_context;
5223  };
5224  
5225  struct mlx5_ifc_query_tir_in_bits {
5226  	u8         opcode[0x10];
5227  	u8         reserved_at_10[0x10];
5228  
5229  	u8         reserved_at_20[0x10];
5230  	u8         op_mod[0x10];
5231  
5232  	u8         reserved_at_40[0x8];
5233  	u8         tirn[0x18];
5234  
5235  	u8         reserved_at_60[0x20];
5236  };
5237  
5238  struct mlx5_ifc_query_srq_out_bits {
5239  	u8         status[0x8];
5240  	u8         reserved_at_8[0x18];
5241  
5242  	u8         syndrome[0x20];
5243  
5244  	u8         reserved_at_40[0x40];
5245  
5246  	struct mlx5_ifc_srqc_bits srq_context_entry;
5247  
5248  	u8         reserved_at_280[0x600];
5249  
5250  	u8         pas[][0x40];
5251  };
5252  
5253  struct mlx5_ifc_query_srq_in_bits {
5254  	u8         opcode[0x10];
5255  	u8         reserved_at_10[0x10];
5256  
5257  	u8         reserved_at_20[0x10];
5258  	u8         op_mod[0x10];
5259  
5260  	u8         reserved_at_40[0x8];
5261  	u8         srqn[0x18];
5262  
5263  	u8         reserved_at_60[0x20];
5264  };
5265  
5266  struct mlx5_ifc_query_sq_out_bits {
5267  	u8         status[0x8];
5268  	u8         reserved_at_8[0x18];
5269  
5270  	u8         syndrome[0x20];
5271  
5272  	u8         reserved_at_40[0xc0];
5273  
5274  	struct mlx5_ifc_sqc_bits sq_context;
5275  };
5276  
5277  struct mlx5_ifc_query_sq_in_bits {
5278  	u8         opcode[0x10];
5279  	u8         reserved_at_10[0x10];
5280  
5281  	u8         reserved_at_20[0x10];
5282  	u8         op_mod[0x10];
5283  
5284  	u8         reserved_at_40[0x8];
5285  	u8         sqn[0x18];
5286  
5287  	u8         reserved_at_60[0x20];
5288  };
5289  
5290  struct mlx5_ifc_query_special_contexts_out_bits {
5291  	u8         status[0x8];
5292  	u8         reserved_at_8[0x18];
5293  
5294  	u8         syndrome[0x20];
5295  
5296  	u8         dump_fill_mkey[0x20];
5297  
5298  	u8         resd_lkey[0x20];
5299  
5300  	u8         null_mkey[0x20];
5301  
5302  	u8	   terminate_scatter_list_mkey[0x20];
5303  
5304  	u8	   repeated_mkey[0x20];
5305  
5306  	u8         reserved_at_a0[0x20];
5307  };
5308  
5309  struct mlx5_ifc_query_special_contexts_in_bits {
5310  	u8         opcode[0x10];
5311  	u8         reserved_at_10[0x10];
5312  
5313  	u8         reserved_at_20[0x10];
5314  	u8         op_mod[0x10];
5315  
5316  	u8         reserved_at_40[0x40];
5317  };
5318  
5319  struct mlx5_ifc_query_scheduling_element_out_bits {
5320  	u8         opcode[0x10];
5321  	u8         reserved_at_10[0x10];
5322  
5323  	u8         reserved_at_20[0x10];
5324  	u8         op_mod[0x10];
5325  
5326  	u8         reserved_at_40[0xc0];
5327  
5328  	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5329  
5330  	u8         reserved_at_300[0x100];
5331  };
5332  
5333  enum {
5334  	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5335  	SCHEDULING_HIERARCHY_NIC = 0x3,
5336  };
5337  
5338  struct mlx5_ifc_query_scheduling_element_in_bits {
5339  	u8         opcode[0x10];
5340  	u8         reserved_at_10[0x10];
5341  
5342  	u8         reserved_at_20[0x10];
5343  	u8         op_mod[0x10];
5344  
5345  	u8         scheduling_hierarchy[0x8];
5346  	u8         reserved_at_48[0x18];
5347  
5348  	u8         scheduling_element_id[0x20];
5349  
5350  	u8         reserved_at_80[0x180];
5351  };
5352  
5353  struct mlx5_ifc_query_rqt_out_bits {
5354  	u8         status[0x8];
5355  	u8         reserved_at_8[0x18];
5356  
5357  	u8         syndrome[0x20];
5358  
5359  	u8         reserved_at_40[0xc0];
5360  
5361  	struct mlx5_ifc_rqtc_bits rqt_context;
5362  };
5363  
5364  struct mlx5_ifc_query_rqt_in_bits {
5365  	u8         opcode[0x10];
5366  	u8         reserved_at_10[0x10];
5367  
5368  	u8         reserved_at_20[0x10];
5369  	u8         op_mod[0x10];
5370  
5371  	u8         reserved_at_40[0x8];
5372  	u8         rqtn[0x18];
5373  
5374  	u8         reserved_at_60[0x20];
5375  };
5376  
5377  struct mlx5_ifc_query_rq_out_bits {
5378  	u8         status[0x8];
5379  	u8         reserved_at_8[0x18];
5380  
5381  	u8         syndrome[0x20];
5382  
5383  	u8         reserved_at_40[0xc0];
5384  
5385  	struct mlx5_ifc_rqc_bits rq_context;
5386  };
5387  
5388  struct mlx5_ifc_query_rq_in_bits {
5389  	u8         opcode[0x10];
5390  	u8         reserved_at_10[0x10];
5391  
5392  	u8         reserved_at_20[0x10];
5393  	u8         op_mod[0x10];
5394  
5395  	u8         reserved_at_40[0x8];
5396  	u8         rqn[0x18];
5397  
5398  	u8         reserved_at_60[0x20];
5399  };
5400  
5401  struct mlx5_ifc_query_roce_address_out_bits {
5402  	u8         status[0x8];
5403  	u8         reserved_at_8[0x18];
5404  
5405  	u8         syndrome[0x20];
5406  
5407  	u8         reserved_at_40[0x40];
5408  
5409  	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5410  };
5411  
5412  struct mlx5_ifc_query_roce_address_in_bits {
5413  	u8         opcode[0x10];
5414  	u8         reserved_at_10[0x10];
5415  
5416  	u8         reserved_at_20[0x10];
5417  	u8         op_mod[0x10];
5418  
5419  	u8         roce_address_index[0x10];
5420  	u8         reserved_at_50[0xc];
5421  	u8	   vhca_port_num[0x4];
5422  
5423  	u8         reserved_at_60[0x20];
5424  };
5425  
5426  struct mlx5_ifc_query_rmp_out_bits {
5427  	u8         status[0x8];
5428  	u8         reserved_at_8[0x18];
5429  
5430  	u8         syndrome[0x20];
5431  
5432  	u8         reserved_at_40[0xc0];
5433  
5434  	struct mlx5_ifc_rmpc_bits rmp_context;
5435  };
5436  
5437  struct mlx5_ifc_query_rmp_in_bits {
5438  	u8         opcode[0x10];
5439  	u8         reserved_at_10[0x10];
5440  
5441  	u8         reserved_at_20[0x10];
5442  	u8         op_mod[0x10];
5443  
5444  	u8         reserved_at_40[0x8];
5445  	u8         rmpn[0x18];
5446  
5447  	u8         reserved_at_60[0x20];
5448  };
5449  
5450  struct mlx5_ifc_cqe_error_syndrome_bits {
5451  	u8         hw_error_syndrome[0x8];
5452  	u8         hw_syndrome_type[0x4];
5453  	u8         reserved_at_c[0x4];
5454  	u8         vendor_error_syndrome[0x8];
5455  	u8         syndrome[0x8];
5456  };
5457  
5458  struct mlx5_ifc_qp_context_extension_bits {
5459  	u8         reserved_at_0[0x60];
5460  
5461  	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5462  
5463  	u8         reserved_at_80[0x580];
5464  };
5465  
5466  struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5467  	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5468  
5469  	u8         pas[0][0x40];
5470  };
5471  
5472  struct mlx5_ifc_qp_pas_list_in_bits {
5473  	struct mlx5_ifc_cmd_pas_bits pas[0];
5474  };
5475  
5476  union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5477  	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5478  	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5479  };
5480  
5481  struct mlx5_ifc_query_qp_out_bits {
5482  	u8         status[0x8];
5483  	u8         reserved_at_8[0x18];
5484  
5485  	u8         syndrome[0x20];
5486  
5487  	u8         reserved_at_40[0x40];
5488  
5489  	u8         opt_param_mask[0x20];
5490  
5491  	u8         ece[0x20];
5492  
5493  	struct mlx5_ifc_qpc_bits qpc;
5494  
5495  	u8         reserved_at_800[0x80];
5496  
5497  	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5498  };
5499  
5500  struct mlx5_ifc_query_qp_in_bits {
5501  	u8         opcode[0x10];
5502  	u8         reserved_at_10[0x10];
5503  
5504  	u8         reserved_at_20[0x10];
5505  	u8         op_mod[0x10];
5506  
5507  	u8         qpc_ext[0x1];
5508  	u8         reserved_at_41[0x7];
5509  	u8         qpn[0x18];
5510  
5511  	u8         reserved_at_60[0x20];
5512  };
5513  
5514  struct mlx5_ifc_query_q_counter_out_bits {
5515  	u8         status[0x8];
5516  	u8         reserved_at_8[0x18];
5517  
5518  	u8         syndrome[0x20];
5519  
5520  	u8         reserved_at_40[0x40];
5521  
5522  	u8         rx_write_requests[0x20];
5523  
5524  	u8         reserved_at_a0[0x20];
5525  
5526  	u8         rx_read_requests[0x20];
5527  
5528  	u8         reserved_at_e0[0x20];
5529  
5530  	u8         rx_atomic_requests[0x20];
5531  
5532  	u8         reserved_at_120[0x20];
5533  
5534  	u8         rx_dct_connect[0x20];
5535  
5536  	u8         reserved_at_160[0x20];
5537  
5538  	u8         out_of_buffer[0x20];
5539  
5540  	u8         reserved_at_1a0[0x20];
5541  
5542  	u8         out_of_sequence[0x20];
5543  
5544  	u8         reserved_at_1e0[0x20];
5545  
5546  	u8         duplicate_request[0x20];
5547  
5548  	u8         reserved_at_220[0x20];
5549  
5550  	u8         rnr_nak_retry_err[0x20];
5551  
5552  	u8         reserved_at_260[0x20];
5553  
5554  	u8         packet_seq_err[0x20];
5555  
5556  	u8         reserved_at_2a0[0x20];
5557  
5558  	u8         implied_nak_seq_err[0x20];
5559  
5560  	u8         reserved_at_2e0[0x20];
5561  
5562  	u8         local_ack_timeout_err[0x20];
5563  
5564  	u8         reserved_at_320[0xa0];
5565  
5566  	u8         resp_local_length_error[0x20];
5567  
5568  	u8         req_local_length_error[0x20];
5569  
5570  	u8         resp_local_qp_error[0x20];
5571  
5572  	u8         local_operation_error[0x20];
5573  
5574  	u8         resp_local_protection[0x20];
5575  
5576  	u8         req_local_protection[0x20];
5577  
5578  	u8         resp_cqe_error[0x20];
5579  
5580  	u8         req_cqe_error[0x20];
5581  
5582  	u8         req_mw_binding[0x20];
5583  
5584  	u8         req_bad_response[0x20];
5585  
5586  	u8         req_remote_invalid_request[0x20];
5587  
5588  	u8         resp_remote_invalid_request[0x20];
5589  
5590  	u8         req_remote_access_errors[0x20];
5591  
5592  	u8	   resp_remote_access_errors[0x20];
5593  
5594  	u8         req_remote_operation_errors[0x20];
5595  
5596  	u8         req_transport_retries_exceeded[0x20];
5597  
5598  	u8         cq_overflow[0x20];
5599  
5600  	u8         resp_cqe_flush_error[0x20];
5601  
5602  	u8         req_cqe_flush_error[0x20];
5603  
5604  	u8         reserved_at_620[0x20];
5605  
5606  	u8         roce_adp_retrans[0x20];
5607  
5608  	u8         roce_adp_retrans_to[0x20];
5609  
5610  	u8         roce_slow_restart[0x20];
5611  
5612  	u8         roce_slow_restart_cnps[0x20];
5613  
5614  	u8         roce_slow_restart_trans[0x20];
5615  
5616  	u8         reserved_at_6e0[0x120];
5617  };
5618  
5619  struct mlx5_ifc_query_q_counter_in_bits {
5620  	u8         opcode[0x10];
5621  	u8         reserved_at_10[0x10];
5622  
5623  	u8         reserved_at_20[0x10];
5624  	u8         op_mod[0x10];
5625  
5626  	u8         other_vport[0x1];
5627  	u8         reserved_at_41[0xf];
5628  	u8         vport_number[0x10];
5629  
5630  	u8         reserved_at_60[0x60];
5631  
5632  	u8         clear[0x1];
5633  	u8         aggregate[0x1];
5634  	u8         reserved_at_c2[0x1e];
5635  
5636  	u8         reserved_at_e0[0x18];
5637  	u8         counter_set_id[0x8];
5638  };
5639  
5640  struct mlx5_ifc_query_pages_out_bits {
5641  	u8         status[0x8];
5642  	u8         reserved_at_8[0x18];
5643  
5644  	u8         syndrome[0x20];
5645  
5646  	u8         embedded_cpu_function[0x1];
5647  	u8         reserved_at_41[0xf];
5648  	u8         function_id[0x10];
5649  
5650  	u8         num_pages[0x20];
5651  };
5652  
5653  enum {
5654  	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5655  	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5656  	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5657  };
5658  
5659  struct mlx5_ifc_query_pages_in_bits {
5660  	u8         opcode[0x10];
5661  	u8         reserved_at_10[0x10];
5662  
5663  	u8         reserved_at_20[0x10];
5664  	u8         op_mod[0x10];
5665  
5666  	u8         embedded_cpu_function[0x1];
5667  	u8         reserved_at_41[0xf];
5668  	u8         function_id[0x10];
5669  
5670  	u8         reserved_at_60[0x20];
5671  };
5672  
5673  struct mlx5_ifc_query_nic_vport_context_out_bits {
5674  	u8         status[0x8];
5675  	u8         reserved_at_8[0x18];
5676  
5677  	u8         syndrome[0x20];
5678  
5679  	u8         reserved_at_40[0x40];
5680  
5681  	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5682  };
5683  
5684  struct mlx5_ifc_query_nic_vport_context_in_bits {
5685  	u8         opcode[0x10];
5686  	u8         reserved_at_10[0x10];
5687  
5688  	u8         reserved_at_20[0x10];
5689  	u8         op_mod[0x10];
5690  
5691  	u8         other_vport[0x1];
5692  	u8         reserved_at_41[0xf];
5693  	u8         vport_number[0x10];
5694  
5695  	u8         reserved_at_60[0x5];
5696  	u8         allowed_list_type[0x3];
5697  	u8         reserved_at_68[0x18];
5698  };
5699  
5700  struct mlx5_ifc_query_mkey_out_bits {
5701  	u8         status[0x8];
5702  	u8         reserved_at_8[0x18];
5703  
5704  	u8         syndrome[0x20];
5705  
5706  	u8         reserved_at_40[0x40];
5707  
5708  	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5709  
5710  	u8         reserved_at_280[0x600];
5711  
5712  	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5713  
5714  	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5715  };
5716  
5717  struct mlx5_ifc_query_mkey_in_bits {
5718  	u8         opcode[0x10];
5719  	u8         reserved_at_10[0x10];
5720  
5721  	u8         reserved_at_20[0x10];
5722  	u8         op_mod[0x10];
5723  
5724  	u8         reserved_at_40[0x8];
5725  	u8         mkey_index[0x18];
5726  
5727  	u8         pg_access[0x1];
5728  	u8         reserved_at_61[0x1f];
5729  };
5730  
5731  struct mlx5_ifc_query_mad_demux_out_bits {
5732  	u8         status[0x8];
5733  	u8         reserved_at_8[0x18];
5734  
5735  	u8         syndrome[0x20];
5736  
5737  	u8         reserved_at_40[0x40];
5738  
5739  	u8         mad_dumux_parameters_block[0x20];
5740  };
5741  
5742  struct mlx5_ifc_query_mad_demux_in_bits {
5743  	u8         opcode[0x10];
5744  	u8         reserved_at_10[0x10];
5745  
5746  	u8         reserved_at_20[0x10];
5747  	u8         op_mod[0x10];
5748  
5749  	u8         reserved_at_40[0x40];
5750  };
5751  
5752  struct mlx5_ifc_query_l2_table_entry_out_bits {
5753  	u8         status[0x8];
5754  	u8         reserved_at_8[0x18];
5755  
5756  	u8         syndrome[0x20];
5757  
5758  	u8         reserved_at_40[0xa0];
5759  
5760  	u8         reserved_at_e0[0x13];
5761  	u8         vlan_valid[0x1];
5762  	u8         vlan[0xc];
5763  
5764  	struct mlx5_ifc_mac_address_layout_bits mac_address;
5765  
5766  	u8         reserved_at_140[0xc0];
5767  };
5768  
5769  struct mlx5_ifc_query_l2_table_entry_in_bits {
5770  	u8         opcode[0x10];
5771  	u8         reserved_at_10[0x10];
5772  
5773  	u8         reserved_at_20[0x10];
5774  	u8         op_mod[0x10];
5775  
5776  	u8         reserved_at_40[0x60];
5777  
5778  	u8         reserved_at_a0[0x8];
5779  	u8         table_index[0x18];
5780  
5781  	u8         reserved_at_c0[0x140];
5782  };
5783  
5784  struct mlx5_ifc_query_issi_out_bits {
5785  	u8         status[0x8];
5786  	u8         reserved_at_8[0x18];
5787  
5788  	u8         syndrome[0x20];
5789  
5790  	u8         reserved_at_40[0x10];
5791  	u8         current_issi[0x10];
5792  
5793  	u8         reserved_at_60[0xa0];
5794  
5795  	u8         reserved_at_100[76][0x8];
5796  	u8         supported_issi_dw0[0x20];
5797  };
5798  
5799  struct mlx5_ifc_query_issi_in_bits {
5800  	u8         opcode[0x10];
5801  	u8         reserved_at_10[0x10];
5802  
5803  	u8         reserved_at_20[0x10];
5804  	u8         op_mod[0x10];
5805  
5806  	u8         reserved_at_40[0x40];
5807  };
5808  
5809  struct mlx5_ifc_set_driver_version_out_bits {
5810  	u8         status[0x8];
5811  	u8         reserved_0[0x18];
5812  
5813  	u8         syndrome[0x20];
5814  	u8         reserved_1[0x40];
5815  };
5816  
5817  struct mlx5_ifc_set_driver_version_in_bits {
5818  	u8         opcode[0x10];
5819  	u8         reserved_0[0x10];
5820  
5821  	u8         reserved_1[0x10];
5822  	u8         op_mod[0x10];
5823  
5824  	u8         reserved_2[0x40];
5825  	u8         driver_version[64][0x8];
5826  };
5827  
5828  struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5829  	u8         status[0x8];
5830  	u8         reserved_at_8[0x18];
5831  
5832  	u8         syndrome[0x20];
5833  
5834  	u8         reserved_at_40[0x40];
5835  
5836  	struct mlx5_ifc_pkey_bits pkey[];
5837  };
5838  
5839  struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5840  	u8         opcode[0x10];
5841  	u8         reserved_at_10[0x10];
5842  
5843  	u8         reserved_at_20[0x10];
5844  	u8         op_mod[0x10];
5845  
5846  	u8         other_vport[0x1];
5847  	u8         reserved_at_41[0xb];
5848  	u8         port_num[0x4];
5849  	u8         vport_number[0x10];
5850  
5851  	u8         reserved_at_60[0x10];
5852  	u8         pkey_index[0x10];
5853  };
5854  
5855  enum {
5856  	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
5857  	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
5858  	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
5859  };
5860  
5861  struct mlx5_ifc_query_hca_vport_gid_out_bits {
5862  	u8         status[0x8];
5863  	u8         reserved_at_8[0x18];
5864  
5865  	u8         syndrome[0x20];
5866  
5867  	u8         reserved_at_40[0x20];
5868  
5869  	u8         gids_num[0x10];
5870  	u8         reserved_at_70[0x10];
5871  
5872  	struct mlx5_ifc_array128_auto_bits gid[];
5873  };
5874  
5875  struct mlx5_ifc_query_hca_vport_gid_in_bits {
5876  	u8         opcode[0x10];
5877  	u8         reserved_at_10[0x10];
5878  
5879  	u8         reserved_at_20[0x10];
5880  	u8         op_mod[0x10];
5881  
5882  	u8         other_vport[0x1];
5883  	u8         reserved_at_41[0xb];
5884  	u8         port_num[0x4];
5885  	u8         vport_number[0x10];
5886  
5887  	u8         reserved_at_60[0x10];
5888  	u8         gid_index[0x10];
5889  };
5890  
5891  struct mlx5_ifc_query_hca_vport_context_out_bits {
5892  	u8         status[0x8];
5893  	u8         reserved_at_8[0x18];
5894  
5895  	u8         syndrome[0x20];
5896  
5897  	u8         reserved_at_40[0x40];
5898  
5899  	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5900  };
5901  
5902  struct mlx5_ifc_query_hca_vport_context_in_bits {
5903  	u8         opcode[0x10];
5904  	u8         reserved_at_10[0x10];
5905  
5906  	u8         reserved_at_20[0x10];
5907  	u8         op_mod[0x10];
5908  
5909  	u8         other_vport[0x1];
5910  	u8         reserved_at_41[0xb];
5911  	u8         port_num[0x4];
5912  	u8         vport_number[0x10];
5913  
5914  	u8         reserved_at_60[0x20];
5915  };
5916  
5917  struct mlx5_ifc_query_hca_cap_out_bits {
5918  	u8         status[0x8];
5919  	u8         reserved_at_8[0x18];
5920  
5921  	u8         syndrome[0x20];
5922  
5923  	u8         reserved_at_40[0x40];
5924  
5925  	union mlx5_ifc_hca_cap_union_bits capability;
5926  };
5927  
5928  struct mlx5_ifc_query_hca_cap_in_bits {
5929  	u8         opcode[0x10];
5930  	u8         reserved_at_10[0x10];
5931  
5932  	u8         reserved_at_20[0x10];
5933  	u8         op_mod[0x10];
5934  
5935  	u8         other_function[0x1];
5936  	u8         ec_vf_function[0x1];
5937  	u8         reserved_at_42[0xe];
5938  	u8         function_id[0x10];
5939  
5940  	u8         reserved_at_60[0x20];
5941  };
5942  
5943  struct mlx5_ifc_other_hca_cap_bits {
5944  	u8         roce[0x1];
5945  	u8         reserved_at_1[0x27f];
5946  };
5947  
5948  struct mlx5_ifc_query_other_hca_cap_out_bits {
5949  	u8         status[0x8];
5950  	u8         reserved_at_8[0x18];
5951  
5952  	u8         syndrome[0x20];
5953  
5954  	u8         reserved_at_40[0x40];
5955  
5956  	struct     mlx5_ifc_other_hca_cap_bits other_capability;
5957  };
5958  
5959  struct mlx5_ifc_query_other_hca_cap_in_bits {
5960  	u8         opcode[0x10];
5961  	u8         reserved_at_10[0x10];
5962  
5963  	u8         reserved_at_20[0x10];
5964  	u8         op_mod[0x10];
5965  
5966  	u8         reserved_at_40[0x10];
5967  	u8         function_id[0x10];
5968  
5969  	u8         reserved_at_60[0x20];
5970  };
5971  
5972  struct mlx5_ifc_modify_other_hca_cap_out_bits {
5973  	u8         status[0x8];
5974  	u8         reserved_at_8[0x18];
5975  
5976  	u8         syndrome[0x20];
5977  
5978  	u8         reserved_at_40[0x40];
5979  };
5980  
5981  struct mlx5_ifc_modify_other_hca_cap_in_bits {
5982  	u8         opcode[0x10];
5983  	u8         reserved_at_10[0x10];
5984  
5985  	u8         reserved_at_20[0x10];
5986  	u8         op_mod[0x10];
5987  
5988  	u8         reserved_at_40[0x10];
5989  	u8         function_id[0x10];
5990  	u8         field_select[0x20];
5991  
5992  	struct     mlx5_ifc_other_hca_cap_bits other_capability;
5993  };
5994  
5995  struct mlx5_ifc_flow_table_context_bits {
5996  	u8         reformat_en[0x1];
5997  	u8         decap_en[0x1];
5998  	u8         sw_owner[0x1];
5999  	u8         termination_table[0x1];
6000  	u8         table_miss_action[0x4];
6001  	u8         level[0x8];
6002  	u8         reserved_at_10[0x8];
6003  	u8         log_size[0x8];
6004  
6005  	u8         reserved_at_20[0x8];
6006  	u8         table_miss_id[0x18];
6007  
6008  	u8         reserved_at_40[0x8];
6009  	u8         lag_master_next_table_id[0x18];
6010  
6011  	u8         reserved_at_60[0x60];
6012  
6013  	u8         sw_owner_icm_root_1[0x40];
6014  
6015  	u8         sw_owner_icm_root_0[0x40];
6016  
6017  };
6018  
6019  struct mlx5_ifc_query_flow_table_out_bits {
6020  	u8         status[0x8];
6021  	u8         reserved_at_8[0x18];
6022  
6023  	u8         syndrome[0x20];
6024  
6025  	u8         reserved_at_40[0x80];
6026  
6027  	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6028  };
6029  
6030  struct mlx5_ifc_query_flow_table_in_bits {
6031  	u8         opcode[0x10];
6032  	u8         reserved_at_10[0x10];
6033  
6034  	u8         reserved_at_20[0x10];
6035  	u8         op_mod[0x10];
6036  
6037  	u8         reserved_at_40[0x40];
6038  
6039  	u8         table_type[0x8];
6040  	u8         reserved_at_88[0x18];
6041  
6042  	u8         reserved_at_a0[0x8];
6043  	u8         table_id[0x18];
6044  
6045  	u8         reserved_at_c0[0x140];
6046  };
6047  
6048  struct mlx5_ifc_query_fte_out_bits {
6049  	u8         status[0x8];
6050  	u8         reserved_at_8[0x18];
6051  
6052  	u8         syndrome[0x20];
6053  
6054  	u8         reserved_at_40[0x1c0];
6055  
6056  	struct mlx5_ifc_flow_context_bits flow_context;
6057  };
6058  
6059  struct mlx5_ifc_query_fte_in_bits {
6060  	u8         opcode[0x10];
6061  	u8         reserved_at_10[0x10];
6062  
6063  	u8         reserved_at_20[0x10];
6064  	u8         op_mod[0x10];
6065  
6066  	u8         reserved_at_40[0x40];
6067  
6068  	u8         table_type[0x8];
6069  	u8         reserved_at_88[0x18];
6070  
6071  	u8         reserved_at_a0[0x8];
6072  	u8         table_id[0x18];
6073  
6074  	u8         reserved_at_c0[0x40];
6075  
6076  	u8         flow_index[0x20];
6077  
6078  	u8         reserved_at_120[0xe0];
6079  };
6080  
6081  struct mlx5_ifc_match_definer_format_0_bits {
6082  	u8         reserved_at_0[0x100];
6083  
6084  	u8         metadata_reg_c_0[0x20];
6085  
6086  	u8         metadata_reg_c_1[0x20];
6087  
6088  	u8         outer_dmac_47_16[0x20];
6089  
6090  	u8         outer_dmac_15_0[0x10];
6091  	u8         outer_ethertype[0x10];
6092  
6093  	u8         reserved_at_180[0x1];
6094  	u8         sx_sniffer[0x1];
6095  	u8         functional_lb[0x1];
6096  	u8         outer_ip_frag[0x1];
6097  	u8         outer_qp_type[0x2];
6098  	u8         outer_encap_type[0x2];
6099  	u8         port_number[0x2];
6100  	u8         outer_l3_type[0x2];
6101  	u8         outer_l4_type[0x2];
6102  	u8         outer_first_vlan_type[0x2];
6103  	u8         outer_first_vlan_prio[0x3];
6104  	u8         outer_first_vlan_cfi[0x1];
6105  	u8         outer_first_vlan_vid[0xc];
6106  
6107  	u8         outer_l4_type_ext[0x4];
6108  	u8         reserved_at_1a4[0x2];
6109  	u8         outer_ipsec_layer[0x2];
6110  	u8         outer_l2_type[0x2];
6111  	u8         force_lb[0x1];
6112  	u8         outer_l2_ok[0x1];
6113  	u8         outer_l3_ok[0x1];
6114  	u8         outer_l4_ok[0x1];
6115  	u8         outer_second_vlan_type[0x2];
6116  	u8         outer_second_vlan_prio[0x3];
6117  	u8         outer_second_vlan_cfi[0x1];
6118  	u8         outer_second_vlan_vid[0xc];
6119  
6120  	u8         outer_smac_47_16[0x20];
6121  
6122  	u8         outer_smac_15_0[0x10];
6123  	u8         inner_ipv4_checksum_ok[0x1];
6124  	u8         inner_l4_checksum_ok[0x1];
6125  	u8         outer_ipv4_checksum_ok[0x1];
6126  	u8         outer_l4_checksum_ok[0x1];
6127  	u8         inner_l3_ok[0x1];
6128  	u8         inner_l4_ok[0x1];
6129  	u8         outer_l3_ok_duplicate[0x1];
6130  	u8         outer_l4_ok_duplicate[0x1];
6131  	u8         outer_tcp_cwr[0x1];
6132  	u8         outer_tcp_ece[0x1];
6133  	u8         outer_tcp_urg[0x1];
6134  	u8         outer_tcp_ack[0x1];
6135  	u8         outer_tcp_psh[0x1];
6136  	u8         outer_tcp_rst[0x1];
6137  	u8         outer_tcp_syn[0x1];
6138  	u8         outer_tcp_fin[0x1];
6139  };
6140  
6141  struct mlx5_ifc_match_definer_format_22_bits {
6142  	u8         reserved_at_0[0x100];
6143  
6144  	u8         outer_ip_src_addr[0x20];
6145  
6146  	u8         outer_ip_dest_addr[0x20];
6147  
6148  	u8         outer_l4_sport[0x10];
6149  	u8         outer_l4_dport[0x10];
6150  
6151  	u8         reserved_at_160[0x1];
6152  	u8         sx_sniffer[0x1];
6153  	u8         functional_lb[0x1];
6154  	u8         outer_ip_frag[0x1];
6155  	u8         outer_qp_type[0x2];
6156  	u8         outer_encap_type[0x2];
6157  	u8         port_number[0x2];
6158  	u8         outer_l3_type[0x2];
6159  	u8         outer_l4_type[0x2];
6160  	u8         outer_first_vlan_type[0x2];
6161  	u8         outer_first_vlan_prio[0x3];
6162  	u8         outer_first_vlan_cfi[0x1];
6163  	u8         outer_first_vlan_vid[0xc];
6164  
6165  	u8         metadata_reg_c_0[0x20];
6166  
6167  	u8         outer_dmac_47_16[0x20];
6168  
6169  	u8         outer_smac_47_16[0x20];
6170  
6171  	u8         outer_smac_15_0[0x10];
6172  	u8         outer_dmac_15_0[0x10];
6173  };
6174  
6175  struct mlx5_ifc_match_definer_format_23_bits {
6176  	u8         reserved_at_0[0x100];
6177  
6178  	u8         inner_ip_src_addr[0x20];
6179  
6180  	u8         inner_ip_dest_addr[0x20];
6181  
6182  	u8         inner_l4_sport[0x10];
6183  	u8         inner_l4_dport[0x10];
6184  
6185  	u8         reserved_at_160[0x1];
6186  	u8         sx_sniffer[0x1];
6187  	u8         functional_lb[0x1];
6188  	u8         inner_ip_frag[0x1];
6189  	u8         inner_qp_type[0x2];
6190  	u8         inner_encap_type[0x2];
6191  	u8         port_number[0x2];
6192  	u8         inner_l3_type[0x2];
6193  	u8         inner_l4_type[0x2];
6194  	u8         inner_first_vlan_type[0x2];
6195  	u8         inner_first_vlan_prio[0x3];
6196  	u8         inner_first_vlan_cfi[0x1];
6197  	u8         inner_first_vlan_vid[0xc];
6198  
6199  	u8         tunnel_header_0[0x20];
6200  
6201  	u8         inner_dmac_47_16[0x20];
6202  
6203  	u8         inner_smac_47_16[0x20];
6204  
6205  	u8         inner_smac_15_0[0x10];
6206  	u8         inner_dmac_15_0[0x10];
6207  };
6208  
6209  struct mlx5_ifc_match_definer_format_29_bits {
6210  	u8         reserved_at_0[0xc0];
6211  
6212  	u8         outer_ip_dest_addr[0x80];
6213  
6214  	u8         outer_ip_src_addr[0x80];
6215  
6216  	u8         outer_l4_sport[0x10];
6217  	u8         outer_l4_dport[0x10];
6218  
6219  	u8         reserved_at_1e0[0x20];
6220  };
6221  
6222  struct mlx5_ifc_match_definer_format_30_bits {
6223  	u8         reserved_at_0[0xa0];
6224  
6225  	u8         outer_ip_dest_addr[0x80];
6226  
6227  	u8         outer_ip_src_addr[0x80];
6228  
6229  	u8         outer_dmac_47_16[0x20];
6230  
6231  	u8         outer_smac_47_16[0x20];
6232  
6233  	u8         outer_smac_15_0[0x10];
6234  	u8         outer_dmac_15_0[0x10];
6235  };
6236  
6237  struct mlx5_ifc_match_definer_format_31_bits {
6238  	u8         reserved_at_0[0xc0];
6239  
6240  	u8         inner_ip_dest_addr[0x80];
6241  
6242  	u8         inner_ip_src_addr[0x80];
6243  
6244  	u8         inner_l4_sport[0x10];
6245  	u8         inner_l4_dport[0x10];
6246  
6247  	u8         reserved_at_1e0[0x20];
6248  };
6249  
6250  struct mlx5_ifc_match_definer_format_32_bits {
6251  	u8         reserved_at_0[0xa0];
6252  
6253  	u8         inner_ip_dest_addr[0x80];
6254  
6255  	u8         inner_ip_src_addr[0x80];
6256  
6257  	u8         inner_dmac_47_16[0x20];
6258  
6259  	u8         inner_smac_47_16[0x20];
6260  
6261  	u8         inner_smac_15_0[0x10];
6262  	u8         inner_dmac_15_0[0x10];
6263  };
6264  
6265  enum {
6266  	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6267  };
6268  
6269  #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6270  #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6271  #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6272  #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6273  
6274  struct mlx5_ifc_match_definer_match_mask_bits {
6275  	u8         reserved_at_1c0[5][0x20];
6276  	u8         match_dw_8[0x20];
6277  	u8         match_dw_7[0x20];
6278  	u8         match_dw_6[0x20];
6279  	u8         match_dw_5[0x20];
6280  	u8         match_dw_4[0x20];
6281  	u8         match_dw_3[0x20];
6282  	u8         match_dw_2[0x20];
6283  	u8         match_dw_1[0x20];
6284  	u8         match_dw_0[0x20];
6285  
6286  	u8         match_byte_7[0x8];
6287  	u8         match_byte_6[0x8];
6288  	u8         match_byte_5[0x8];
6289  	u8         match_byte_4[0x8];
6290  
6291  	u8         match_byte_3[0x8];
6292  	u8         match_byte_2[0x8];
6293  	u8         match_byte_1[0x8];
6294  	u8         match_byte_0[0x8];
6295  };
6296  
6297  struct mlx5_ifc_match_definer_bits {
6298  	u8         modify_field_select[0x40];
6299  
6300  	u8         reserved_at_40[0x40];
6301  
6302  	u8         reserved_at_80[0x10];
6303  	u8         format_id[0x10];
6304  
6305  	u8         reserved_at_a0[0x60];
6306  
6307  	u8         format_select_dw3[0x8];
6308  	u8         format_select_dw2[0x8];
6309  	u8         format_select_dw1[0x8];
6310  	u8         format_select_dw0[0x8];
6311  
6312  	u8         format_select_dw7[0x8];
6313  	u8         format_select_dw6[0x8];
6314  	u8         format_select_dw5[0x8];
6315  	u8         format_select_dw4[0x8];
6316  
6317  	u8         reserved_at_100[0x18];
6318  	u8         format_select_dw8[0x8];
6319  
6320  	u8         reserved_at_120[0x20];
6321  
6322  	u8         format_select_byte3[0x8];
6323  	u8         format_select_byte2[0x8];
6324  	u8         format_select_byte1[0x8];
6325  	u8         format_select_byte0[0x8];
6326  
6327  	u8         format_select_byte7[0x8];
6328  	u8         format_select_byte6[0x8];
6329  	u8         format_select_byte5[0x8];
6330  	u8         format_select_byte4[0x8];
6331  
6332  	u8         reserved_at_180[0x40];
6333  
6334  	union {
6335  		struct {
6336  			u8         match_mask[16][0x20];
6337  		};
6338  		struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6339  	};
6340  };
6341  
6342  struct mlx5_ifc_general_obj_create_param_bits {
6343  	u8         alias_object[0x1];
6344  	u8         reserved_at_1[0x2];
6345  	u8         log_obj_range[0x5];
6346  	u8         reserved_at_8[0x18];
6347  };
6348  
6349  struct mlx5_ifc_general_obj_query_param_bits {
6350  	u8         alias_object[0x1];
6351  	u8         obj_offset[0x1f];
6352  };
6353  
6354  struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6355  	u8         opcode[0x10];
6356  	u8         uid[0x10];
6357  
6358  	u8         vhca_tunnel_id[0x10];
6359  	u8         obj_type[0x10];
6360  
6361  	u8         obj_id[0x20];
6362  
6363  	union {
6364  		struct mlx5_ifc_general_obj_create_param_bits create;
6365  		struct mlx5_ifc_general_obj_query_param_bits query;
6366  	} op_param;
6367  };
6368  
6369  struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6370  	u8         status[0x8];
6371  	u8         reserved_at_8[0x18];
6372  
6373  	u8         syndrome[0x20];
6374  
6375  	u8         obj_id[0x20];
6376  
6377  	u8         reserved_at_60[0x20];
6378  };
6379  
6380  struct mlx5_ifc_modify_header_arg_bits {
6381  	u8         reserved_at_0[0x80];
6382  
6383  	u8         reserved_at_80[0x8];
6384  	u8         access_pd[0x18];
6385  };
6386  
6387  struct mlx5_ifc_create_modify_header_arg_in_bits {
6388  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6389  	struct mlx5_ifc_modify_header_arg_bits arg;
6390  };
6391  
6392  struct mlx5_ifc_create_match_definer_in_bits {
6393  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6394  
6395  	struct mlx5_ifc_match_definer_bits obj_context;
6396  };
6397  
6398  struct mlx5_ifc_create_match_definer_out_bits {
6399  	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6400  };
6401  
6402  enum {
6403  	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6404  	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6405  	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6406  	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6407  	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6408  	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6409  	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6410  };
6411  
6412  struct mlx5_ifc_query_flow_group_out_bits {
6413  	u8         status[0x8];
6414  	u8         reserved_at_8[0x18];
6415  
6416  	u8         syndrome[0x20];
6417  
6418  	u8         reserved_at_40[0xa0];
6419  
6420  	u8         start_flow_index[0x20];
6421  
6422  	u8         reserved_at_100[0x20];
6423  
6424  	u8         end_flow_index[0x20];
6425  
6426  	u8         reserved_at_140[0xa0];
6427  
6428  	u8         reserved_at_1e0[0x18];
6429  	u8         match_criteria_enable[0x8];
6430  
6431  	struct mlx5_ifc_fte_match_param_bits match_criteria;
6432  
6433  	u8         reserved_at_1200[0xe00];
6434  };
6435  
6436  struct mlx5_ifc_query_flow_group_in_bits {
6437  	u8         opcode[0x10];
6438  	u8         reserved_at_10[0x10];
6439  
6440  	u8         reserved_at_20[0x10];
6441  	u8         op_mod[0x10];
6442  
6443  	u8         reserved_at_40[0x40];
6444  
6445  	u8         table_type[0x8];
6446  	u8         reserved_at_88[0x18];
6447  
6448  	u8         reserved_at_a0[0x8];
6449  	u8         table_id[0x18];
6450  
6451  	u8         group_id[0x20];
6452  
6453  	u8         reserved_at_e0[0x120];
6454  };
6455  
6456  struct mlx5_ifc_query_flow_counter_out_bits {
6457  	u8         status[0x8];
6458  	u8         reserved_at_8[0x18];
6459  
6460  	u8         syndrome[0x20];
6461  
6462  	u8         reserved_at_40[0x40];
6463  
6464  	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6465  };
6466  
6467  struct mlx5_ifc_query_flow_counter_in_bits {
6468  	u8         opcode[0x10];
6469  	u8         reserved_at_10[0x10];
6470  
6471  	u8         reserved_at_20[0x10];
6472  	u8         op_mod[0x10];
6473  
6474  	u8         reserved_at_40[0x80];
6475  
6476  	u8         clear[0x1];
6477  	u8         reserved_at_c1[0xf];
6478  	u8         num_of_counters[0x10];
6479  
6480  	u8         flow_counter_id[0x20];
6481  };
6482  
6483  struct mlx5_ifc_query_esw_vport_context_out_bits {
6484  	u8         status[0x8];
6485  	u8         reserved_at_8[0x18];
6486  
6487  	u8         syndrome[0x20];
6488  
6489  	u8         reserved_at_40[0x40];
6490  
6491  	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6492  };
6493  
6494  struct mlx5_ifc_query_esw_vport_context_in_bits {
6495  	u8         opcode[0x10];
6496  	u8         reserved_at_10[0x10];
6497  
6498  	u8         reserved_at_20[0x10];
6499  	u8         op_mod[0x10];
6500  
6501  	u8         other_vport[0x1];
6502  	u8         reserved_at_41[0xf];
6503  	u8         vport_number[0x10];
6504  
6505  	u8         reserved_at_60[0x20];
6506  };
6507  
6508  struct mlx5_ifc_modify_esw_vport_context_out_bits {
6509  	u8         status[0x8];
6510  	u8         reserved_at_8[0x18];
6511  
6512  	u8         syndrome[0x20];
6513  
6514  	u8         reserved_at_40[0x40];
6515  };
6516  
6517  struct mlx5_ifc_esw_vport_context_fields_select_bits {
6518  	u8         reserved_at_0[0x1b];
6519  	u8         fdb_to_vport_reg_c_id[0x1];
6520  	u8         vport_cvlan_insert[0x1];
6521  	u8         vport_svlan_insert[0x1];
6522  	u8         vport_cvlan_strip[0x1];
6523  	u8         vport_svlan_strip[0x1];
6524  };
6525  
6526  struct mlx5_ifc_modify_esw_vport_context_in_bits {
6527  	u8         opcode[0x10];
6528  	u8         reserved_at_10[0x10];
6529  
6530  	u8         reserved_at_20[0x10];
6531  	u8         op_mod[0x10];
6532  
6533  	u8         other_vport[0x1];
6534  	u8         reserved_at_41[0xf];
6535  	u8         vport_number[0x10];
6536  
6537  	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6538  
6539  	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6540  };
6541  
6542  struct mlx5_ifc_query_eq_out_bits {
6543  	u8         status[0x8];
6544  	u8         reserved_at_8[0x18];
6545  
6546  	u8         syndrome[0x20];
6547  
6548  	u8         reserved_at_40[0x40];
6549  
6550  	struct mlx5_ifc_eqc_bits eq_context_entry;
6551  
6552  	u8         reserved_at_280[0x40];
6553  
6554  	u8         event_bitmask[0x40];
6555  
6556  	u8         reserved_at_300[0x580];
6557  
6558  	u8         pas[][0x40];
6559  };
6560  
6561  struct mlx5_ifc_query_eq_in_bits {
6562  	u8         opcode[0x10];
6563  	u8         reserved_at_10[0x10];
6564  
6565  	u8         reserved_at_20[0x10];
6566  	u8         op_mod[0x10];
6567  
6568  	u8         reserved_at_40[0x18];
6569  	u8         eq_number[0x8];
6570  
6571  	u8         reserved_at_60[0x20];
6572  };
6573  
6574  struct mlx5_ifc_packet_reformat_context_in_bits {
6575  	u8         reformat_type[0x8];
6576  	u8         reserved_at_8[0x4];
6577  	u8         reformat_param_0[0x4];
6578  	u8         reserved_at_10[0x6];
6579  	u8         reformat_data_size[0xa];
6580  
6581  	u8         reformat_param_1[0x8];
6582  	u8         reserved_at_28[0x8];
6583  	u8         reformat_data[2][0x8];
6584  
6585  	u8         more_reformat_data[][0x8];
6586  };
6587  
6588  struct mlx5_ifc_query_packet_reformat_context_out_bits {
6589  	u8         status[0x8];
6590  	u8         reserved_at_8[0x18];
6591  
6592  	u8         syndrome[0x20];
6593  
6594  	u8         reserved_at_40[0xa0];
6595  
6596  	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6597  };
6598  
6599  struct mlx5_ifc_query_packet_reformat_context_in_bits {
6600  	u8         opcode[0x10];
6601  	u8         reserved_at_10[0x10];
6602  
6603  	u8         reserved_at_20[0x10];
6604  	u8         op_mod[0x10];
6605  
6606  	u8         packet_reformat_id[0x20];
6607  
6608  	u8         reserved_at_60[0xa0];
6609  };
6610  
6611  struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6612  	u8         status[0x8];
6613  	u8         reserved_at_8[0x18];
6614  
6615  	u8         syndrome[0x20];
6616  
6617  	u8         packet_reformat_id[0x20];
6618  
6619  	u8         reserved_at_60[0x20];
6620  };
6621  
6622  enum {
6623  	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6624  	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6625  	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6626  };
6627  
6628  enum mlx5_reformat_ctx_type {
6629  	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6630  	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6631  	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6632  	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6633  	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6634  	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
6635  	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
6636  	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
6637  	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
6638  	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
6639  	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
6640  	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
6641  	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
6642  	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6643  	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6644  	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6645  	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
6646  };
6647  
6648  struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6649  	u8         opcode[0x10];
6650  	u8         reserved_at_10[0x10];
6651  
6652  	u8         reserved_at_20[0x10];
6653  	u8         op_mod[0x10];
6654  
6655  	u8         reserved_at_40[0xa0];
6656  
6657  	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6658  };
6659  
6660  struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6661  	u8         status[0x8];
6662  	u8         reserved_at_8[0x18];
6663  
6664  	u8         syndrome[0x20];
6665  
6666  	u8         reserved_at_40[0x40];
6667  };
6668  
6669  struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6670  	u8         opcode[0x10];
6671  	u8         reserved_at_10[0x10];
6672  
6673  	u8         reserved_20[0x10];
6674  	u8         op_mod[0x10];
6675  
6676  	u8         packet_reformat_id[0x20];
6677  
6678  	u8         reserved_60[0x20];
6679  };
6680  
6681  struct mlx5_ifc_set_action_in_bits {
6682  	u8         action_type[0x4];
6683  	u8         field[0xc];
6684  	u8         reserved_at_10[0x3];
6685  	u8         offset[0x5];
6686  	u8         reserved_at_18[0x3];
6687  	u8         length[0x5];
6688  
6689  	u8         data[0x20];
6690  };
6691  
6692  struct mlx5_ifc_add_action_in_bits {
6693  	u8         action_type[0x4];
6694  	u8         field[0xc];
6695  	u8         reserved_at_10[0x10];
6696  
6697  	u8         data[0x20];
6698  };
6699  
6700  struct mlx5_ifc_copy_action_in_bits {
6701  	u8         action_type[0x4];
6702  	u8         src_field[0xc];
6703  	u8         reserved_at_10[0x3];
6704  	u8         src_offset[0x5];
6705  	u8         reserved_at_18[0x3];
6706  	u8         length[0x5];
6707  
6708  	u8         reserved_at_20[0x4];
6709  	u8         dst_field[0xc];
6710  	u8         reserved_at_30[0x3];
6711  	u8         dst_offset[0x5];
6712  	u8         reserved_at_38[0x8];
6713  };
6714  
6715  union mlx5_ifc_set_add_copy_action_in_auto_bits {
6716  	struct mlx5_ifc_set_action_in_bits  set_action_in;
6717  	struct mlx5_ifc_add_action_in_bits  add_action_in;
6718  	struct mlx5_ifc_copy_action_in_bits copy_action_in;
6719  	u8         reserved_at_0[0x40];
6720  };
6721  
6722  enum {
6723  	MLX5_ACTION_TYPE_SET   = 0x1,
6724  	MLX5_ACTION_TYPE_ADD   = 0x2,
6725  	MLX5_ACTION_TYPE_COPY  = 0x3,
6726  };
6727  
6728  enum {
6729  	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
6730  	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
6731  	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
6732  	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
6733  	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
6734  	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
6735  	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
6736  	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
6737  	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
6738  	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
6739  	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
6740  	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
6741  	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
6742  	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
6743  	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
6744  	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
6745  	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
6746  	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
6747  	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
6748  	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
6749  	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
6750  	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
6751  	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
6752  	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6753  	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
6754  	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
6755  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
6756  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
6757  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
6758  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6759  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6760  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6761  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6762  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6763  	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6764  	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6765  	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6766  	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6767  	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6768  };
6769  
6770  struct mlx5_ifc_alloc_modify_header_context_out_bits {
6771  	u8         status[0x8];
6772  	u8         reserved_at_8[0x18];
6773  
6774  	u8         syndrome[0x20];
6775  
6776  	u8         modify_header_id[0x20];
6777  
6778  	u8         reserved_at_60[0x20];
6779  };
6780  
6781  struct mlx5_ifc_alloc_modify_header_context_in_bits {
6782  	u8         opcode[0x10];
6783  	u8         reserved_at_10[0x10];
6784  
6785  	u8         reserved_at_20[0x10];
6786  	u8         op_mod[0x10];
6787  
6788  	u8         reserved_at_40[0x20];
6789  
6790  	u8         table_type[0x8];
6791  	u8         reserved_at_68[0x10];
6792  	u8         num_of_actions[0x8];
6793  
6794  	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6795  };
6796  
6797  struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6798  	u8         status[0x8];
6799  	u8         reserved_at_8[0x18];
6800  
6801  	u8         syndrome[0x20];
6802  
6803  	u8         reserved_at_40[0x40];
6804  };
6805  
6806  struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6807  	u8         opcode[0x10];
6808  	u8         reserved_at_10[0x10];
6809  
6810  	u8         reserved_at_20[0x10];
6811  	u8         op_mod[0x10];
6812  
6813  	u8         modify_header_id[0x20];
6814  
6815  	u8         reserved_at_60[0x20];
6816  };
6817  
6818  struct mlx5_ifc_query_modify_header_context_in_bits {
6819  	u8         opcode[0x10];
6820  	u8         uid[0x10];
6821  
6822  	u8         reserved_at_20[0x10];
6823  	u8         op_mod[0x10];
6824  
6825  	u8         modify_header_id[0x20];
6826  
6827  	u8         reserved_at_60[0xa0];
6828  };
6829  
6830  struct mlx5_ifc_query_dct_out_bits {
6831  	u8         status[0x8];
6832  	u8         reserved_at_8[0x18];
6833  
6834  	u8         syndrome[0x20];
6835  
6836  	u8         reserved_at_40[0x40];
6837  
6838  	struct mlx5_ifc_dctc_bits dct_context_entry;
6839  
6840  	u8         reserved_at_280[0x180];
6841  };
6842  
6843  struct mlx5_ifc_query_dct_in_bits {
6844  	u8         opcode[0x10];
6845  	u8         reserved_at_10[0x10];
6846  
6847  	u8         reserved_at_20[0x10];
6848  	u8         op_mod[0x10];
6849  
6850  	u8         reserved_at_40[0x8];
6851  	u8         dctn[0x18];
6852  
6853  	u8         reserved_at_60[0x20];
6854  };
6855  
6856  struct mlx5_ifc_query_cq_out_bits {
6857  	u8         status[0x8];
6858  	u8         reserved_at_8[0x18];
6859  
6860  	u8         syndrome[0x20];
6861  
6862  	u8         reserved_at_40[0x40];
6863  
6864  	struct mlx5_ifc_cqc_bits cq_context;
6865  
6866  	u8         reserved_at_280[0x600];
6867  
6868  	u8         pas[][0x40];
6869  };
6870  
6871  struct mlx5_ifc_query_cq_in_bits {
6872  	u8         opcode[0x10];
6873  	u8         reserved_at_10[0x10];
6874  
6875  	u8         reserved_at_20[0x10];
6876  	u8         op_mod[0x10];
6877  
6878  	u8         reserved_at_40[0x8];
6879  	u8         cqn[0x18];
6880  
6881  	u8         reserved_at_60[0x20];
6882  };
6883  
6884  struct mlx5_ifc_query_cong_status_out_bits {
6885  	u8         status[0x8];
6886  	u8         reserved_at_8[0x18];
6887  
6888  	u8         syndrome[0x20];
6889  
6890  	u8         reserved_at_40[0x20];
6891  
6892  	u8         enable[0x1];
6893  	u8         tag_enable[0x1];
6894  	u8         reserved_at_62[0x1e];
6895  };
6896  
6897  struct mlx5_ifc_query_cong_status_in_bits {
6898  	u8         opcode[0x10];
6899  	u8         reserved_at_10[0x10];
6900  
6901  	u8         reserved_at_20[0x10];
6902  	u8         op_mod[0x10];
6903  
6904  	u8         reserved_at_40[0x18];
6905  	u8         priority[0x4];
6906  	u8         cong_protocol[0x4];
6907  
6908  	u8         reserved_at_60[0x20];
6909  };
6910  
6911  struct mlx5_ifc_query_cong_statistics_out_bits {
6912  	u8         status[0x8];
6913  	u8         reserved_at_8[0x18];
6914  
6915  	u8         syndrome[0x20];
6916  
6917  	u8         reserved_at_40[0x40];
6918  
6919  	u8         rp_cur_flows[0x20];
6920  
6921  	u8         sum_flows[0x20];
6922  
6923  	u8         rp_cnp_ignored_high[0x20];
6924  
6925  	u8         rp_cnp_ignored_low[0x20];
6926  
6927  	u8         rp_cnp_handled_high[0x20];
6928  
6929  	u8         rp_cnp_handled_low[0x20];
6930  
6931  	u8         reserved_at_140[0x100];
6932  
6933  	u8         time_stamp_high[0x20];
6934  
6935  	u8         time_stamp_low[0x20];
6936  
6937  	u8         accumulators_period[0x20];
6938  
6939  	u8         np_ecn_marked_roce_packets_high[0x20];
6940  
6941  	u8         np_ecn_marked_roce_packets_low[0x20];
6942  
6943  	u8         np_cnp_sent_high[0x20];
6944  
6945  	u8         np_cnp_sent_low[0x20];
6946  
6947  	u8         reserved_at_320[0x560];
6948  };
6949  
6950  struct mlx5_ifc_query_cong_statistics_in_bits {
6951  	u8         opcode[0x10];
6952  	u8         reserved_at_10[0x10];
6953  
6954  	u8         reserved_at_20[0x10];
6955  	u8         op_mod[0x10];
6956  
6957  	u8         clear[0x1];
6958  	u8         reserved_at_41[0x1f];
6959  
6960  	u8         reserved_at_60[0x20];
6961  };
6962  
6963  struct mlx5_ifc_query_cong_params_out_bits {
6964  	u8         status[0x8];
6965  	u8         reserved_at_8[0x18];
6966  
6967  	u8         syndrome[0x20];
6968  
6969  	u8         reserved_at_40[0x40];
6970  
6971  	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6972  };
6973  
6974  struct mlx5_ifc_query_cong_params_in_bits {
6975  	u8         opcode[0x10];
6976  	u8         reserved_at_10[0x10];
6977  
6978  	u8         reserved_at_20[0x10];
6979  	u8         op_mod[0x10];
6980  
6981  	u8         reserved_at_40[0x1c];
6982  	u8         cong_protocol[0x4];
6983  
6984  	u8         reserved_at_60[0x20];
6985  };
6986  
6987  struct mlx5_ifc_query_adapter_out_bits {
6988  	u8         status[0x8];
6989  	u8         reserved_at_8[0x18];
6990  
6991  	u8         syndrome[0x20];
6992  
6993  	u8         reserved_at_40[0x40];
6994  
6995  	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6996  };
6997  
6998  struct mlx5_ifc_query_adapter_in_bits {
6999  	u8         opcode[0x10];
7000  	u8         reserved_at_10[0x10];
7001  
7002  	u8         reserved_at_20[0x10];
7003  	u8         op_mod[0x10];
7004  
7005  	u8         reserved_at_40[0x40];
7006  };
7007  
7008  struct mlx5_ifc_qp_2rst_out_bits {
7009  	u8         status[0x8];
7010  	u8         reserved_at_8[0x18];
7011  
7012  	u8         syndrome[0x20];
7013  
7014  	u8         reserved_at_40[0x40];
7015  };
7016  
7017  struct mlx5_ifc_qp_2rst_in_bits {
7018  	u8         opcode[0x10];
7019  	u8         uid[0x10];
7020  
7021  	u8         reserved_at_20[0x10];
7022  	u8         op_mod[0x10];
7023  
7024  	u8         reserved_at_40[0x8];
7025  	u8         qpn[0x18];
7026  
7027  	u8         reserved_at_60[0x20];
7028  };
7029  
7030  struct mlx5_ifc_qp_2err_out_bits {
7031  	u8         status[0x8];
7032  	u8         reserved_at_8[0x18];
7033  
7034  	u8         syndrome[0x20];
7035  
7036  	u8         reserved_at_40[0x40];
7037  };
7038  
7039  struct mlx5_ifc_qp_2err_in_bits {
7040  	u8         opcode[0x10];
7041  	u8         uid[0x10];
7042  
7043  	u8         reserved_at_20[0x10];
7044  	u8         op_mod[0x10];
7045  
7046  	u8         reserved_at_40[0x8];
7047  	u8         qpn[0x18];
7048  
7049  	u8         reserved_at_60[0x20];
7050  };
7051  
7052  struct mlx5_ifc_page_fault_resume_out_bits {
7053  	u8         status[0x8];
7054  	u8         reserved_at_8[0x18];
7055  
7056  	u8         syndrome[0x20];
7057  
7058  	u8         reserved_at_40[0x40];
7059  };
7060  
7061  struct mlx5_ifc_page_fault_resume_in_bits {
7062  	u8         opcode[0x10];
7063  	u8         reserved_at_10[0x10];
7064  
7065  	u8         reserved_at_20[0x10];
7066  	u8         op_mod[0x10];
7067  
7068  	u8         error[0x1];
7069  	u8         reserved_at_41[0x4];
7070  	u8         page_fault_type[0x3];
7071  	u8         wq_number[0x18];
7072  
7073  	u8         reserved_at_60[0x8];
7074  	u8         token[0x18];
7075  };
7076  
7077  struct mlx5_ifc_nop_out_bits {
7078  	u8         status[0x8];
7079  	u8         reserved_at_8[0x18];
7080  
7081  	u8         syndrome[0x20];
7082  
7083  	u8         reserved_at_40[0x40];
7084  };
7085  
7086  struct mlx5_ifc_nop_in_bits {
7087  	u8         opcode[0x10];
7088  	u8         reserved_at_10[0x10];
7089  
7090  	u8         reserved_at_20[0x10];
7091  	u8         op_mod[0x10];
7092  
7093  	u8         reserved_at_40[0x40];
7094  };
7095  
7096  struct mlx5_ifc_modify_vport_state_out_bits {
7097  	u8         status[0x8];
7098  	u8         reserved_at_8[0x18];
7099  
7100  	u8         syndrome[0x20];
7101  
7102  	u8         reserved_at_40[0x40];
7103  };
7104  
7105  struct mlx5_ifc_modify_vport_state_in_bits {
7106  	u8         opcode[0x10];
7107  	u8         reserved_at_10[0x10];
7108  
7109  	u8         reserved_at_20[0x10];
7110  	u8         op_mod[0x10];
7111  
7112  	u8         other_vport[0x1];
7113  	u8         reserved_at_41[0xf];
7114  	u8         vport_number[0x10];
7115  
7116  	u8         reserved_at_60[0x18];
7117  	u8         admin_state[0x4];
7118  	u8         reserved_at_7c[0x4];
7119  };
7120  
7121  struct mlx5_ifc_modify_tis_out_bits {
7122  	u8         status[0x8];
7123  	u8         reserved_at_8[0x18];
7124  
7125  	u8         syndrome[0x20];
7126  
7127  	u8         reserved_at_40[0x40];
7128  };
7129  
7130  struct mlx5_ifc_modify_tis_bitmask_bits {
7131  	u8         reserved_at_0[0x20];
7132  
7133  	u8         reserved_at_20[0x1d];
7134  	u8         lag_tx_port_affinity[0x1];
7135  	u8         strict_lag_tx_port_affinity[0x1];
7136  	u8         prio[0x1];
7137  };
7138  
7139  struct mlx5_ifc_modify_tis_in_bits {
7140  	u8         opcode[0x10];
7141  	u8         uid[0x10];
7142  
7143  	u8         reserved_at_20[0x10];
7144  	u8         op_mod[0x10];
7145  
7146  	u8         reserved_at_40[0x8];
7147  	u8         tisn[0x18];
7148  
7149  	u8         reserved_at_60[0x20];
7150  
7151  	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7152  
7153  	u8         reserved_at_c0[0x40];
7154  
7155  	struct mlx5_ifc_tisc_bits ctx;
7156  };
7157  
7158  struct mlx5_ifc_modify_tir_bitmask_bits {
7159  	u8	   reserved_at_0[0x20];
7160  
7161  	u8         reserved_at_20[0x1b];
7162  	u8         self_lb_en[0x1];
7163  	u8         reserved_at_3c[0x1];
7164  	u8         hash[0x1];
7165  	u8         reserved_at_3e[0x1];
7166  	u8         packet_merge[0x1];
7167  };
7168  
7169  struct mlx5_ifc_modify_tir_out_bits {
7170  	u8         status[0x8];
7171  	u8         reserved_at_8[0x18];
7172  
7173  	u8         syndrome[0x20];
7174  
7175  	u8         reserved_at_40[0x40];
7176  };
7177  
7178  struct mlx5_ifc_modify_tir_in_bits {
7179  	u8         opcode[0x10];
7180  	u8         uid[0x10];
7181  
7182  	u8         reserved_at_20[0x10];
7183  	u8         op_mod[0x10];
7184  
7185  	u8         reserved_at_40[0x8];
7186  	u8         tirn[0x18];
7187  
7188  	u8         reserved_at_60[0x20];
7189  
7190  	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7191  
7192  	u8         reserved_at_c0[0x40];
7193  
7194  	struct mlx5_ifc_tirc_bits ctx;
7195  };
7196  
7197  struct mlx5_ifc_modify_sq_out_bits {
7198  	u8         status[0x8];
7199  	u8         reserved_at_8[0x18];
7200  
7201  	u8         syndrome[0x20];
7202  
7203  	u8         reserved_at_40[0x40];
7204  };
7205  
7206  struct mlx5_ifc_modify_sq_in_bits {
7207  	u8         opcode[0x10];
7208  	u8         uid[0x10];
7209  
7210  	u8         reserved_at_20[0x10];
7211  	u8         op_mod[0x10];
7212  
7213  	u8         sq_state[0x4];
7214  	u8         reserved_at_44[0x4];
7215  	u8         sqn[0x18];
7216  
7217  	u8         reserved_at_60[0x20];
7218  
7219  	u8         modify_bitmask[0x40];
7220  
7221  	u8         reserved_at_c0[0x40];
7222  
7223  	struct mlx5_ifc_sqc_bits ctx;
7224  };
7225  
7226  struct mlx5_ifc_modify_scheduling_element_out_bits {
7227  	u8         status[0x8];
7228  	u8         reserved_at_8[0x18];
7229  
7230  	u8         syndrome[0x20];
7231  
7232  	u8         reserved_at_40[0x1c0];
7233  };
7234  
7235  enum {
7236  	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7237  	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7238  };
7239  
7240  struct mlx5_ifc_modify_scheduling_element_in_bits {
7241  	u8         opcode[0x10];
7242  	u8         reserved_at_10[0x10];
7243  
7244  	u8         reserved_at_20[0x10];
7245  	u8         op_mod[0x10];
7246  
7247  	u8         scheduling_hierarchy[0x8];
7248  	u8         reserved_at_48[0x18];
7249  
7250  	u8         scheduling_element_id[0x20];
7251  
7252  	u8         reserved_at_80[0x20];
7253  
7254  	u8         modify_bitmask[0x20];
7255  
7256  	u8         reserved_at_c0[0x40];
7257  
7258  	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7259  
7260  	u8         reserved_at_300[0x100];
7261  };
7262  
7263  struct mlx5_ifc_modify_rqt_out_bits {
7264  	u8         status[0x8];
7265  	u8         reserved_at_8[0x18];
7266  
7267  	u8         syndrome[0x20];
7268  
7269  	u8         reserved_at_40[0x40];
7270  };
7271  
7272  struct mlx5_ifc_rqt_bitmask_bits {
7273  	u8	   reserved_at_0[0x20];
7274  
7275  	u8         reserved_at_20[0x1f];
7276  	u8         rqn_list[0x1];
7277  };
7278  
7279  struct mlx5_ifc_modify_rqt_in_bits {
7280  	u8         opcode[0x10];
7281  	u8         uid[0x10];
7282  
7283  	u8         reserved_at_20[0x10];
7284  	u8         op_mod[0x10];
7285  
7286  	u8         reserved_at_40[0x8];
7287  	u8         rqtn[0x18];
7288  
7289  	u8         reserved_at_60[0x20];
7290  
7291  	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7292  
7293  	u8         reserved_at_c0[0x40];
7294  
7295  	struct mlx5_ifc_rqtc_bits ctx;
7296  };
7297  
7298  struct mlx5_ifc_modify_rq_out_bits {
7299  	u8         status[0x8];
7300  	u8         reserved_at_8[0x18];
7301  
7302  	u8         syndrome[0x20];
7303  
7304  	u8         reserved_at_40[0x40];
7305  };
7306  
7307  enum {
7308  	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7309  	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7310  	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7311  };
7312  
7313  struct mlx5_ifc_modify_rq_in_bits {
7314  	u8         opcode[0x10];
7315  	u8         uid[0x10];
7316  
7317  	u8         reserved_at_20[0x10];
7318  	u8         op_mod[0x10];
7319  
7320  	u8         rq_state[0x4];
7321  	u8         reserved_at_44[0x4];
7322  	u8         rqn[0x18];
7323  
7324  	u8         reserved_at_60[0x20];
7325  
7326  	u8         modify_bitmask[0x40];
7327  
7328  	u8         reserved_at_c0[0x40];
7329  
7330  	struct mlx5_ifc_rqc_bits ctx;
7331  };
7332  
7333  struct mlx5_ifc_modify_rmp_out_bits {
7334  	u8         status[0x8];
7335  	u8         reserved_at_8[0x18];
7336  
7337  	u8         syndrome[0x20];
7338  
7339  	u8         reserved_at_40[0x40];
7340  };
7341  
7342  struct mlx5_ifc_rmp_bitmask_bits {
7343  	u8	   reserved_at_0[0x20];
7344  
7345  	u8         reserved_at_20[0x1f];
7346  	u8         lwm[0x1];
7347  };
7348  
7349  struct mlx5_ifc_modify_rmp_in_bits {
7350  	u8         opcode[0x10];
7351  	u8         uid[0x10];
7352  
7353  	u8         reserved_at_20[0x10];
7354  	u8         op_mod[0x10];
7355  
7356  	u8         rmp_state[0x4];
7357  	u8         reserved_at_44[0x4];
7358  	u8         rmpn[0x18];
7359  
7360  	u8         reserved_at_60[0x20];
7361  
7362  	struct mlx5_ifc_rmp_bitmask_bits bitmask;
7363  
7364  	u8         reserved_at_c0[0x40];
7365  
7366  	struct mlx5_ifc_rmpc_bits ctx;
7367  };
7368  
7369  struct mlx5_ifc_modify_nic_vport_context_out_bits {
7370  	u8         status[0x8];
7371  	u8         reserved_at_8[0x18];
7372  
7373  	u8         syndrome[0x20];
7374  
7375  	u8         reserved_at_40[0x40];
7376  };
7377  
7378  struct mlx5_ifc_modify_nic_vport_field_select_bits {
7379  	u8         reserved_at_0[0x12];
7380  	u8	   affiliation[0x1];
7381  	u8	   reserved_at_13[0x1];
7382  	u8         disable_uc_local_lb[0x1];
7383  	u8         disable_mc_local_lb[0x1];
7384  	u8         node_guid[0x1];
7385  	u8         port_guid[0x1];
7386  	u8         min_inline[0x1];
7387  	u8         mtu[0x1];
7388  	u8         change_event[0x1];
7389  	u8         promisc[0x1];
7390  	u8         permanent_address[0x1];
7391  	u8         addresses_list[0x1];
7392  	u8         roce_en[0x1];
7393  	u8         reserved_at_1f[0x1];
7394  };
7395  
7396  struct mlx5_ifc_modify_nic_vport_context_in_bits {
7397  	u8         opcode[0x10];
7398  	u8         reserved_at_10[0x10];
7399  
7400  	u8         reserved_at_20[0x10];
7401  	u8         op_mod[0x10];
7402  
7403  	u8         other_vport[0x1];
7404  	u8         reserved_at_41[0xf];
7405  	u8         vport_number[0x10];
7406  
7407  	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7408  
7409  	u8         reserved_at_80[0x780];
7410  
7411  	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7412  };
7413  
7414  struct mlx5_ifc_modify_hca_vport_context_out_bits {
7415  	u8         status[0x8];
7416  	u8         reserved_at_8[0x18];
7417  
7418  	u8         syndrome[0x20];
7419  
7420  	u8         reserved_at_40[0x40];
7421  };
7422  
7423  struct mlx5_ifc_modify_hca_vport_context_in_bits {
7424  	u8         opcode[0x10];
7425  	u8         reserved_at_10[0x10];
7426  
7427  	u8         reserved_at_20[0x10];
7428  	u8         op_mod[0x10];
7429  
7430  	u8         other_vport[0x1];
7431  	u8         reserved_at_41[0xb];
7432  	u8         port_num[0x4];
7433  	u8         vport_number[0x10];
7434  
7435  	u8         reserved_at_60[0x20];
7436  
7437  	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7438  };
7439  
7440  struct mlx5_ifc_modify_cq_out_bits {
7441  	u8         status[0x8];
7442  	u8         reserved_at_8[0x18];
7443  
7444  	u8         syndrome[0x20];
7445  
7446  	u8         reserved_at_40[0x40];
7447  };
7448  
7449  enum {
7450  	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7451  	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7452  };
7453  
7454  struct mlx5_ifc_modify_cq_in_bits {
7455  	u8         opcode[0x10];
7456  	u8         uid[0x10];
7457  
7458  	u8         reserved_at_20[0x10];
7459  	u8         op_mod[0x10];
7460  
7461  	u8         reserved_at_40[0x8];
7462  	u8         cqn[0x18];
7463  
7464  	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7465  
7466  	struct mlx5_ifc_cqc_bits cq_context;
7467  
7468  	u8         reserved_at_280[0x60];
7469  
7470  	u8         cq_umem_valid[0x1];
7471  	u8         reserved_at_2e1[0x1f];
7472  
7473  	u8         reserved_at_300[0x580];
7474  
7475  	u8         pas[][0x40];
7476  };
7477  
7478  struct mlx5_ifc_modify_cong_status_out_bits {
7479  	u8         status[0x8];
7480  	u8         reserved_at_8[0x18];
7481  
7482  	u8         syndrome[0x20];
7483  
7484  	u8         reserved_at_40[0x40];
7485  };
7486  
7487  struct mlx5_ifc_modify_cong_status_in_bits {
7488  	u8         opcode[0x10];
7489  	u8         reserved_at_10[0x10];
7490  
7491  	u8         reserved_at_20[0x10];
7492  	u8         op_mod[0x10];
7493  
7494  	u8         reserved_at_40[0x18];
7495  	u8         priority[0x4];
7496  	u8         cong_protocol[0x4];
7497  
7498  	u8         enable[0x1];
7499  	u8         tag_enable[0x1];
7500  	u8         reserved_at_62[0x1e];
7501  };
7502  
7503  struct mlx5_ifc_modify_cong_params_out_bits {
7504  	u8         status[0x8];
7505  	u8         reserved_at_8[0x18];
7506  
7507  	u8         syndrome[0x20];
7508  
7509  	u8         reserved_at_40[0x40];
7510  };
7511  
7512  struct mlx5_ifc_modify_cong_params_in_bits {
7513  	u8         opcode[0x10];
7514  	u8         reserved_at_10[0x10];
7515  
7516  	u8         reserved_at_20[0x10];
7517  	u8         op_mod[0x10];
7518  
7519  	u8         reserved_at_40[0x1c];
7520  	u8         cong_protocol[0x4];
7521  
7522  	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7523  
7524  	u8         reserved_at_80[0x80];
7525  
7526  	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7527  };
7528  
7529  struct mlx5_ifc_manage_pages_out_bits {
7530  	u8         status[0x8];
7531  	u8         reserved_at_8[0x18];
7532  
7533  	u8         syndrome[0x20];
7534  
7535  	u8         output_num_entries[0x20];
7536  
7537  	u8         reserved_at_60[0x20];
7538  
7539  	u8         pas[][0x40];
7540  };
7541  
7542  enum {
7543  	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7544  	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7545  	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7546  };
7547  
7548  struct mlx5_ifc_manage_pages_in_bits {
7549  	u8         opcode[0x10];
7550  	u8         reserved_at_10[0x10];
7551  
7552  	u8         reserved_at_20[0x10];
7553  	u8         op_mod[0x10];
7554  
7555  	u8         embedded_cpu_function[0x1];
7556  	u8         reserved_at_41[0xf];
7557  	u8         function_id[0x10];
7558  
7559  	u8         input_num_entries[0x20];
7560  
7561  	u8         pas[][0x40];
7562  };
7563  
7564  struct mlx5_ifc_mad_ifc_out_bits {
7565  	u8         status[0x8];
7566  	u8         reserved_at_8[0x18];
7567  
7568  	u8         syndrome[0x20];
7569  
7570  	u8         reserved_at_40[0x40];
7571  
7572  	u8         response_mad_packet[256][0x8];
7573  };
7574  
7575  struct mlx5_ifc_mad_ifc_in_bits {
7576  	u8         opcode[0x10];
7577  	u8         reserved_at_10[0x10];
7578  
7579  	u8         reserved_at_20[0x10];
7580  	u8         op_mod[0x10];
7581  
7582  	u8         remote_lid[0x10];
7583  	u8         reserved_at_50[0x8];
7584  	u8         port[0x8];
7585  
7586  	u8         reserved_at_60[0x20];
7587  
7588  	u8         mad[256][0x8];
7589  };
7590  
7591  struct mlx5_ifc_init_hca_out_bits {
7592  	u8         status[0x8];
7593  	u8         reserved_at_8[0x18];
7594  
7595  	u8         syndrome[0x20];
7596  
7597  	u8         reserved_at_40[0x40];
7598  };
7599  
7600  struct mlx5_ifc_init_hca_in_bits {
7601  	u8         opcode[0x10];
7602  	u8         reserved_at_10[0x10];
7603  
7604  	u8         reserved_at_20[0x10];
7605  	u8         op_mod[0x10];
7606  
7607  	u8         reserved_at_40[0x20];
7608  
7609  	u8         reserved_at_60[0x2];
7610  	u8         sw_vhca_id[0xe];
7611  	u8         reserved_at_70[0x10];
7612  
7613  	u8	   sw_owner_id[4][0x20];
7614  };
7615  
7616  struct mlx5_ifc_init2rtr_qp_out_bits {
7617  	u8         status[0x8];
7618  	u8         reserved_at_8[0x18];
7619  
7620  	u8         syndrome[0x20];
7621  
7622  	u8         reserved_at_40[0x20];
7623  	u8         ece[0x20];
7624  };
7625  
7626  struct mlx5_ifc_init2rtr_qp_in_bits {
7627  	u8         opcode[0x10];
7628  	u8         uid[0x10];
7629  
7630  	u8         reserved_at_20[0x10];
7631  	u8         op_mod[0x10];
7632  
7633  	u8         reserved_at_40[0x8];
7634  	u8         qpn[0x18];
7635  
7636  	u8         reserved_at_60[0x20];
7637  
7638  	u8         opt_param_mask[0x20];
7639  
7640  	u8         ece[0x20];
7641  
7642  	struct mlx5_ifc_qpc_bits qpc;
7643  
7644  	u8         reserved_at_800[0x80];
7645  };
7646  
7647  struct mlx5_ifc_init2init_qp_out_bits {
7648  	u8         status[0x8];
7649  	u8         reserved_at_8[0x18];
7650  
7651  	u8         syndrome[0x20];
7652  
7653  	u8         reserved_at_40[0x20];
7654  	u8         ece[0x20];
7655  };
7656  
7657  struct mlx5_ifc_init2init_qp_in_bits {
7658  	u8         opcode[0x10];
7659  	u8         uid[0x10];
7660  
7661  	u8         reserved_at_20[0x10];
7662  	u8         op_mod[0x10];
7663  
7664  	u8         reserved_at_40[0x8];
7665  	u8         qpn[0x18];
7666  
7667  	u8         reserved_at_60[0x20];
7668  
7669  	u8         opt_param_mask[0x20];
7670  
7671  	u8         ece[0x20];
7672  
7673  	struct mlx5_ifc_qpc_bits qpc;
7674  
7675  	u8         reserved_at_800[0x80];
7676  };
7677  
7678  struct mlx5_ifc_get_dropped_packet_log_out_bits {
7679  	u8         status[0x8];
7680  	u8         reserved_at_8[0x18];
7681  
7682  	u8         syndrome[0x20];
7683  
7684  	u8         reserved_at_40[0x40];
7685  
7686  	u8         packet_headers_log[128][0x8];
7687  
7688  	u8         packet_syndrome[64][0x8];
7689  };
7690  
7691  struct mlx5_ifc_get_dropped_packet_log_in_bits {
7692  	u8         opcode[0x10];
7693  	u8         reserved_at_10[0x10];
7694  
7695  	u8         reserved_at_20[0x10];
7696  	u8         op_mod[0x10];
7697  
7698  	u8         reserved_at_40[0x40];
7699  };
7700  
7701  struct mlx5_ifc_gen_eqe_in_bits {
7702  	u8         opcode[0x10];
7703  	u8         reserved_at_10[0x10];
7704  
7705  	u8         reserved_at_20[0x10];
7706  	u8         op_mod[0x10];
7707  
7708  	u8         reserved_at_40[0x18];
7709  	u8         eq_number[0x8];
7710  
7711  	u8         reserved_at_60[0x20];
7712  
7713  	u8         eqe[64][0x8];
7714  };
7715  
7716  struct mlx5_ifc_gen_eq_out_bits {
7717  	u8         status[0x8];
7718  	u8         reserved_at_8[0x18];
7719  
7720  	u8         syndrome[0x20];
7721  
7722  	u8         reserved_at_40[0x40];
7723  };
7724  
7725  struct mlx5_ifc_enable_hca_out_bits {
7726  	u8         status[0x8];
7727  	u8         reserved_at_8[0x18];
7728  
7729  	u8         syndrome[0x20];
7730  
7731  	u8         reserved_at_40[0x20];
7732  };
7733  
7734  struct mlx5_ifc_enable_hca_in_bits {
7735  	u8         opcode[0x10];
7736  	u8         reserved_at_10[0x10];
7737  
7738  	u8         reserved_at_20[0x10];
7739  	u8         op_mod[0x10];
7740  
7741  	u8         embedded_cpu_function[0x1];
7742  	u8         reserved_at_41[0xf];
7743  	u8         function_id[0x10];
7744  
7745  	u8         reserved_at_60[0x20];
7746  };
7747  
7748  struct mlx5_ifc_drain_dct_out_bits {
7749  	u8         status[0x8];
7750  	u8         reserved_at_8[0x18];
7751  
7752  	u8         syndrome[0x20];
7753  
7754  	u8         reserved_at_40[0x40];
7755  };
7756  
7757  struct mlx5_ifc_drain_dct_in_bits {
7758  	u8         opcode[0x10];
7759  	u8         uid[0x10];
7760  
7761  	u8         reserved_at_20[0x10];
7762  	u8         op_mod[0x10];
7763  
7764  	u8         reserved_at_40[0x8];
7765  	u8         dctn[0x18];
7766  
7767  	u8         reserved_at_60[0x20];
7768  };
7769  
7770  struct mlx5_ifc_disable_hca_out_bits {
7771  	u8         status[0x8];
7772  	u8         reserved_at_8[0x18];
7773  
7774  	u8         syndrome[0x20];
7775  
7776  	u8         reserved_at_40[0x20];
7777  };
7778  
7779  struct mlx5_ifc_disable_hca_in_bits {
7780  	u8         opcode[0x10];
7781  	u8         reserved_at_10[0x10];
7782  
7783  	u8         reserved_at_20[0x10];
7784  	u8         op_mod[0x10];
7785  
7786  	u8         embedded_cpu_function[0x1];
7787  	u8         reserved_at_41[0xf];
7788  	u8         function_id[0x10];
7789  
7790  	u8         reserved_at_60[0x20];
7791  };
7792  
7793  struct mlx5_ifc_detach_from_mcg_out_bits {
7794  	u8         status[0x8];
7795  	u8         reserved_at_8[0x18];
7796  
7797  	u8         syndrome[0x20];
7798  
7799  	u8         reserved_at_40[0x40];
7800  };
7801  
7802  struct mlx5_ifc_detach_from_mcg_in_bits {
7803  	u8         opcode[0x10];
7804  	u8         uid[0x10];
7805  
7806  	u8         reserved_at_20[0x10];
7807  	u8         op_mod[0x10];
7808  
7809  	u8         reserved_at_40[0x8];
7810  	u8         qpn[0x18];
7811  
7812  	u8         reserved_at_60[0x20];
7813  
7814  	u8         multicast_gid[16][0x8];
7815  };
7816  
7817  struct mlx5_ifc_destroy_xrq_out_bits {
7818  	u8         status[0x8];
7819  	u8         reserved_at_8[0x18];
7820  
7821  	u8         syndrome[0x20];
7822  
7823  	u8         reserved_at_40[0x40];
7824  };
7825  
7826  struct mlx5_ifc_destroy_xrq_in_bits {
7827  	u8         opcode[0x10];
7828  	u8         uid[0x10];
7829  
7830  	u8         reserved_at_20[0x10];
7831  	u8         op_mod[0x10];
7832  
7833  	u8         reserved_at_40[0x8];
7834  	u8         xrqn[0x18];
7835  
7836  	u8         reserved_at_60[0x20];
7837  };
7838  
7839  struct mlx5_ifc_destroy_xrc_srq_out_bits {
7840  	u8         status[0x8];
7841  	u8         reserved_at_8[0x18];
7842  
7843  	u8         syndrome[0x20];
7844  
7845  	u8         reserved_at_40[0x40];
7846  };
7847  
7848  struct mlx5_ifc_destroy_xrc_srq_in_bits {
7849  	u8         opcode[0x10];
7850  	u8         uid[0x10];
7851  
7852  	u8         reserved_at_20[0x10];
7853  	u8         op_mod[0x10];
7854  
7855  	u8         reserved_at_40[0x8];
7856  	u8         xrc_srqn[0x18];
7857  
7858  	u8         reserved_at_60[0x20];
7859  };
7860  
7861  struct mlx5_ifc_destroy_tis_out_bits {
7862  	u8         status[0x8];
7863  	u8         reserved_at_8[0x18];
7864  
7865  	u8         syndrome[0x20];
7866  
7867  	u8         reserved_at_40[0x40];
7868  };
7869  
7870  struct mlx5_ifc_destroy_tis_in_bits {
7871  	u8         opcode[0x10];
7872  	u8         uid[0x10];
7873  
7874  	u8         reserved_at_20[0x10];
7875  	u8         op_mod[0x10];
7876  
7877  	u8         reserved_at_40[0x8];
7878  	u8         tisn[0x18];
7879  
7880  	u8         reserved_at_60[0x20];
7881  };
7882  
7883  struct mlx5_ifc_destroy_tir_out_bits {
7884  	u8         status[0x8];
7885  	u8         reserved_at_8[0x18];
7886  
7887  	u8         syndrome[0x20];
7888  
7889  	u8         reserved_at_40[0x40];
7890  };
7891  
7892  struct mlx5_ifc_destroy_tir_in_bits {
7893  	u8         opcode[0x10];
7894  	u8         uid[0x10];
7895  
7896  	u8         reserved_at_20[0x10];
7897  	u8         op_mod[0x10];
7898  
7899  	u8         reserved_at_40[0x8];
7900  	u8         tirn[0x18];
7901  
7902  	u8         reserved_at_60[0x20];
7903  };
7904  
7905  struct mlx5_ifc_destroy_srq_out_bits {
7906  	u8         status[0x8];
7907  	u8         reserved_at_8[0x18];
7908  
7909  	u8         syndrome[0x20];
7910  
7911  	u8         reserved_at_40[0x40];
7912  };
7913  
7914  struct mlx5_ifc_destroy_srq_in_bits {
7915  	u8         opcode[0x10];
7916  	u8         uid[0x10];
7917  
7918  	u8         reserved_at_20[0x10];
7919  	u8         op_mod[0x10];
7920  
7921  	u8         reserved_at_40[0x8];
7922  	u8         srqn[0x18];
7923  
7924  	u8         reserved_at_60[0x20];
7925  };
7926  
7927  struct mlx5_ifc_destroy_sq_out_bits {
7928  	u8         status[0x8];
7929  	u8         reserved_at_8[0x18];
7930  
7931  	u8         syndrome[0x20];
7932  
7933  	u8         reserved_at_40[0x40];
7934  };
7935  
7936  struct mlx5_ifc_destroy_sq_in_bits {
7937  	u8         opcode[0x10];
7938  	u8         uid[0x10];
7939  
7940  	u8         reserved_at_20[0x10];
7941  	u8         op_mod[0x10];
7942  
7943  	u8         reserved_at_40[0x8];
7944  	u8         sqn[0x18];
7945  
7946  	u8         reserved_at_60[0x20];
7947  };
7948  
7949  struct mlx5_ifc_destroy_scheduling_element_out_bits {
7950  	u8         status[0x8];
7951  	u8         reserved_at_8[0x18];
7952  
7953  	u8         syndrome[0x20];
7954  
7955  	u8         reserved_at_40[0x1c0];
7956  };
7957  
7958  struct mlx5_ifc_destroy_scheduling_element_in_bits {
7959  	u8         opcode[0x10];
7960  	u8         reserved_at_10[0x10];
7961  
7962  	u8         reserved_at_20[0x10];
7963  	u8         op_mod[0x10];
7964  
7965  	u8         scheduling_hierarchy[0x8];
7966  	u8         reserved_at_48[0x18];
7967  
7968  	u8         scheduling_element_id[0x20];
7969  
7970  	u8         reserved_at_80[0x180];
7971  };
7972  
7973  struct mlx5_ifc_destroy_rqt_out_bits {
7974  	u8         status[0x8];
7975  	u8         reserved_at_8[0x18];
7976  
7977  	u8         syndrome[0x20];
7978  
7979  	u8         reserved_at_40[0x40];
7980  };
7981  
7982  struct mlx5_ifc_destroy_rqt_in_bits {
7983  	u8         opcode[0x10];
7984  	u8         uid[0x10];
7985  
7986  	u8         reserved_at_20[0x10];
7987  	u8         op_mod[0x10];
7988  
7989  	u8         reserved_at_40[0x8];
7990  	u8         rqtn[0x18];
7991  
7992  	u8         reserved_at_60[0x20];
7993  };
7994  
7995  struct mlx5_ifc_destroy_rq_out_bits {
7996  	u8         status[0x8];
7997  	u8         reserved_at_8[0x18];
7998  
7999  	u8         syndrome[0x20];
8000  
8001  	u8         reserved_at_40[0x40];
8002  };
8003  
8004  struct mlx5_ifc_destroy_rq_in_bits {
8005  	u8         opcode[0x10];
8006  	u8         uid[0x10];
8007  
8008  	u8         reserved_at_20[0x10];
8009  	u8         op_mod[0x10];
8010  
8011  	u8         reserved_at_40[0x8];
8012  	u8         rqn[0x18];
8013  
8014  	u8         reserved_at_60[0x20];
8015  };
8016  
8017  struct mlx5_ifc_set_delay_drop_params_in_bits {
8018  	u8         opcode[0x10];
8019  	u8         reserved_at_10[0x10];
8020  
8021  	u8         reserved_at_20[0x10];
8022  	u8         op_mod[0x10];
8023  
8024  	u8         reserved_at_40[0x20];
8025  
8026  	u8         reserved_at_60[0x10];
8027  	u8         delay_drop_timeout[0x10];
8028  };
8029  
8030  struct mlx5_ifc_set_delay_drop_params_out_bits {
8031  	u8         status[0x8];
8032  	u8         reserved_at_8[0x18];
8033  
8034  	u8         syndrome[0x20];
8035  
8036  	u8         reserved_at_40[0x40];
8037  };
8038  
8039  struct mlx5_ifc_destroy_rmp_out_bits {
8040  	u8         status[0x8];
8041  	u8         reserved_at_8[0x18];
8042  
8043  	u8         syndrome[0x20];
8044  
8045  	u8         reserved_at_40[0x40];
8046  };
8047  
8048  struct mlx5_ifc_destroy_rmp_in_bits {
8049  	u8         opcode[0x10];
8050  	u8         uid[0x10];
8051  
8052  	u8         reserved_at_20[0x10];
8053  	u8         op_mod[0x10];
8054  
8055  	u8         reserved_at_40[0x8];
8056  	u8         rmpn[0x18];
8057  
8058  	u8         reserved_at_60[0x20];
8059  };
8060  
8061  struct mlx5_ifc_destroy_qp_out_bits {
8062  	u8         status[0x8];
8063  	u8         reserved_at_8[0x18];
8064  
8065  	u8         syndrome[0x20];
8066  
8067  	u8         reserved_at_40[0x40];
8068  };
8069  
8070  struct mlx5_ifc_destroy_qp_in_bits {
8071  	u8         opcode[0x10];
8072  	u8         uid[0x10];
8073  
8074  	u8         reserved_at_20[0x10];
8075  	u8         op_mod[0x10];
8076  
8077  	u8         reserved_at_40[0x8];
8078  	u8         qpn[0x18];
8079  
8080  	u8         reserved_at_60[0x20];
8081  };
8082  
8083  struct mlx5_ifc_destroy_psv_out_bits {
8084  	u8         status[0x8];
8085  	u8         reserved_at_8[0x18];
8086  
8087  	u8         syndrome[0x20];
8088  
8089  	u8         reserved_at_40[0x40];
8090  };
8091  
8092  struct mlx5_ifc_destroy_psv_in_bits {
8093  	u8         opcode[0x10];
8094  	u8         reserved_at_10[0x10];
8095  
8096  	u8         reserved_at_20[0x10];
8097  	u8         op_mod[0x10];
8098  
8099  	u8         reserved_at_40[0x8];
8100  	u8         psvn[0x18];
8101  
8102  	u8         reserved_at_60[0x20];
8103  };
8104  
8105  struct mlx5_ifc_destroy_mkey_out_bits {
8106  	u8         status[0x8];
8107  	u8         reserved_at_8[0x18];
8108  
8109  	u8         syndrome[0x20];
8110  
8111  	u8         reserved_at_40[0x40];
8112  };
8113  
8114  struct mlx5_ifc_destroy_mkey_in_bits {
8115  	u8         opcode[0x10];
8116  	u8         uid[0x10];
8117  
8118  	u8         reserved_at_20[0x10];
8119  	u8         op_mod[0x10];
8120  
8121  	u8         reserved_at_40[0x8];
8122  	u8         mkey_index[0x18];
8123  
8124  	u8         reserved_at_60[0x20];
8125  };
8126  
8127  struct mlx5_ifc_destroy_flow_table_out_bits {
8128  	u8         status[0x8];
8129  	u8         reserved_at_8[0x18];
8130  
8131  	u8         syndrome[0x20];
8132  
8133  	u8         reserved_at_40[0x40];
8134  };
8135  
8136  struct mlx5_ifc_destroy_flow_table_in_bits {
8137  	u8         opcode[0x10];
8138  	u8         reserved_at_10[0x10];
8139  
8140  	u8         reserved_at_20[0x10];
8141  	u8         op_mod[0x10];
8142  
8143  	u8         other_vport[0x1];
8144  	u8         reserved_at_41[0xf];
8145  	u8         vport_number[0x10];
8146  
8147  	u8         reserved_at_60[0x20];
8148  
8149  	u8         table_type[0x8];
8150  	u8         reserved_at_88[0x18];
8151  
8152  	u8         reserved_at_a0[0x8];
8153  	u8         table_id[0x18];
8154  
8155  	u8         reserved_at_c0[0x140];
8156  };
8157  
8158  struct mlx5_ifc_destroy_flow_group_out_bits {
8159  	u8         status[0x8];
8160  	u8         reserved_at_8[0x18];
8161  
8162  	u8         syndrome[0x20];
8163  
8164  	u8         reserved_at_40[0x40];
8165  };
8166  
8167  struct mlx5_ifc_destroy_flow_group_in_bits {
8168  	u8         opcode[0x10];
8169  	u8         reserved_at_10[0x10];
8170  
8171  	u8         reserved_at_20[0x10];
8172  	u8         op_mod[0x10];
8173  
8174  	u8         other_vport[0x1];
8175  	u8         reserved_at_41[0xf];
8176  	u8         vport_number[0x10];
8177  
8178  	u8         reserved_at_60[0x20];
8179  
8180  	u8         table_type[0x8];
8181  	u8         reserved_at_88[0x18];
8182  
8183  	u8         reserved_at_a0[0x8];
8184  	u8         table_id[0x18];
8185  
8186  	u8         group_id[0x20];
8187  
8188  	u8         reserved_at_e0[0x120];
8189  };
8190  
8191  struct mlx5_ifc_destroy_eq_out_bits {
8192  	u8         status[0x8];
8193  	u8         reserved_at_8[0x18];
8194  
8195  	u8         syndrome[0x20];
8196  
8197  	u8         reserved_at_40[0x40];
8198  };
8199  
8200  struct mlx5_ifc_destroy_eq_in_bits {
8201  	u8         opcode[0x10];
8202  	u8         reserved_at_10[0x10];
8203  
8204  	u8         reserved_at_20[0x10];
8205  	u8         op_mod[0x10];
8206  
8207  	u8         reserved_at_40[0x18];
8208  	u8         eq_number[0x8];
8209  
8210  	u8         reserved_at_60[0x20];
8211  };
8212  
8213  struct mlx5_ifc_destroy_dct_out_bits {
8214  	u8         status[0x8];
8215  	u8         reserved_at_8[0x18];
8216  
8217  	u8         syndrome[0x20];
8218  
8219  	u8         reserved_at_40[0x40];
8220  };
8221  
8222  struct mlx5_ifc_destroy_dct_in_bits {
8223  	u8         opcode[0x10];
8224  	u8         uid[0x10];
8225  
8226  	u8         reserved_at_20[0x10];
8227  	u8         op_mod[0x10];
8228  
8229  	u8         reserved_at_40[0x8];
8230  	u8         dctn[0x18];
8231  
8232  	u8         reserved_at_60[0x20];
8233  };
8234  
8235  struct mlx5_ifc_destroy_cq_out_bits {
8236  	u8         status[0x8];
8237  	u8         reserved_at_8[0x18];
8238  
8239  	u8         syndrome[0x20];
8240  
8241  	u8         reserved_at_40[0x40];
8242  };
8243  
8244  struct mlx5_ifc_destroy_cq_in_bits {
8245  	u8         opcode[0x10];
8246  	u8         uid[0x10];
8247  
8248  	u8         reserved_at_20[0x10];
8249  	u8         op_mod[0x10];
8250  
8251  	u8         reserved_at_40[0x8];
8252  	u8         cqn[0x18];
8253  
8254  	u8         reserved_at_60[0x20];
8255  };
8256  
8257  struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8258  	u8         status[0x8];
8259  	u8         reserved_at_8[0x18];
8260  
8261  	u8         syndrome[0x20];
8262  
8263  	u8         reserved_at_40[0x40];
8264  };
8265  
8266  struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8267  	u8         opcode[0x10];
8268  	u8         reserved_at_10[0x10];
8269  
8270  	u8         reserved_at_20[0x10];
8271  	u8         op_mod[0x10];
8272  
8273  	u8         reserved_at_40[0x20];
8274  
8275  	u8         reserved_at_60[0x10];
8276  	u8         vxlan_udp_port[0x10];
8277  };
8278  
8279  struct mlx5_ifc_delete_l2_table_entry_out_bits {
8280  	u8         status[0x8];
8281  	u8         reserved_at_8[0x18];
8282  
8283  	u8         syndrome[0x20];
8284  
8285  	u8         reserved_at_40[0x40];
8286  };
8287  
8288  struct mlx5_ifc_delete_l2_table_entry_in_bits {
8289  	u8         opcode[0x10];
8290  	u8         reserved_at_10[0x10];
8291  
8292  	u8         reserved_at_20[0x10];
8293  	u8         op_mod[0x10];
8294  
8295  	u8         reserved_at_40[0x60];
8296  
8297  	u8         reserved_at_a0[0x8];
8298  	u8         table_index[0x18];
8299  
8300  	u8         reserved_at_c0[0x140];
8301  };
8302  
8303  struct mlx5_ifc_delete_fte_out_bits {
8304  	u8         status[0x8];
8305  	u8         reserved_at_8[0x18];
8306  
8307  	u8         syndrome[0x20];
8308  
8309  	u8         reserved_at_40[0x40];
8310  };
8311  
8312  struct mlx5_ifc_delete_fte_in_bits {
8313  	u8         opcode[0x10];
8314  	u8         reserved_at_10[0x10];
8315  
8316  	u8         reserved_at_20[0x10];
8317  	u8         op_mod[0x10];
8318  
8319  	u8         other_vport[0x1];
8320  	u8         reserved_at_41[0xf];
8321  	u8         vport_number[0x10];
8322  
8323  	u8         reserved_at_60[0x20];
8324  
8325  	u8         table_type[0x8];
8326  	u8         reserved_at_88[0x18];
8327  
8328  	u8         reserved_at_a0[0x8];
8329  	u8         table_id[0x18];
8330  
8331  	u8         reserved_at_c0[0x40];
8332  
8333  	u8         flow_index[0x20];
8334  
8335  	u8         reserved_at_120[0xe0];
8336  };
8337  
8338  struct mlx5_ifc_dealloc_xrcd_out_bits {
8339  	u8         status[0x8];
8340  	u8         reserved_at_8[0x18];
8341  
8342  	u8         syndrome[0x20];
8343  
8344  	u8         reserved_at_40[0x40];
8345  };
8346  
8347  struct mlx5_ifc_dealloc_xrcd_in_bits {
8348  	u8         opcode[0x10];
8349  	u8         uid[0x10];
8350  
8351  	u8         reserved_at_20[0x10];
8352  	u8         op_mod[0x10];
8353  
8354  	u8         reserved_at_40[0x8];
8355  	u8         xrcd[0x18];
8356  
8357  	u8         reserved_at_60[0x20];
8358  };
8359  
8360  struct mlx5_ifc_dealloc_uar_out_bits {
8361  	u8         status[0x8];
8362  	u8         reserved_at_8[0x18];
8363  
8364  	u8         syndrome[0x20];
8365  
8366  	u8         reserved_at_40[0x40];
8367  };
8368  
8369  struct mlx5_ifc_dealloc_uar_in_bits {
8370  	u8         opcode[0x10];
8371  	u8         uid[0x10];
8372  
8373  	u8         reserved_at_20[0x10];
8374  	u8         op_mod[0x10];
8375  
8376  	u8         reserved_at_40[0x8];
8377  	u8         uar[0x18];
8378  
8379  	u8         reserved_at_60[0x20];
8380  };
8381  
8382  struct mlx5_ifc_dealloc_transport_domain_out_bits {
8383  	u8         status[0x8];
8384  	u8         reserved_at_8[0x18];
8385  
8386  	u8         syndrome[0x20];
8387  
8388  	u8         reserved_at_40[0x40];
8389  };
8390  
8391  struct mlx5_ifc_dealloc_transport_domain_in_bits {
8392  	u8         opcode[0x10];
8393  	u8         uid[0x10];
8394  
8395  	u8         reserved_at_20[0x10];
8396  	u8         op_mod[0x10];
8397  
8398  	u8         reserved_at_40[0x8];
8399  	u8         transport_domain[0x18];
8400  
8401  	u8         reserved_at_60[0x20];
8402  };
8403  
8404  struct mlx5_ifc_dealloc_q_counter_out_bits {
8405  	u8         status[0x8];
8406  	u8         reserved_at_8[0x18];
8407  
8408  	u8         syndrome[0x20];
8409  
8410  	u8         reserved_at_40[0x40];
8411  };
8412  
8413  struct mlx5_ifc_dealloc_q_counter_in_bits {
8414  	u8         opcode[0x10];
8415  	u8         reserved_at_10[0x10];
8416  
8417  	u8         reserved_at_20[0x10];
8418  	u8         op_mod[0x10];
8419  
8420  	u8         reserved_at_40[0x18];
8421  	u8         counter_set_id[0x8];
8422  
8423  	u8         reserved_at_60[0x20];
8424  };
8425  
8426  struct mlx5_ifc_dealloc_pd_out_bits {
8427  	u8         status[0x8];
8428  	u8         reserved_at_8[0x18];
8429  
8430  	u8         syndrome[0x20];
8431  
8432  	u8         reserved_at_40[0x40];
8433  };
8434  
8435  struct mlx5_ifc_dealloc_pd_in_bits {
8436  	u8         opcode[0x10];
8437  	u8         uid[0x10];
8438  
8439  	u8         reserved_at_20[0x10];
8440  	u8         op_mod[0x10];
8441  
8442  	u8         reserved_at_40[0x8];
8443  	u8         pd[0x18];
8444  
8445  	u8         reserved_at_60[0x20];
8446  };
8447  
8448  struct mlx5_ifc_dealloc_flow_counter_out_bits {
8449  	u8         status[0x8];
8450  	u8         reserved_at_8[0x18];
8451  
8452  	u8         syndrome[0x20];
8453  
8454  	u8         reserved_at_40[0x40];
8455  };
8456  
8457  struct mlx5_ifc_dealloc_flow_counter_in_bits {
8458  	u8         opcode[0x10];
8459  	u8         reserved_at_10[0x10];
8460  
8461  	u8         reserved_at_20[0x10];
8462  	u8         op_mod[0x10];
8463  
8464  	u8         flow_counter_id[0x20];
8465  
8466  	u8         reserved_at_60[0x20];
8467  };
8468  
8469  struct mlx5_ifc_create_xrq_out_bits {
8470  	u8         status[0x8];
8471  	u8         reserved_at_8[0x18];
8472  
8473  	u8         syndrome[0x20];
8474  
8475  	u8         reserved_at_40[0x8];
8476  	u8         xrqn[0x18];
8477  
8478  	u8         reserved_at_60[0x20];
8479  };
8480  
8481  struct mlx5_ifc_create_xrq_in_bits {
8482  	u8         opcode[0x10];
8483  	u8         uid[0x10];
8484  
8485  	u8         reserved_at_20[0x10];
8486  	u8         op_mod[0x10];
8487  
8488  	u8         reserved_at_40[0x40];
8489  
8490  	struct mlx5_ifc_xrqc_bits xrq_context;
8491  };
8492  
8493  struct mlx5_ifc_create_xrc_srq_out_bits {
8494  	u8         status[0x8];
8495  	u8         reserved_at_8[0x18];
8496  
8497  	u8         syndrome[0x20];
8498  
8499  	u8         reserved_at_40[0x8];
8500  	u8         xrc_srqn[0x18];
8501  
8502  	u8         reserved_at_60[0x20];
8503  };
8504  
8505  struct mlx5_ifc_create_xrc_srq_in_bits {
8506  	u8         opcode[0x10];
8507  	u8         uid[0x10];
8508  
8509  	u8         reserved_at_20[0x10];
8510  	u8         op_mod[0x10];
8511  
8512  	u8         reserved_at_40[0x40];
8513  
8514  	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8515  
8516  	u8         reserved_at_280[0x60];
8517  
8518  	u8         xrc_srq_umem_valid[0x1];
8519  	u8         reserved_at_2e1[0x1f];
8520  
8521  	u8         reserved_at_300[0x580];
8522  
8523  	u8         pas[][0x40];
8524  };
8525  
8526  struct mlx5_ifc_create_tis_out_bits {
8527  	u8         status[0x8];
8528  	u8         reserved_at_8[0x18];
8529  
8530  	u8         syndrome[0x20];
8531  
8532  	u8         reserved_at_40[0x8];
8533  	u8         tisn[0x18];
8534  
8535  	u8         reserved_at_60[0x20];
8536  };
8537  
8538  struct mlx5_ifc_create_tis_in_bits {
8539  	u8         opcode[0x10];
8540  	u8         uid[0x10];
8541  
8542  	u8         reserved_at_20[0x10];
8543  	u8         op_mod[0x10];
8544  
8545  	u8         reserved_at_40[0xc0];
8546  
8547  	struct mlx5_ifc_tisc_bits ctx;
8548  };
8549  
8550  struct mlx5_ifc_create_tir_out_bits {
8551  	u8         status[0x8];
8552  	u8         icm_address_63_40[0x18];
8553  
8554  	u8         syndrome[0x20];
8555  
8556  	u8         icm_address_39_32[0x8];
8557  	u8         tirn[0x18];
8558  
8559  	u8         icm_address_31_0[0x20];
8560  };
8561  
8562  struct mlx5_ifc_create_tir_in_bits {
8563  	u8         opcode[0x10];
8564  	u8         uid[0x10];
8565  
8566  	u8         reserved_at_20[0x10];
8567  	u8         op_mod[0x10];
8568  
8569  	u8         reserved_at_40[0xc0];
8570  
8571  	struct mlx5_ifc_tirc_bits ctx;
8572  };
8573  
8574  struct mlx5_ifc_create_srq_out_bits {
8575  	u8         status[0x8];
8576  	u8         reserved_at_8[0x18];
8577  
8578  	u8         syndrome[0x20];
8579  
8580  	u8         reserved_at_40[0x8];
8581  	u8         srqn[0x18];
8582  
8583  	u8         reserved_at_60[0x20];
8584  };
8585  
8586  struct mlx5_ifc_create_srq_in_bits {
8587  	u8         opcode[0x10];
8588  	u8         uid[0x10];
8589  
8590  	u8         reserved_at_20[0x10];
8591  	u8         op_mod[0x10];
8592  
8593  	u8         reserved_at_40[0x40];
8594  
8595  	struct mlx5_ifc_srqc_bits srq_context_entry;
8596  
8597  	u8         reserved_at_280[0x600];
8598  
8599  	u8         pas[][0x40];
8600  };
8601  
8602  struct mlx5_ifc_create_sq_out_bits {
8603  	u8         status[0x8];
8604  	u8         reserved_at_8[0x18];
8605  
8606  	u8         syndrome[0x20];
8607  
8608  	u8         reserved_at_40[0x8];
8609  	u8         sqn[0x18];
8610  
8611  	u8         reserved_at_60[0x20];
8612  };
8613  
8614  struct mlx5_ifc_create_sq_in_bits {
8615  	u8         opcode[0x10];
8616  	u8         uid[0x10];
8617  
8618  	u8         reserved_at_20[0x10];
8619  	u8         op_mod[0x10];
8620  
8621  	u8         reserved_at_40[0xc0];
8622  
8623  	struct mlx5_ifc_sqc_bits ctx;
8624  };
8625  
8626  struct mlx5_ifc_create_scheduling_element_out_bits {
8627  	u8         status[0x8];
8628  	u8         reserved_at_8[0x18];
8629  
8630  	u8         syndrome[0x20];
8631  
8632  	u8         reserved_at_40[0x40];
8633  
8634  	u8         scheduling_element_id[0x20];
8635  
8636  	u8         reserved_at_a0[0x160];
8637  };
8638  
8639  struct mlx5_ifc_create_scheduling_element_in_bits {
8640  	u8         opcode[0x10];
8641  	u8         reserved_at_10[0x10];
8642  
8643  	u8         reserved_at_20[0x10];
8644  	u8         op_mod[0x10];
8645  
8646  	u8         scheduling_hierarchy[0x8];
8647  	u8         reserved_at_48[0x18];
8648  
8649  	u8         reserved_at_60[0xa0];
8650  
8651  	struct mlx5_ifc_scheduling_context_bits scheduling_context;
8652  
8653  	u8         reserved_at_300[0x100];
8654  };
8655  
8656  struct mlx5_ifc_create_rqt_out_bits {
8657  	u8         status[0x8];
8658  	u8         reserved_at_8[0x18];
8659  
8660  	u8         syndrome[0x20];
8661  
8662  	u8         reserved_at_40[0x8];
8663  	u8         rqtn[0x18];
8664  
8665  	u8         reserved_at_60[0x20];
8666  };
8667  
8668  struct mlx5_ifc_create_rqt_in_bits {
8669  	u8         opcode[0x10];
8670  	u8         uid[0x10];
8671  
8672  	u8         reserved_at_20[0x10];
8673  	u8         op_mod[0x10];
8674  
8675  	u8         reserved_at_40[0xc0];
8676  
8677  	struct mlx5_ifc_rqtc_bits rqt_context;
8678  };
8679  
8680  struct mlx5_ifc_create_rq_out_bits {
8681  	u8         status[0x8];
8682  	u8         reserved_at_8[0x18];
8683  
8684  	u8         syndrome[0x20];
8685  
8686  	u8         reserved_at_40[0x8];
8687  	u8         rqn[0x18];
8688  
8689  	u8         reserved_at_60[0x20];
8690  };
8691  
8692  struct mlx5_ifc_create_rq_in_bits {
8693  	u8         opcode[0x10];
8694  	u8         uid[0x10];
8695  
8696  	u8         reserved_at_20[0x10];
8697  	u8         op_mod[0x10];
8698  
8699  	u8         reserved_at_40[0xc0];
8700  
8701  	struct mlx5_ifc_rqc_bits ctx;
8702  };
8703  
8704  struct mlx5_ifc_create_rmp_out_bits {
8705  	u8         status[0x8];
8706  	u8         reserved_at_8[0x18];
8707  
8708  	u8         syndrome[0x20];
8709  
8710  	u8         reserved_at_40[0x8];
8711  	u8         rmpn[0x18];
8712  
8713  	u8         reserved_at_60[0x20];
8714  };
8715  
8716  struct mlx5_ifc_create_rmp_in_bits {
8717  	u8         opcode[0x10];
8718  	u8         uid[0x10];
8719  
8720  	u8         reserved_at_20[0x10];
8721  	u8         op_mod[0x10];
8722  
8723  	u8         reserved_at_40[0xc0];
8724  
8725  	struct mlx5_ifc_rmpc_bits ctx;
8726  };
8727  
8728  struct mlx5_ifc_create_qp_out_bits {
8729  	u8         status[0x8];
8730  	u8         reserved_at_8[0x18];
8731  
8732  	u8         syndrome[0x20];
8733  
8734  	u8         reserved_at_40[0x8];
8735  	u8         qpn[0x18];
8736  
8737  	u8         ece[0x20];
8738  };
8739  
8740  struct mlx5_ifc_create_qp_in_bits {
8741  	u8         opcode[0x10];
8742  	u8         uid[0x10];
8743  
8744  	u8         reserved_at_20[0x10];
8745  	u8         op_mod[0x10];
8746  
8747  	u8         qpc_ext[0x1];
8748  	u8         reserved_at_41[0x7];
8749  	u8         input_qpn[0x18];
8750  
8751  	u8         reserved_at_60[0x20];
8752  	u8         opt_param_mask[0x20];
8753  
8754  	u8         ece[0x20];
8755  
8756  	struct mlx5_ifc_qpc_bits qpc;
8757  
8758  	u8         reserved_at_800[0x60];
8759  
8760  	u8         wq_umem_valid[0x1];
8761  	u8         reserved_at_861[0x1f];
8762  
8763  	u8         pas[][0x40];
8764  };
8765  
8766  struct mlx5_ifc_create_psv_out_bits {
8767  	u8         status[0x8];
8768  	u8         reserved_at_8[0x18];
8769  
8770  	u8         syndrome[0x20];
8771  
8772  	u8         reserved_at_40[0x40];
8773  
8774  	u8         reserved_at_80[0x8];
8775  	u8         psv0_index[0x18];
8776  
8777  	u8         reserved_at_a0[0x8];
8778  	u8         psv1_index[0x18];
8779  
8780  	u8         reserved_at_c0[0x8];
8781  	u8         psv2_index[0x18];
8782  
8783  	u8         reserved_at_e0[0x8];
8784  	u8         psv3_index[0x18];
8785  };
8786  
8787  struct mlx5_ifc_create_psv_in_bits {
8788  	u8         opcode[0x10];
8789  	u8         reserved_at_10[0x10];
8790  
8791  	u8         reserved_at_20[0x10];
8792  	u8         op_mod[0x10];
8793  
8794  	u8         num_psv[0x4];
8795  	u8         reserved_at_44[0x4];
8796  	u8         pd[0x18];
8797  
8798  	u8         reserved_at_60[0x20];
8799  };
8800  
8801  struct mlx5_ifc_create_mkey_out_bits {
8802  	u8         status[0x8];
8803  	u8         reserved_at_8[0x18];
8804  
8805  	u8         syndrome[0x20];
8806  
8807  	u8         reserved_at_40[0x8];
8808  	u8         mkey_index[0x18];
8809  
8810  	u8         reserved_at_60[0x20];
8811  };
8812  
8813  struct mlx5_ifc_create_mkey_in_bits {
8814  	u8         opcode[0x10];
8815  	u8         uid[0x10];
8816  
8817  	u8         reserved_at_20[0x10];
8818  	u8         op_mod[0x10];
8819  
8820  	u8         reserved_at_40[0x20];
8821  
8822  	u8         pg_access[0x1];
8823  	u8         mkey_umem_valid[0x1];
8824  	u8         reserved_at_62[0x1e];
8825  
8826  	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8827  
8828  	u8         reserved_at_280[0x80];
8829  
8830  	u8         translations_octword_actual_size[0x20];
8831  
8832  	u8         reserved_at_320[0x560];
8833  
8834  	u8         klm_pas_mtt[][0x20];
8835  };
8836  
8837  enum {
8838  	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
8839  	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
8840  	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
8841  	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
8842  	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
8843  	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
8844  	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
8845  };
8846  
8847  struct mlx5_ifc_create_flow_table_out_bits {
8848  	u8         status[0x8];
8849  	u8         icm_address_63_40[0x18];
8850  
8851  	u8         syndrome[0x20];
8852  
8853  	u8         icm_address_39_32[0x8];
8854  	u8         table_id[0x18];
8855  
8856  	u8         icm_address_31_0[0x20];
8857  };
8858  
8859  struct mlx5_ifc_create_flow_table_in_bits {
8860  	u8         opcode[0x10];
8861  	u8         uid[0x10];
8862  
8863  	u8         reserved_at_20[0x10];
8864  	u8         op_mod[0x10];
8865  
8866  	u8         other_vport[0x1];
8867  	u8         reserved_at_41[0xf];
8868  	u8         vport_number[0x10];
8869  
8870  	u8         reserved_at_60[0x20];
8871  
8872  	u8         table_type[0x8];
8873  	u8         reserved_at_88[0x18];
8874  
8875  	u8         reserved_at_a0[0x20];
8876  
8877  	struct mlx5_ifc_flow_table_context_bits flow_table_context;
8878  };
8879  
8880  struct mlx5_ifc_create_flow_group_out_bits {
8881  	u8         status[0x8];
8882  	u8         reserved_at_8[0x18];
8883  
8884  	u8         syndrome[0x20];
8885  
8886  	u8         reserved_at_40[0x8];
8887  	u8         group_id[0x18];
8888  
8889  	u8         reserved_at_60[0x20];
8890  };
8891  
8892  enum {
8893  	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
8894  	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
8895  };
8896  
8897  enum {
8898  	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8899  	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8900  	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8901  	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8902  };
8903  
8904  struct mlx5_ifc_create_flow_group_in_bits {
8905  	u8         opcode[0x10];
8906  	u8         reserved_at_10[0x10];
8907  
8908  	u8         reserved_at_20[0x10];
8909  	u8         op_mod[0x10];
8910  
8911  	u8         other_vport[0x1];
8912  	u8         reserved_at_41[0xf];
8913  	u8         vport_number[0x10];
8914  
8915  	u8         reserved_at_60[0x20];
8916  
8917  	u8         table_type[0x8];
8918  	u8         reserved_at_88[0x4];
8919  	u8         group_type[0x4];
8920  	u8         reserved_at_90[0x10];
8921  
8922  	u8         reserved_at_a0[0x8];
8923  	u8         table_id[0x18];
8924  
8925  	u8         source_eswitch_owner_vhca_id_valid[0x1];
8926  
8927  	u8         reserved_at_c1[0x1f];
8928  
8929  	u8         start_flow_index[0x20];
8930  
8931  	u8         reserved_at_100[0x20];
8932  
8933  	u8         end_flow_index[0x20];
8934  
8935  	u8         reserved_at_140[0x10];
8936  	u8         match_definer_id[0x10];
8937  
8938  	u8         reserved_at_160[0x80];
8939  
8940  	u8         reserved_at_1e0[0x18];
8941  	u8         match_criteria_enable[0x8];
8942  
8943  	struct mlx5_ifc_fte_match_param_bits match_criteria;
8944  
8945  	u8         reserved_at_1200[0xe00];
8946  };
8947  
8948  struct mlx5_ifc_create_eq_out_bits {
8949  	u8         status[0x8];
8950  	u8         reserved_at_8[0x18];
8951  
8952  	u8         syndrome[0x20];
8953  
8954  	u8         reserved_at_40[0x18];
8955  	u8         eq_number[0x8];
8956  
8957  	u8         reserved_at_60[0x20];
8958  };
8959  
8960  struct mlx5_ifc_create_eq_in_bits {
8961  	u8         opcode[0x10];
8962  	u8         uid[0x10];
8963  
8964  	u8         reserved_at_20[0x10];
8965  	u8         op_mod[0x10];
8966  
8967  	u8         reserved_at_40[0x40];
8968  
8969  	struct mlx5_ifc_eqc_bits eq_context_entry;
8970  
8971  	u8         reserved_at_280[0x40];
8972  
8973  	u8         event_bitmask[4][0x40];
8974  
8975  	u8         reserved_at_3c0[0x4c0];
8976  
8977  	u8         pas[][0x40];
8978  };
8979  
8980  struct mlx5_ifc_create_dct_out_bits {
8981  	u8         status[0x8];
8982  	u8         reserved_at_8[0x18];
8983  
8984  	u8         syndrome[0x20];
8985  
8986  	u8         reserved_at_40[0x8];
8987  	u8         dctn[0x18];
8988  
8989  	u8         ece[0x20];
8990  };
8991  
8992  struct mlx5_ifc_create_dct_in_bits {
8993  	u8         opcode[0x10];
8994  	u8         uid[0x10];
8995  
8996  	u8         reserved_at_20[0x10];
8997  	u8         op_mod[0x10];
8998  
8999  	u8         reserved_at_40[0x40];
9000  
9001  	struct mlx5_ifc_dctc_bits dct_context_entry;
9002  
9003  	u8         reserved_at_280[0x180];
9004  };
9005  
9006  struct mlx5_ifc_create_cq_out_bits {
9007  	u8         status[0x8];
9008  	u8         reserved_at_8[0x18];
9009  
9010  	u8         syndrome[0x20];
9011  
9012  	u8         reserved_at_40[0x8];
9013  	u8         cqn[0x18];
9014  
9015  	u8         reserved_at_60[0x20];
9016  };
9017  
9018  struct mlx5_ifc_create_cq_in_bits {
9019  	u8         opcode[0x10];
9020  	u8         uid[0x10];
9021  
9022  	u8         reserved_at_20[0x10];
9023  	u8         op_mod[0x10];
9024  
9025  	u8         reserved_at_40[0x40];
9026  
9027  	struct mlx5_ifc_cqc_bits cq_context;
9028  
9029  	u8         reserved_at_280[0x60];
9030  
9031  	u8         cq_umem_valid[0x1];
9032  	u8         reserved_at_2e1[0x59f];
9033  
9034  	u8         pas[][0x40];
9035  };
9036  
9037  struct mlx5_ifc_config_int_moderation_out_bits {
9038  	u8         status[0x8];
9039  	u8         reserved_at_8[0x18];
9040  
9041  	u8         syndrome[0x20];
9042  
9043  	u8         reserved_at_40[0x4];
9044  	u8         min_delay[0xc];
9045  	u8         int_vector[0x10];
9046  
9047  	u8         reserved_at_60[0x20];
9048  };
9049  
9050  enum {
9051  	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9052  	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9053  };
9054  
9055  struct mlx5_ifc_config_int_moderation_in_bits {
9056  	u8         opcode[0x10];
9057  	u8         reserved_at_10[0x10];
9058  
9059  	u8         reserved_at_20[0x10];
9060  	u8         op_mod[0x10];
9061  
9062  	u8         reserved_at_40[0x4];
9063  	u8         min_delay[0xc];
9064  	u8         int_vector[0x10];
9065  
9066  	u8         reserved_at_60[0x20];
9067  };
9068  
9069  struct mlx5_ifc_attach_to_mcg_out_bits {
9070  	u8         status[0x8];
9071  	u8         reserved_at_8[0x18];
9072  
9073  	u8         syndrome[0x20];
9074  
9075  	u8         reserved_at_40[0x40];
9076  };
9077  
9078  struct mlx5_ifc_attach_to_mcg_in_bits {
9079  	u8         opcode[0x10];
9080  	u8         uid[0x10];
9081  
9082  	u8         reserved_at_20[0x10];
9083  	u8         op_mod[0x10];
9084  
9085  	u8         reserved_at_40[0x8];
9086  	u8         qpn[0x18];
9087  
9088  	u8         reserved_at_60[0x20];
9089  
9090  	u8         multicast_gid[16][0x8];
9091  };
9092  
9093  struct mlx5_ifc_arm_xrq_out_bits {
9094  	u8         status[0x8];
9095  	u8         reserved_at_8[0x18];
9096  
9097  	u8         syndrome[0x20];
9098  
9099  	u8         reserved_at_40[0x40];
9100  };
9101  
9102  struct mlx5_ifc_arm_xrq_in_bits {
9103  	u8         opcode[0x10];
9104  	u8         reserved_at_10[0x10];
9105  
9106  	u8         reserved_at_20[0x10];
9107  	u8         op_mod[0x10];
9108  
9109  	u8         reserved_at_40[0x8];
9110  	u8         xrqn[0x18];
9111  
9112  	u8         reserved_at_60[0x10];
9113  	u8         lwm[0x10];
9114  };
9115  
9116  struct mlx5_ifc_arm_xrc_srq_out_bits {
9117  	u8         status[0x8];
9118  	u8         reserved_at_8[0x18];
9119  
9120  	u8         syndrome[0x20];
9121  
9122  	u8         reserved_at_40[0x40];
9123  };
9124  
9125  enum {
9126  	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9127  };
9128  
9129  struct mlx5_ifc_arm_xrc_srq_in_bits {
9130  	u8         opcode[0x10];
9131  	u8         uid[0x10];
9132  
9133  	u8         reserved_at_20[0x10];
9134  	u8         op_mod[0x10];
9135  
9136  	u8         reserved_at_40[0x8];
9137  	u8         xrc_srqn[0x18];
9138  
9139  	u8         reserved_at_60[0x10];
9140  	u8         lwm[0x10];
9141  };
9142  
9143  struct mlx5_ifc_arm_rq_out_bits {
9144  	u8         status[0x8];
9145  	u8         reserved_at_8[0x18];
9146  
9147  	u8         syndrome[0x20];
9148  
9149  	u8         reserved_at_40[0x40];
9150  };
9151  
9152  enum {
9153  	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9154  	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9155  };
9156  
9157  struct mlx5_ifc_arm_rq_in_bits {
9158  	u8         opcode[0x10];
9159  	u8         uid[0x10];
9160  
9161  	u8         reserved_at_20[0x10];
9162  	u8         op_mod[0x10];
9163  
9164  	u8         reserved_at_40[0x8];
9165  	u8         srq_number[0x18];
9166  
9167  	u8         reserved_at_60[0x10];
9168  	u8         lwm[0x10];
9169  };
9170  
9171  struct mlx5_ifc_arm_dct_out_bits {
9172  	u8         status[0x8];
9173  	u8         reserved_at_8[0x18];
9174  
9175  	u8         syndrome[0x20];
9176  
9177  	u8         reserved_at_40[0x40];
9178  };
9179  
9180  struct mlx5_ifc_arm_dct_in_bits {
9181  	u8         opcode[0x10];
9182  	u8         reserved_at_10[0x10];
9183  
9184  	u8         reserved_at_20[0x10];
9185  	u8         op_mod[0x10];
9186  
9187  	u8         reserved_at_40[0x8];
9188  	u8         dct_number[0x18];
9189  
9190  	u8         reserved_at_60[0x20];
9191  };
9192  
9193  struct mlx5_ifc_alloc_xrcd_out_bits {
9194  	u8         status[0x8];
9195  	u8         reserved_at_8[0x18];
9196  
9197  	u8         syndrome[0x20];
9198  
9199  	u8         reserved_at_40[0x8];
9200  	u8         xrcd[0x18];
9201  
9202  	u8         reserved_at_60[0x20];
9203  };
9204  
9205  struct mlx5_ifc_alloc_xrcd_in_bits {
9206  	u8         opcode[0x10];
9207  	u8         uid[0x10];
9208  
9209  	u8         reserved_at_20[0x10];
9210  	u8         op_mod[0x10];
9211  
9212  	u8         reserved_at_40[0x40];
9213  };
9214  
9215  struct mlx5_ifc_alloc_uar_out_bits {
9216  	u8         status[0x8];
9217  	u8         reserved_at_8[0x18];
9218  
9219  	u8         syndrome[0x20];
9220  
9221  	u8         reserved_at_40[0x8];
9222  	u8         uar[0x18];
9223  
9224  	u8         reserved_at_60[0x20];
9225  };
9226  
9227  struct mlx5_ifc_alloc_uar_in_bits {
9228  	u8         opcode[0x10];
9229  	u8         uid[0x10];
9230  
9231  	u8         reserved_at_20[0x10];
9232  	u8         op_mod[0x10];
9233  
9234  	u8         reserved_at_40[0x40];
9235  };
9236  
9237  struct mlx5_ifc_alloc_transport_domain_out_bits {
9238  	u8         status[0x8];
9239  	u8         reserved_at_8[0x18];
9240  
9241  	u8         syndrome[0x20];
9242  
9243  	u8         reserved_at_40[0x8];
9244  	u8         transport_domain[0x18];
9245  
9246  	u8         reserved_at_60[0x20];
9247  };
9248  
9249  struct mlx5_ifc_alloc_transport_domain_in_bits {
9250  	u8         opcode[0x10];
9251  	u8         uid[0x10];
9252  
9253  	u8         reserved_at_20[0x10];
9254  	u8         op_mod[0x10];
9255  
9256  	u8         reserved_at_40[0x40];
9257  };
9258  
9259  struct mlx5_ifc_alloc_q_counter_out_bits {
9260  	u8         status[0x8];
9261  	u8         reserved_at_8[0x18];
9262  
9263  	u8         syndrome[0x20];
9264  
9265  	u8         reserved_at_40[0x18];
9266  	u8         counter_set_id[0x8];
9267  
9268  	u8         reserved_at_60[0x20];
9269  };
9270  
9271  struct mlx5_ifc_alloc_q_counter_in_bits {
9272  	u8         opcode[0x10];
9273  	u8         uid[0x10];
9274  
9275  	u8         reserved_at_20[0x10];
9276  	u8         op_mod[0x10];
9277  
9278  	u8         reserved_at_40[0x40];
9279  };
9280  
9281  struct mlx5_ifc_alloc_pd_out_bits {
9282  	u8         status[0x8];
9283  	u8         reserved_at_8[0x18];
9284  
9285  	u8         syndrome[0x20];
9286  
9287  	u8         reserved_at_40[0x8];
9288  	u8         pd[0x18];
9289  
9290  	u8         reserved_at_60[0x20];
9291  };
9292  
9293  struct mlx5_ifc_alloc_pd_in_bits {
9294  	u8         opcode[0x10];
9295  	u8         uid[0x10];
9296  
9297  	u8         reserved_at_20[0x10];
9298  	u8         op_mod[0x10];
9299  
9300  	u8         reserved_at_40[0x40];
9301  };
9302  
9303  struct mlx5_ifc_alloc_flow_counter_out_bits {
9304  	u8         status[0x8];
9305  	u8         reserved_at_8[0x18];
9306  
9307  	u8         syndrome[0x20];
9308  
9309  	u8         flow_counter_id[0x20];
9310  
9311  	u8         reserved_at_60[0x20];
9312  };
9313  
9314  struct mlx5_ifc_alloc_flow_counter_in_bits {
9315  	u8         opcode[0x10];
9316  	u8         reserved_at_10[0x10];
9317  
9318  	u8         reserved_at_20[0x10];
9319  	u8         op_mod[0x10];
9320  
9321  	u8         reserved_at_40[0x33];
9322  	u8         flow_counter_bulk_log_size[0x5];
9323  	u8         flow_counter_bulk[0x8];
9324  };
9325  
9326  struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9327  	u8         status[0x8];
9328  	u8         reserved_at_8[0x18];
9329  
9330  	u8         syndrome[0x20];
9331  
9332  	u8         reserved_at_40[0x40];
9333  };
9334  
9335  struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9336  	u8         opcode[0x10];
9337  	u8         reserved_at_10[0x10];
9338  
9339  	u8         reserved_at_20[0x10];
9340  	u8         op_mod[0x10];
9341  
9342  	u8         reserved_at_40[0x20];
9343  
9344  	u8         reserved_at_60[0x10];
9345  	u8         vxlan_udp_port[0x10];
9346  };
9347  
9348  struct mlx5_ifc_set_pp_rate_limit_out_bits {
9349  	u8         status[0x8];
9350  	u8         reserved_at_8[0x18];
9351  
9352  	u8         syndrome[0x20];
9353  
9354  	u8         reserved_at_40[0x40];
9355  };
9356  
9357  struct mlx5_ifc_set_pp_rate_limit_context_bits {
9358  	u8         rate_limit[0x20];
9359  
9360  	u8	   burst_upper_bound[0x20];
9361  
9362  	u8         reserved_at_40[0x10];
9363  	u8	   typical_packet_size[0x10];
9364  
9365  	u8         reserved_at_60[0x120];
9366  };
9367  
9368  struct mlx5_ifc_set_pp_rate_limit_in_bits {
9369  	u8         opcode[0x10];
9370  	u8         uid[0x10];
9371  
9372  	u8         reserved_at_20[0x10];
9373  	u8         op_mod[0x10];
9374  
9375  	u8         reserved_at_40[0x10];
9376  	u8         rate_limit_index[0x10];
9377  
9378  	u8         reserved_at_60[0x20];
9379  
9380  	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9381  };
9382  
9383  struct mlx5_ifc_access_register_out_bits {
9384  	u8         status[0x8];
9385  	u8         reserved_at_8[0x18];
9386  
9387  	u8         syndrome[0x20];
9388  
9389  	u8         reserved_at_40[0x40];
9390  
9391  	u8         register_data[][0x20];
9392  };
9393  
9394  enum {
9395  	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9396  	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9397  };
9398  
9399  struct mlx5_ifc_access_register_in_bits {
9400  	u8         opcode[0x10];
9401  	u8         reserved_at_10[0x10];
9402  
9403  	u8         reserved_at_20[0x10];
9404  	u8         op_mod[0x10];
9405  
9406  	u8         reserved_at_40[0x10];
9407  	u8         register_id[0x10];
9408  
9409  	u8         argument[0x20];
9410  
9411  	u8         register_data[][0x20];
9412  };
9413  
9414  struct mlx5_ifc_sltp_reg_bits {
9415  	u8         status[0x4];
9416  	u8         version[0x4];
9417  	u8         local_port[0x8];
9418  	u8         pnat[0x2];
9419  	u8         reserved_at_12[0x2];
9420  	u8         lane[0x4];
9421  	u8         reserved_at_18[0x8];
9422  
9423  	u8         reserved_at_20[0x20];
9424  
9425  	u8         reserved_at_40[0x7];
9426  	u8         polarity[0x1];
9427  	u8         ob_tap0[0x8];
9428  	u8         ob_tap1[0x8];
9429  	u8         ob_tap2[0x8];
9430  
9431  	u8         reserved_at_60[0xc];
9432  	u8         ob_preemp_mode[0x4];
9433  	u8         ob_reg[0x8];
9434  	u8         ob_bias[0x8];
9435  
9436  	u8         reserved_at_80[0x20];
9437  };
9438  
9439  struct mlx5_ifc_slrg_reg_bits {
9440  	u8         status[0x4];
9441  	u8         version[0x4];
9442  	u8         local_port[0x8];
9443  	u8         pnat[0x2];
9444  	u8         reserved_at_12[0x2];
9445  	u8         lane[0x4];
9446  	u8         reserved_at_18[0x8];
9447  
9448  	u8         time_to_link_up[0x10];
9449  	u8         reserved_at_30[0xc];
9450  	u8         grade_lane_speed[0x4];
9451  
9452  	u8         grade_version[0x8];
9453  	u8         grade[0x18];
9454  
9455  	u8         reserved_at_60[0x4];
9456  	u8         height_grade_type[0x4];
9457  	u8         height_grade[0x18];
9458  
9459  	u8         height_dz[0x10];
9460  	u8         height_dv[0x10];
9461  
9462  	u8         reserved_at_a0[0x10];
9463  	u8         height_sigma[0x10];
9464  
9465  	u8         reserved_at_c0[0x20];
9466  
9467  	u8         reserved_at_e0[0x4];
9468  	u8         phase_grade_type[0x4];
9469  	u8         phase_grade[0x18];
9470  
9471  	u8         reserved_at_100[0x8];
9472  	u8         phase_eo_pos[0x8];
9473  	u8         reserved_at_110[0x8];
9474  	u8         phase_eo_neg[0x8];
9475  
9476  	u8         ffe_set_tested[0x10];
9477  	u8         test_errors_per_lane[0x10];
9478  };
9479  
9480  struct mlx5_ifc_pvlc_reg_bits {
9481  	u8         reserved_at_0[0x8];
9482  	u8         local_port[0x8];
9483  	u8         reserved_at_10[0x10];
9484  
9485  	u8         reserved_at_20[0x1c];
9486  	u8         vl_hw_cap[0x4];
9487  
9488  	u8         reserved_at_40[0x1c];
9489  	u8         vl_admin[0x4];
9490  
9491  	u8         reserved_at_60[0x1c];
9492  	u8         vl_operational[0x4];
9493  };
9494  
9495  struct mlx5_ifc_pude_reg_bits {
9496  	u8         swid[0x8];
9497  	u8         local_port[0x8];
9498  	u8         reserved_at_10[0x4];
9499  	u8         admin_status[0x4];
9500  	u8         reserved_at_18[0x4];
9501  	u8         oper_status[0x4];
9502  
9503  	u8         reserved_at_20[0x60];
9504  };
9505  
9506  struct mlx5_ifc_ptys_reg_bits {
9507  	u8         reserved_at_0[0x1];
9508  	u8         an_disable_admin[0x1];
9509  	u8         an_disable_cap[0x1];
9510  	u8         reserved_at_3[0x5];
9511  	u8         local_port[0x8];
9512  	u8         reserved_at_10[0xd];
9513  	u8         proto_mask[0x3];
9514  
9515  	u8         an_status[0x4];
9516  	u8         reserved_at_24[0xc];
9517  	u8         data_rate_oper[0x10];
9518  
9519  	u8         ext_eth_proto_capability[0x20];
9520  
9521  	u8         eth_proto_capability[0x20];
9522  
9523  	u8         ib_link_width_capability[0x10];
9524  	u8         ib_proto_capability[0x10];
9525  
9526  	u8         ext_eth_proto_admin[0x20];
9527  
9528  	u8         eth_proto_admin[0x20];
9529  
9530  	u8         ib_link_width_admin[0x10];
9531  	u8         ib_proto_admin[0x10];
9532  
9533  	u8         ext_eth_proto_oper[0x20];
9534  
9535  	u8         eth_proto_oper[0x20];
9536  
9537  	u8         ib_link_width_oper[0x10];
9538  	u8         ib_proto_oper[0x10];
9539  
9540  	u8         reserved_at_160[0x1c];
9541  	u8         connector_type[0x4];
9542  
9543  	u8         eth_proto_lp_advertise[0x20];
9544  
9545  	u8         reserved_at_1a0[0x60];
9546  };
9547  
9548  struct mlx5_ifc_mlcr_reg_bits {
9549  	u8         reserved_at_0[0x8];
9550  	u8         local_port[0x8];
9551  	u8         reserved_at_10[0x20];
9552  
9553  	u8         beacon_duration[0x10];
9554  	u8         reserved_at_40[0x10];
9555  
9556  	u8         beacon_remain[0x10];
9557  };
9558  
9559  struct mlx5_ifc_ptas_reg_bits {
9560  	u8         reserved_at_0[0x20];
9561  
9562  	u8         algorithm_options[0x10];
9563  	u8         reserved_at_30[0x4];
9564  	u8         repetitions_mode[0x4];
9565  	u8         num_of_repetitions[0x8];
9566  
9567  	u8         grade_version[0x8];
9568  	u8         height_grade_type[0x4];
9569  	u8         phase_grade_type[0x4];
9570  	u8         height_grade_weight[0x8];
9571  	u8         phase_grade_weight[0x8];
9572  
9573  	u8         gisim_measure_bits[0x10];
9574  	u8         adaptive_tap_measure_bits[0x10];
9575  
9576  	u8         ber_bath_high_error_threshold[0x10];
9577  	u8         ber_bath_mid_error_threshold[0x10];
9578  
9579  	u8         ber_bath_low_error_threshold[0x10];
9580  	u8         one_ratio_high_threshold[0x10];
9581  
9582  	u8         one_ratio_high_mid_threshold[0x10];
9583  	u8         one_ratio_low_mid_threshold[0x10];
9584  
9585  	u8         one_ratio_low_threshold[0x10];
9586  	u8         ndeo_error_threshold[0x10];
9587  
9588  	u8         mixer_offset_step_size[0x10];
9589  	u8         reserved_at_110[0x8];
9590  	u8         mix90_phase_for_voltage_bath[0x8];
9591  
9592  	u8         mixer_offset_start[0x10];
9593  	u8         mixer_offset_end[0x10];
9594  
9595  	u8         reserved_at_140[0x15];
9596  	u8         ber_test_time[0xb];
9597  };
9598  
9599  struct mlx5_ifc_pspa_reg_bits {
9600  	u8         swid[0x8];
9601  	u8         local_port[0x8];
9602  	u8         sub_port[0x8];
9603  	u8         reserved_at_18[0x8];
9604  
9605  	u8         reserved_at_20[0x20];
9606  };
9607  
9608  struct mlx5_ifc_pqdr_reg_bits {
9609  	u8         reserved_at_0[0x8];
9610  	u8         local_port[0x8];
9611  	u8         reserved_at_10[0x5];
9612  	u8         prio[0x3];
9613  	u8         reserved_at_18[0x6];
9614  	u8         mode[0x2];
9615  
9616  	u8         reserved_at_20[0x20];
9617  
9618  	u8         reserved_at_40[0x10];
9619  	u8         min_threshold[0x10];
9620  
9621  	u8         reserved_at_60[0x10];
9622  	u8         max_threshold[0x10];
9623  
9624  	u8         reserved_at_80[0x10];
9625  	u8         mark_probability_denominator[0x10];
9626  
9627  	u8         reserved_at_a0[0x60];
9628  };
9629  
9630  struct mlx5_ifc_ppsc_reg_bits {
9631  	u8         reserved_at_0[0x8];
9632  	u8         local_port[0x8];
9633  	u8         reserved_at_10[0x10];
9634  
9635  	u8         reserved_at_20[0x60];
9636  
9637  	u8         reserved_at_80[0x1c];
9638  	u8         wrps_admin[0x4];
9639  
9640  	u8         reserved_at_a0[0x1c];
9641  	u8         wrps_status[0x4];
9642  
9643  	u8         reserved_at_c0[0x8];
9644  	u8         up_threshold[0x8];
9645  	u8         reserved_at_d0[0x8];
9646  	u8         down_threshold[0x8];
9647  
9648  	u8         reserved_at_e0[0x20];
9649  
9650  	u8         reserved_at_100[0x1c];
9651  	u8         srps_admin[0x4];
9652  
9653  	u8         reserved_at_120[0x1c];
9654  	u8         srps_status[0x4];
9655  
9656  	u8         reserved_at_140[0x40];
9657  };
9658  
9659  struct mlx5_ifc_pplr_reg_bits {
9660  	u8         reserved_at_0[0x8];
9661  	u8         local_port[0x8];
9662  	u8         reserved_at_10[0x10];
9663  
9664  	u8         reserved_at_20[0x8];
9665  	u8         lb_cap[0x8];
9666  	u8         reserved_at_30[0x8];
9667  	u8         lb_en[0x8];
9668  };
9669  
9670  struct mlx5_ifc_pplm_reg_bits {
9671  	u8         reserved_at_0[0x8];
9672  	u8	   local_port[0x8];
9673  	u8	   reserved_at_10[0x10];
9674  
9675  	u8	   reserved_at_20[0x20];
9676  
9677  	u8	   port_profile_mode[0x8];
9678  	u8	   static_port_profile[0x8];
9679  	u8	   active_port_profile[0x8];
9680  	u8	   reserved_at_58[0x8];
9681  
9682  	u8	   retransmission_active[0x8];
9683  	u8	   fec_mode_active[0x18];
9684  
9685  	u8	   rs_fec_correction_bypass_cap[0x4];
9686  	u8	   reserved_at_84[0x8];
9687  	u8	   fec_override_cap_56g[0x4];
9688  	u8	   fec_override_cap_100g[0x4];
9689  	u8	   fec_override_cap_50g[0x4];
9690  	u8	   fec_override_cap_25g[0x4];
9691  	u8	   fec_override_cap_10g_40g[0x4];
9692  
9693  	u8	   rs_fec_correction_bypass_admin[0x4];
9694  	u8	   reserved_at_a4[0x8];
9695  	u8	   fec_override_admin_56g[0x4];
9696  	u8	   fec_override_admin_100g[0x4];
9697  	u8	   fec_override_admin_50g[0x4];
9698  	u8	   fec_override_admin_25g[0x4];
9699  	u8	   fec_override_admin_10g_40g[0x4];
9700  
9701  	u8         fec_override_cap_400g_8x[0x10];
9702  	u8         fec_override_cap_200g_4x[0x10];
9703  
9704  	u8         fec_override_cap_100g_2x[0x10];
9705  	u8         fec_override_cap_50g_1x[0x10];
9706  
9707  	u8         fec_override_admin_400g_8x[0x10];
9708  	u8         fec_override_admin_200g_4x[0x10];
9709  
9710  	u8         fec_override_admin_100g_2x[0x10];
9711  	u8         fec_override_admin_50g_1x[0x10];
9712  
9713  	u8         reserved_at_140[0x140];
9714  };
9715  
9716  struct mlx5_ifc_ppcnt_reg_bits {
9717  	u8         swid[0x8];
9718  	u8         local_port[0x8];
9719  	u8         pnat[0x2];
9720  	u8         reserved_at_12[0x8];
9721  	u8         grp[0x6];
9722  
9723  	u8         clr[0x1];
9724  	u8         reserved_at_21[0x1c];
9725  	u8         prio_tc[0x3];
9726  
9727  	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9728  };
9729  
9730  struct mlx5_ifc_mpein_reg_bits {
9731  	u8         reserved_at_0[0x2];
9732  	u8         depth[0x6];
9733  	u8         pcie_index[0x8];
9734  	u8         node[0x8];
9735  	u8         reserved_at_18[0x8];
9736  
9737  	u8         capability_mask[0x20];
9738  
9739  	u8         reserved_at_40[0x8];
9740  	u8         link_width_enabled[0x8];
9741  	u8         link_speed_enabled[0x10];
9742  
9743  	u8         lane0_physical_position[0x8];
9744  	u8         link_width_active[0x8];
9745  	u8         link_speed_active[0x10];
9746  
9747  	u8         num_of_pfs[0x10];
9748  	u8         num_of_vfs[0x10];
9749  
9750  	u8         bdf0[0x10];
9751  	u8         reserved_at_b0[0x10];
9752  
9753  	u8         max_read_request_size[0x4];
9754  	u8         max_payload_size[0x4];
9755  	u8         reserved_at_c8[0x5];
9756  	u8         pwr_status[0x3];
9757  	u8         port_type[0x4];
9758  	u8         reserved_at_d4[0xb];
9759  	u8         lane_reversal[0x1];
9760  
9761  	u8         reserved_at_e0[0x14];
9762  	u8         pci_power[0xc];
9763  
9764  	u8         reserved_at_100[0x20];
9765  
9766  	u8         device_status[0x10];
9767  	u8         port_state[0x8];
9768  	u8         reserved_at_138[0x8];
9769  
9770  	u8         reserved_at_140[0x10];
9771  	u8         receiver_detect_result[0x10];
9772  
9773  	u8         reserved_at_160[0x20];
9774  };
9775  
9776  struct mlx5_ifc_mpcnt_reg_bits {
9777  	u8         reserved_at_0[0x8];
9778  	u8         pcie_index[0x8];
9779  	u8         reserved_at_10[0xa];
9780  	u8         grp[0x6];
9781  
9782  	u8         clr[0x1];
9783  	u8         reserved_at_21[0x1f];
9784  
9785  	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9786  };
9787  
9788  struct mlx5_ifc_ppad_reg_bits {
9789  	u8         reserved_at_0[0x3];
9790  	u8         single_mac[0x1];
9791  	u8         reserved_at_4[0x4];
9792  	u8         local_port[0x8];
9793  	u8         mac_47_32[0x10];
9794  
9795  	u8         mac_31_0[0x20];
9796  
9797  	u8         reserved_at_40[0x40];
9798  };
9799  
9800  struct mlx5_ifc_pmtu_reg_bits {
9801  	u8         reserved_at_0[0x8];
9802  	u8         local_port[0x8];
9803  	u8         reserved_at_10[0x10];
9804  
9805  	u8         max_mtu[0x10];
9806  	u8         reserved_at_30[0x10];
9807  
9808  	u8         admin_mtu[0x10];
9809  	u8         reserved_at_50[0x10];
9810  
9811  	u8         oper_mtu[0x10];
9812  	u8         reserved_at_70[0x10];
9813  };
9814  
9815  struct mlx5_ifc_pmpr_reg_bits {
9816  	u8         reserved_at_0[0x8];
9817  	u8         module[0x8];
9818  	u8         reserved_at_10[0x10];
9819  
9820  	u8         reserved_at_20[0x18];
9821  	u8         attenuation_5g[0x8];
9822  
9823  	u8         reserved_at_40[0x18];
9824  	u8         attenuation_7g[0x8];
9825  
9826  	u8         reserved_at_60[0x18];
9827  	u8         attenuation_12g[0x8];
9828  };
9829  
9830  struct mlx5_ifc_pmpe_reg_bits {
9831  	u8         reserved_at_0[0x8];
9832  	u8         module[0x8];
9833  	u8         reserved_at_10[0xc];
9834  	u8         module_status[0x4];
9835  
9836  	u8         reserved_at_20[0x60];
9837  };
9838  
9839  struct mlx5_ifc_pmpc_reg_bits {
9840  	u8         module_state_updated[32][0x8];
9841  };
9842  
9843  struct mlx5_ifc_pmlpn_reg_bits {
9844  	u8         reserved_at_0[0x4];
9845  	u8         mlpn_status[0x4];
9846  	u8         local_port[0x8];
9847  	u8         reserved_at_10[0x10];
9848  
9849  	u8         e[0x1];
9850  	u8         reserved_at_21[0x1f];
9851  };
9852  
9853  struct mlx5_ifc_pmlp_reg_bits {
9854  	u8         rxtx[0x1];
9855  	u8         reserved_at_1[0x7];
9856  	u8         local_port[0x8];
9857  	u8         reserved_at_10[0x8];
9858  	u8         width[0x8];
9859  
9860  	u8         lane0_module_mapping[0x20];
9861  
9862  	u8         lane1_module_mapping[0x20];
9863  
9864  	u8         lane2_module_mapping[0x20];
9865  
9866  	u8         lane3_module_mapping[0x20];
9867  
9868  	u8         reserved_at_a0[0x160];
9869  };
9870  
9871  struct mlx5_ifc_pmaos_reg_bits {
9872  	u8         reserved_at_0[0x8];
9873  	u8         module[0x8];
9874  	u8         reserved_at_10[0x4];
9875  	u8         admin_status[0x4];
9876  	u8         reserved_at_18[0x4];
9877  	u8         oper_status[0x4];
9878  
9879  	u8         ase[0x1];
9880  	u8         ee[0x1];
9881  	u8         reserved_at_22[0x1c];
9882  	u8         e[0x2];
9883  
9884  	u8         reserved_at_40[0x40];
9885  };
9886  
9887  struct mlx5_ifc_plpc_reg_bits {
9888  	u8         reserved_at_0[0x4];
9889  	u8         profile_id[0xc];
9890  	u8         reserved_at_10[0x4];
9891  	u8         proto_mask[0x4];
9892  	u8         reserved_at_18[0x8];
9893  
9894  	u8         reserved_at_20[0x10];
9895  	u8         lane_speed[0x10];
9896  
9897  	u8         reserved_at_40[0x17];
9898  	u8         lpbf[0x1];
9899  	u8         fec_mode_policy[0x8];
9900  
9901  	u8         retransmission_capability[0x8];
9902  	u8         fec_mode_capability[0x18];
9903  
9904  	u8         retransmission_support_admin[0x8];
9905  	u8         fec_mode_support_admin[0x18];
9906  
9907  	u8         retransmission_request_admin[0x8];
9908  	u8         fec_mode_request_admin[0x18];
9909  
9910  	u8         reserved_at_c0[0x80];
9911  };
9912  
9913  struct mlx5_ifc_plib_reg_bits {
9914  	u8         reserved_at_0[0x8];
9915  	u8         local_port[0x8];
9916  	u8         reserved_at_10[0x8];
9917  	u8         ib_port[0x8];
9918  
9919  	u8         reserved_at_20[0x60];
9920  };
9921  
9922  struct mlx5_ifc_plbf_reg_bits {
9923  	u8         reserved_at_0[0x8];
9924  	u8         local_port[0x8];
9925  	u8         reserved_at_10[0xd];
9926  	u8         lbf_mode[0x3];
9927  
9928  	u8         reserved_at_20[0x20];
9929  };
9930  
9931  struct mlx5_ifc_pipg_reg_bits {
9932  	u8         reserved_at_0[0x8];
9933  	u8         local_port[0x8];
9934  	u8         reserved_at_10[0x10];
9935  
9936  	u8         dic[0x1];
9937  	u8         reserved_at_21[0x19];
9938  	u8         ipg[0x4];
9939  	u8         reserved_at_3e[0x2];
9940  };
9941  
9942  struct mlx5_ifc_pifr_reg_bits {
9943  	u8         reserved_at_0[0x8];
9944  	u8         local_port[0x8];
9945  	u8         reserved_at_10[0x10];
9946  
9947  	u8         reserved_at_20[0xe0];
9948  
9949  	u8         port_filter[8][0x20];
9950  
9951  	u8         port_filter_update_en[8][0x20];
9952  };
9953  
9954  struct mlx5_ifc_pfcc_reg_bits {
9955  	u8         reserved_at_0[0x8];
9956  	u8         local_port[0x8];
9957  	u8         reserved_at_10[0xb];
9958  	u8         ppan_mask_n[0x1];
9959  	u8         minor_stall_mask[0x1];
9960  	u8         critical_stall_mask[0x1];
9961  	u8         reserved_at_1e[0x2];
9962  
9963  	u8         ppan[0x4];
9964  	u8         reserved_at_24[0x4];
9965  	u8         prio_mask_tx[0x8];
9966  	u8         reserved_at_30[0x8];
9967  	u8         prio_mask_rx[0x8];
9968  
9969  	u8         pptx[0x1];
9970  	u8         aptx[0x1];
9971  	u8         pptx_mask_n[0x1];
9972  	u8         reserved_at_43[0x5];
9973  	u8         pfctx[0x8];
9974  	u8         reserved_at_50[0x10];
9975  
9976  	u8         pprx[0x1];
9977  	u8         aprx[0x1];
9978  	u8         pprx_mask_n[0x1];
9979  	u8         reserved_at_63[0x5];
9980  	u8         pfcrx[0x8];
9981  	u8         reserved_at_70[0x10];
9982  
9983  	u8         device_stall_minor_watermark[0x10];
9984  	u8         device_stall_critical_watermark[0x10];
9985  
9986  	u8         reserved_at_a0[0x60];
9987  };
9988  
9989  struct mlx5_ifc_pelc_reg_bits {
9990  	u8         op[0x4];
9991  	u8         reserved_at_4[0x4];
9992  	u8         local_port[0x8];
9993  	u8         reserved_at_10[0x10];
9994  
9995  	u8         op_admin[0x8];
9996  	u8         op_capability[0x8];
9997  	u8         op_request[0x8];
9998  	u8         op_active[0x8];
9999  
10000  	u8         admin[0x40];
10001  
10002  	u8         capability[0x40];
10003  
10004  	u8         request[0x40];
10005  
10006  	u8         active[0x40];
10007  
10008  	u8         reserved_at_140[0x80];
10009  };
10010  
10011  struct mlx5_ifc_peir_reg_bits {
10012  	u8         reserved_at_0[0x8];
10013  	u8         local_port[0x8];
10014  	u8         reserved_at_10[0x10];
10015  
10016  	u8         reserved_at_20[0xc];
10017  	u8         error_count[0x4];
10018  	u8         reserved_at_30[0x10];
10019  
10020  	u8         reserved_at_40[0xc];
10021  	u8         lane[0x4];
10022  	u8         reserved_at_50[0x8];
10023  	u8         error_type[0x8];
10024  };
10025  
10026  struct mlx5_ifc_mpegc_reg_bits {
10027  	u8         reserved_at_0[0x30];
10028  	u8         field_select[0x10];
10029  
10030  	u8         tx_overflow_sense[0x1];
10031  	u8         mark_cqe[0x1];
10032  	u8         mark_cnp[0x1];
10033  	u8         reserved_at_43[0x1b];
10034  	u8         tx_lossy_overflow_oper[0x2];
10035  
10036  	u8         reserved_at_60[0x100];
10037  };
10038  
10039  enum {
10040  	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10041  	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10042  };
10043  
10044  enum {
10045  	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10046  	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10047  	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10048  };
10049  
10050  struct mlx5_ifc_mtutc_reg_bits {
10051  	u8         reserved_at_0[0x5];
10052  	u8         freq_adj_units[0x3];
10053  	u8         reserved_at_8[0x14];
10054  	u8         operation[0x4];
10055  
10056  	u8         freq_adjustment[0x20];
10057  
10058  	u8         reserved_at_40[0x40];
10059  
10060  	u8         utc_sec[0x20];
10061  
10062  	u8         reserved_at_a0[0x2];
10063  	u8         utc_nsec[0x1e];
10064  
10065  	u8         time_adjustment[0x20];
10066  };
10067  
10068  struct mlx5_ifc_pcam_enhanced_features_bits {
10069  	u8         reserved_at_0[0x68];
10070  	u8         fec_50G_per_lane_in_pplm[0x1];
10071  	u8         reserved_at_69[0x4];
10072  	u8         rx_icrc_encapsulated_counter[0x1];
10073  	u8	   reserved_at_6e[0x4];
10074  	u8         ptys_extended_ethernet[0x1];
10075  	u8	   reserved_at_73[0x3];
10076  	u8         pfcc_mask[0x1];
10077  	u8         reserved_at_77[0x3];
10078  	u8         per_lane_error_counters[0x1];
10079  	u8         rx_buffer_fullness_counters[0x1];
10080  	u8         ptys_connector_type[0x1];
10081  	u8         reserved_at_7d[0x1];
10082  	u8         ppcnt_discard_group[0x1];
10083  	u8         ppcnt_statistical_group[0x1];
10084  };
10085  
10086  struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10087  	u8         port_access_reg_cap_mask_127_to_96[0x20];
10088  	u8         port_access_reg_cap_mask_95_to_64[0x20];
10089  
10090  	u8         port_access_reg_cap_mask_63_to_36[0x1c];
10091  	u8         pplm[0x1];
10092  	u8         port_access_reg_cap_mask_34_to_32[0x3];
10093  
10094  	u8         port_access_reg_cap_mask_31_to_13[0x13];
10095  	u8         pbmc[0x1];
10096  	u8         pptb[0x1];
10097  	u8         port_access_reg_cap_mask_10_to_09[0x2];
10098  	u8         ppcnt[0x1];
10099  	u8         port_access_reg_cap_mask_07_to_00[0x8];
10100  };
10101  
10102  struct mlx5_ifc_pcam_reg_bits {
10103  	u8         reserved_at_0[0x8];
10104  	u8         feature_group[0x8];
10105  	u8         reserved_at_10[0x8];
10106  	u8         access_reg_group[0x8];
10107  
10108  	u8         reserved_at_20[0x20];
10109  
10110  	union {
10111  		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10112  		u8         reserved_at_0[0x80];
10113  	} port_access_reg_cap_mask;
10114  
10115  	u8         reserved_at_c0[0x80];
10116  
10117  	union {
10118  		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10119  		u8         reserved_at_0[0x80];
10120  	} feature_cap_mask;
10121  
10122  	u8         reserved_at_1c0[0xc0];
10123  };
10124  
10125  struct mlx5_ifc_mcam_enhanced_features_bits {
10126  	u8         reserved_at_0[0x50];
10127  	u8         mtutc_freq_adj_units[0x1];
10128  	u8         mtutc_time_adjustment_extended_range[0x1];
10129  	u8         reserved_at_52[0xb];
10130  	u8         mcia_32dwords[0x1];
10131  	u8         out_pulse_duration_ns[0x1];
10132  	u8         npps_period[0x1];
10133  	u8         reserved_at_60[0xa];
10134  	u8         reset_state[0x1];
10135  	u8         ptpcyc2realtime_modify[0x1];
10136  	u8         reserved_at_6c[0x2];
10137  	u8         pci_status_and_power[0x1];
10138  	u8         reserved_at_6f[0x5];
10139  	u8         mark_tx_action_cnp[0x1];
10140  	u8         mark_tx_action_cqe[0x1];
10141  	u8         dynamic_tx_overflow[0x1];
10142  	u8         reserved_at_77[0x4];
10143  	u8         pcie_outbound_stalled[0x1];
10144  	u8         tx_overflow_buffer_pkt[0x1];
10145  	u8         mtpps_enh_out_per_adj[0x1];
10146  	u8         mtpps_fs[0x1];
10147  	u8         pcie_performance_group[0x1];
10148  };
10149  
10150  struct mlx5_ifc_mcam_access_reg_bits {
10151  	u8         reserved_at_0[0x1c];
10152  	u8         mcda[0x1];
10153  	u8         mcc[0x1];
10154  	u8         mcqi[0x1];
10155  	u8         mcqs[0x1];
10156  
10157  	u8         regs_95_to_87[0x9];
10158  	u8         mpegc[0x1];
10159  	u8         mtutc[0x1];
10160  	u8         regs_84_to_68[0x11];
10161  	u8         tracer_registers[0x4];
10162  
10163  	u8         regs_63_to_46[0x12];
10164  	u8         mrtc[0x1];
10165  	u8         regs_44_to_41[0x4];
10166  	u8         mfrl[0x1];
10167  	u8         regs_39_to_32[0x8];
10168  
10169  	u8         regs_31_to_11[0x15];
10170  	u8         mtmp[0x1];
10171  	u8         regs_9_to_0[0xa];
10172  };
10173  
10174  struct mlx5_ifc_mcam_access_reg_bits1 {
10175  	u8         regs_127_to_96[0x20];
10176  
10177  	u8         regs_95_to_64[0x20];
10178  
10179  	u8         regs_63_to_32[0x20];
10180  
10181  	u8         regs_31_to_0[0x20];
10182  };
10183  
10184  struct mlx5_ifc_mcam_access_reg_bits2 {
10185  	u8         regs_127_to_99[0x1d];
10186  	u8         mirc[0x1];
10187  	u8         regs_97_to_96[0x2];
10188  
10189  	u8         regs_95_to_64[0x20];
10190  
10191  	u8         regs_63_to_32[0x20];
10192  
10193  	u8         regs_31_to_0[0x20];
10194  };
10195  
10196  struct mlx5_ifc_mcam_reg_bits {
10197  	u8         reserved_at_0[0x8];
10198  	u8         feature_group[0x8];
10199  	u8         reserved_at_10[0x8];
10200  	u8         access_reg_group[0x8];
10201  
10202  	u8         reserved_at_20[0x20];
10203  
10204  	union {
10205  		struct mlx5_ifc_mcam_access_reg_bits access_regs;
10206  		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10207  		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10208  		u8         reserved_at_0[0x80];
10209  	} mng_access_reg_cap_mask;
10210  
10211  	u8         reserved_at_c0[0x80];
10212  
10213  	union {
10214  		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10215  		u8         reserved_at_0[0x80];
10216  	} mng_feature_cap_mask;
10217  
10218  	u8         reserved_at_1c0[0x80];
10219  };
10220  
10221  struct mlx5_ifc_qcam_access_reg_cap_mask {
10222  	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10223  	u8         qpdpm[0x1];
10224  	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10225  	u8         qdpm[0x1];
10226  	u8         qpts[0x1];
10227  	u8         qcap[0x1];
10228  	u8         qcam_access_reg_cap_mask_0[0x1];
10229  };
10230  
10231  struct mlx5_ifc_qcam_qos_feature_cap_mask {
10232  	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10233  	u8         qpts_trust_both[0x1];
10234  };
10235  
10236  struct mlx5_ifc_qcam_reg_bits {
10237  	u8         reserved_at_0[0x8];
10238  	u8         feature_group[0x8];
10239  	u8         reserved_at_10[0x8];
10240  	u8         access_reg_group[0x8];
10241  	u8         reserved_at_20[0x20];
10242  
10243  	union {
10244  		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10245  		u8  reserved_at_0[0x80];
10246  	} qos_access_reg_cap_mask;
10247  
10248  	u8         reserved_at_c0[0x80];
10249  
10250  	union {
10251  		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10252  		u8  reserved_at_0[0x80];
10253  	} qos_feature_cap_mask;
10254  
10255  	u8         reserved_at_1c0[0x80];
10256  };
10257  
10258  struct mlx5_ifc_core_dump_reg_bits {
10259  	u8         reserved_at_0[0x18];
10260  	u8         core_dump_type[0x8];
10261  
10262  	u8         reserved_at_20[0x30];
10263  	u8         vhca_id[0x10];
10264  
10265  	u8         reserved_at_60[0x8];
10266  	u8         qpn[0x18];
10267  	u8         reserved_at_80[0x180];
10268  };
10269  
10270  struct mlx5_ifc_pcap_reg_bits {
10271  	u8         reserved_at_0[0x8];
10272  	u8         local_port[0x8];
10273  	u8         reserved_at_10[0x10];
10274  
10275  	u8         port_capability_mask[4][0x20];
10276  };
10277  
10278  struct mlx5_ifc_paos_reg_bits {
10279  	u8         swid[0x8];
10280  	u8         local_port[0x8];
10281  	u8         reserved_at_10[0x4];
10282  	u8         admin_status[0x4];
10283  	u8         reserved_at_18[0x4];
10284  	u8         oper_status[0x4];
10285  
10286  	u8         ase[0x1];
10287  	u8         ee[0x1];
10288  	u8         reserved_at_22[0x1c];
10289  	u8         e[0x2];
10290  
10291  	u8         reserved_at_40[0x40];
10292  };
10293  
10294  struct mlx5_ifc_pamp_reg_bits {
10295  	u8         reserved_at_0[0x8];
10296  	u8         opamp_group[0x8];
10297  	u8         reserved_at_10[0xc];
10298  	u8         opamp_group_type[0x4];
10299  
10300  	u8         start_index[0x10];
10301  	u8         reserved_at_30[0x4];
10302  	u8         num_of_indices[0xc];
10303  
10304  	u8         index_data[18][0x10];
10305  };
10306  
10307  struct mlx5_ifc_pcmr_reg_bits {
10308  	u8         reserved_at_0[0x8];
10309  	u8         local_port[0x8];
10310  	u8         reserved_at_10[0x10];
10311  
10312  	u8         entropy_force_cap[0x1];
10313  	u8         entropy_calc_cap[0x1];
10314  	u8         entropy_gre_calc_cap[0x1];
10315  	u8         reserved_at_23[0xf];
10316  	u8         rx_ts_over_crc_cap[0x1];
10317  	u8         reserved_at_33[0xb];
10318  	u8         fcs_cap[0x1];
10319  	u8         reserved_at_3f[0x1];
10320  
10321  	u8         entropy_force[0x1];
10322  	u8         entropy_calc[0x1];
10323  	u8         entropy_gre_calc[0x1];
10324  	u8         reserved_at_43[0xf];
10325  	u8         rx_ts_over_crc[0x1];
10326  	u8         reserved_at_53[0xb];
10327  	u8         fcs_chk[0x1];
10328  	u8         reserved_at_5f[0x1];
10329  };
10330  
10331  struct mlx5_ifc_lane_2_module_mapping_bits {
10332  	u8         reserved_at_0[0x4];
10333  	u8         rx_lane[0x4];
10334  	u8         reserved_at_8[0x4];
10335  	u8         tx_lane[0x4];
10336  	u8         reserved_at_10[0x8];
10337  	u8         module[0x8];
10338  };
10339  
10340  struct mlx5_ifc_bufferx_reg_bits {
10341  	u8         reserved_at_0[0x6];
10342  	u8         lossy[0x1];
10343  	u8         epsb[0x1];
10344  	u8         reserved_at_8[0x8];
10345  	u8         size[0x10];
10346  
10347  	u8         xoff_threshold[0x10];
10348  	u8         xon_threshold[0x10];
10349  };
10350  
10351  struct mlx5_ifc_set_node_in_bits {
10352  	u8         node_description[64][0x8];
10353  };
10354  
10355  struct mlx5_ifc_register_power_settings_bits {
10356  	u8         reserved_at_0[0x18];
10357  	u8         power_settings_level[0x8];
10358  
10359  	u8         reserved_at_20[0x60];
10360  };
10361  
10362  struct mlx5_ifc_register_host_endianness_bits {
10363  	u8         he[0x1];
10364  	u8         reserved_at_1[0x1f];
10365  
10366  	u8         reserved_at_20[0x60];
10367  };
10368  
10369  struct mlx5_ifc_umr_pointer_desc_argument_bits {
10370  	u8         reserved_at_0[0x20];
10371  
10372  	u8         mkey[0x20];
10373  
10374  	u8         addressh_63_32[0x20];
10375  
10376  	u8         addressl_31_0[0x20];
10377  };
10378  
10379  struct mlx5_ifc_ud_adrs_vector_bits {
10380  	u8         dc_key[0x40];
10381  
10382  	u8         ext[0x1];
10383  	u8         reserved_at_41[0x7];
10384  	u8         destination_qp_dct[0x18];
10385  
10386  	u8         static_rate[0x4];
10387  	u8         sl_eth_prio[0x4];
10388  	u8         fl[0x1];
10389  	u8         mlid[0x7];
10390  	u8         rlid_udp_sport[0x10];
10391  
10392  	u8         reserved_at_80[0x20];
10393  
10394  	u8         rmac_47_16[0x20];
10395  
10396  	u8         rmac_15_0[0x10];
10397  	u8         tclass[0x8];
10398  	u8         hop_limit[0x8];
10399  
10400  	u8         reserved_at_e0[0x1];
10401  	u8         grh[0x1];
10402  	u8         reserved_at_e2[0x2];
10403  	u8         src_addr_index[0x8];
10404  	u8         flow_label[0x14];
10405  
10406  	u8         rgid_rip[16][0x8];
10407  };
10408  
10409  struct mlx5_ifc_pages_req_event_bits {
10410  	u8         reserved_at_0[0x10];
10411  	u8         function_id[0x10];
10412  
10413  	u8         num_pages[0x20];
10414  
10415  	u8         reserved_at_40[0xa0];
10416  };
10417  
10418  struct mlx5_ifc_eqe_bits {
10419  	u8         reserved_at_0[0x8];
10420  	u8         event_type[0x8];
10421  	u8         reserved_at_10[0x8];
10422  	u8         event_sub_type[0x8];
10423  
10424  	u8         reserved_at_20[0xe0];
10425  
10426  	union mlx5_ifc_event_auto_bits event_data;
10427  
10428  	u8         reserved_at_1e0[0x10];
10429  	u8         signature[0x8];
10430  	u8         reserved_at_1f8[0x7];
10431  	u8         owner[0x1];
10432  };
10433  
10434  enum {
10435  	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10436  };
10437  
10438  struct mlx5_ifc_cmd_queue_entry_bits {
10439  	u8         type[0x8];
10440  	u8         reserved_at_8[0x18];
10441  
10442  	u8         input_length[0x20];
10443  
10444  	u8         input_mailbox_pointer_63_32[0x20];
10445  
10446  	u8         input_mailbox_pointer_31_9[0x17];
10447  	u8         reserved_at_77[0x9];
10448  
10449  	u8         command_input_inline_data[16][0x8];
10450  
10451  	u8         command_output_inline_data[16][0x8];
10452  
10453  	u8         output_mailbox_pointer_63_32[0x20];
10454  
10455  	u8         output_mailbox_pointer_31_9[0x17];
10456  	u8         reserved_at_1b7[0x9];
10457  
10458  	u8         output_length[0x20];
10459  
10460  	u8         token[0x8];
10461  	u8         signature[0x8];
10462  	u8         reserved_at_1f0[0x8];
10463  	u8         status[0x7];
10464  	u8         ownership[0x1];
10465  };
10466  
10467  struct mlx5_ifc_cmd_out_bits {
10468  	u8         status[0x8];
10469  	u8         reserved_at_8[0x18];
10470  
10471  	u8         syndrome[0x20];
10472  
10473  	u8         command_output[0x20];
10474  };
10475  
10476  struct mlx5_ifc_cmd_in_bits {
10477  	u8         opcode[0x10];
10478  	u8         reserved_at_10[0x10];
10479  
10480  	u8         reserved_at_20[0x10];
10481  	u8         op_mod[0x10];
10482  
10483  	u8         command[][0x20];
10484  };
10485  
10486  struct mlx5_ifc_cmd_if_box_bits {
10487  	u8         mailbox_data[512][0x8];
10488  
10489  	u8         reserved_at_1000[0x180];
10490  
10491  	u8         next_pointer_63_32[0x20];
10492  
10493  	u8         next_pointer_31_10[0x16];
10494  	u8         reserved_at_11b6[0xa];
10495  
10496  	u8         block_number[0x20];
10497  
10498  	u8         reserved_at_11e0[0x8];
10499  	u8         token[0x8];
10500  	u8         ctrl_signature[0x8];
10501  	u8         signature[0x8];
10502  };
10503  
10504  struct mlx5_ifc_mtt_bits {
10505  	u8         ptag_63_32[0x20];
10506  
10507  	u8         ptag_31_8[0x18];
10508  	u8         reserved_at_38[0x6];
10509  	u8         wr_en[0x1];
10510  	u8         rd_en[0x1];
10511  };
10512  
10513  struct mlx5_ifc_query_wol_rol_out_bits {
10514  	u8         status[0x8];
10515  	u8         reserved_at_8[0x18];
10516  
10517  	u8         syndrome[0x20];
10518  
10519  	u8         reserved_at_40[0x10];
10520  	u8         rol_mode[0x8];
10521  	u8         wol_mode[0x8];
10522  
10523  	u8         reserved_at_60[0x20];
10524  };
10525  
10526  struct mlx5_ifc_query_wol_rol_in_bits {
10527  	u8         opcode[0x10];
10528  	u8         reserved_at_10[0x10];
10529  
10530  	u8         reserved_at_20[0x10];
10531  	u8         op_mod[0x10];
10532  
10533  	u8         reserved_at_40[0x40];
10534  };
10535  
10536  struct mlx5_ifc_set_wol_rol_out_bits {
10537  	u8         status[0x8];
10538  	u8         reserved_at_8[0x18];
10539  
10540  	u8         syndrome[0x20];
10541  
10542  	u8         reserved_at_40[0x40];
10543  };
10544  
10545  struct mlx5_ifc_set_wol_rol_in_bits {
10546  	u8         opcode[0x10];
10547  	u8         reserved_at_10[0x10];
10548  
10549  	u8         reserved_at_20[0x10];
10550  	u8         op_mod[0x10];
10551  
10552  	u8         rol_mode_valid[0x1];
10553  	u8         wol_mode_valid[0x1];
10554  	u8         reserved_at_42[0xe];
10555  	u8         rol_mode[0x8];
10556  	u8         wol_mode[0x8];
10557  
10558  	u8         reserved_at_60[0x20];
10559  };
10560  
10561  enum {
10562  	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10563  	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10564  	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10565  };
10566  
10567  enum {
10568  	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10569  	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10570  	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10571  };
10572  
10573  enum {
10574  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
10575  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
10576  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
10577  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
10578  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
10579  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
10580  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
10581  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
10582  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
10583  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
10584  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
10585  };
10586  
10587  struct mlx5_ifc_initial_seg_bits {
10588  	u8         fw_rev_minor[0x10];
10589  	u8         fw_rev_major[0x10];
10590  
10591  	u8         cmd_interface_rev[0x10];
10592  	u8         fw_rev_subminor[0x10];
10593  
10594  	u8         reserved_at_40[0x40];
10595  
10596  	u8         cmdq_phy_addr_63_32[0x20];
10597  
10598  	u8         cmdq_phy_addr_31_12[0x14];
10599  	u8         reserved_at_b4[0x2];
10600  	u8         nic_interface[0x2];
10601  	u8         log_cmdq_size[0x4];
10602  	u8         log_cmdq_stride[0x4];
10603  
10604  	u8         command_doorbell_vector[0x20];
10605  
10606  	u8         reserved_at_e0[0xf00];
10607  
10608  	u8         initializing[0x1];
10609  	u8         reserved_at_fe1[0x4];
10610  	u8         nic_interface_supported[0x3];
10611  	u8         embedded_cpu[0x1];
10612  	u8         reserved_at_fe9[0x17];
10613  
10614  	struct mlx5_ifc_health_buffer_bits health_buffer;
10615  
10616  	u8         no_dram_nic_offset[0x20];
10617  
10618  	u8         reserved_at_1220[0x6e40];
10619  
10620  	u8         reserved_at_8060[0x1f];
10621  	u8         clear_int[0x1];
10622  
10623  	u8         health_syndrome[0x8];
10624  	u8         health_counter[0x18];
10625  
10626  	u8         reserved_at_80a0[0x17fc0];
10627  };
10628  
10629  struct mlx5_ifc_mtpps_reg_bits {
10630  	u8         reserved_at_0[0xc];
10631  	u8         cap_number_of_pps_pins[0x4];
10632  	u8         reserved_at_10[0x4];
10633  	u8         cap_max_num_of_pps_in_pins[0x4];
10634  	u8         reserved_at_18[0x4];
10635  	u8         cap_max_num_of_pps_out_pins[0x4];
10636  
10637  	u8         reserved_at_20[0x13];
10638  	u8         cap_log_min_npps_period[0x5];
10639  	u8         reserved_at_38[0x3];
10640  	u8         cap_log_min_out_pulse_duration_ns[0x5];
10641  
10642  	u8         reserved_at_40[0x4];
10643  	u8         cap_pin_3_mode[0x4];
10644  	u8         reserved_at_48[0x4];
10645  	u8         cap_pin_2_mode[0x4];
10646  	u8         reserved_at_50[0x4];
10647  	u8         cap_pin_1_mode[0x4];
10648  	u8         reserved_at_58[0x4];
10649  	u8         cap_pin_0_mode[0x4];
10650  
10651  	u8         reserved_at_60[0x4];
10652  	u8         cap_pin_7_mode[0x4];
10653  	u8         reserved_at_68[0x4];
10654  	u8         cap_pin_6_mode[0x4];
10655  	u8         reserved_at_70[0x4];
10656  	u8         cap_pin_5_mode[0x4];
10657  	u8         reserved_at_78[0x4];
10658  	u8         cap_pin_4_mode[0x4];
10659  
10660  	u8         field_select[0x20];
10661  	u8         reserved_at_a0[0x20];
10662  
10663  	u8         npps_period[0x40];
10664  
10665  	u8         enable[0x1];
10666  	u8         reserved_at_101[0xb];
10667  	u8         pattern[0x4];
10668  	u8         reserved_at_110[0x4];
10669  	u8         pin_mode[0x4];
10670  	u8         pin[0x8];
10671  
10672  	u8         reserved_at_120[0x2];
10673  	u8         out_pulse_duration_ns[0x1e];
10674  
10675  	u8         time_stamp[0x40];
10676  
10677  	u8         out_pulse_duration[0x10];
10678  	u8         out_periodic_adjustment[0x10];
10679  	u8         enhanced_out_periodic_adjustment[0x20];
10680  
10681  	u8         reserved_at_1c0[0x20];
10682  };
10683  
10684  struct mlx5_ifc_mtppse_reg_bits {
10685  	u8         reserved_at_0[0x18];
10686  	u8         pin[0x8];
10687  	u8         event_arm[0x1];
10688  	u8         reserved_at_21[0x1b];
10689  	u8         event_generation_mode[0x4];
10690  	u8         reserved_at_40[0x40];
10691  };
10692  
10693  struct mlx5_ifc_mcqs_reg_bits {
10694  	u8         last_index_flag[0x1];
10695  	u8         reserved_at_1[0x7];
10696  	u8         fw_device[0x8];
10697  	u8         component_index[0x10];
10698  
10699  	u8         reserved_at_20[0x10];
10700  	u8         identifier[0x10];
10701  
10702  	u8         reserved_at_40[0x17];
10703  	u8         component_status[0x5];
10704  	u8         component_update_state[0x4];
10705  
10706  	u8         last_update_state_changer_type[0x4];
10707  	u8         last_update_state_changer_host_id[0x4];
10708  	u8         reserved_at_68[0x18];
10709  };
10710  
10711  struct mlx5_ifc_mcqi_cap_bits {
10712  	u8         supported_info_bitmask[0x20];
10713  
10714  	u8         component_size[0x20];
10715  
10716  	u8         max_component_size[0x20];
10717  
10718  	u8         log_mcda_word_size[0x4];
10719  	u8         reserved_at_64[0xc];
10720  	u8         mcda_max_write_size[0x10];
10721  
10722  	u8         rd_en[0x1];
10723  	u8         reserved_at_81[0x1];
10724  	u8         match_chip_id[0x1];
10725  	u8         match_psid[0x1];
10726  	u8         check_user_timestamp[0x1];
10727  	u8         match_base_guid_mac[0x1];
10728  	u8         reserved_at_86[0x1a];
10729  };
10730  
10731  struct mlx5_ifc_mcqi_version_bits {
10732  	u8         reserved_at_0[0x2];
10733  	u8         build_time_valid[0x1];
10734  	u8         user_defined_time_valid[0x1];
10735  	u8         reserved_at_4[0x14];
10736  	u8         version_string_length[0x8];
10737  
10738  	u8         version[0x20];
10739  
10740  	u8         build_time[0x40];
10741  
10742  	u8         user_defined_time[0x40];
10743  
10744  	u8         build_tool_version[0x20];
10745  
10746  	u8         reserved_at_e0[0x20];
10747  
10748  	u8         version_string[92][0x8];
10749  };
10750  
10751  struct mlx5_ifc_mcqi_activation_method_bits {
10752  	u8         pending_server_ac_power_cycle[0x1];
10753  	u8         pending_server_dc_power_cycle[0x1];
10754  	u8         pending_server_reboot[0x1];
10755  	u8         pending_fw_reset[0x1];
10756  	u8         auto_activate[0x1];
10757  	u8         all_hosts_sync[0x1];
10758  	u8         device_hw_reset[0x1];
10759  	u8         reserved_at_7[0x19];
10760  };
10761  
10762  union mlx5_ifc_mcqi_reg_data_bits {
10763  	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
10764  	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
10765  	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10766  };
10767  
10768  struct mlx5_ifc_mcqi_reg_bits {
10769  	u8         read_pending_component[0x1];
10770  	u8         reserved_at_1[0xf];
10771  	u8         component_index[0x10];
10772  
10773  	u8         reserved_at_20[0x20];
10774  
10775  	u8         reserved_at_40[0x1b];
10776  	u8         info_type[0x5];
10777  
10778  	u8         info_size[0x20];
10779  
10780  	u8         offset[0x20];
10781  
10782  	u8         reserved_at_a0[0x10];
10783  	u8         data_size[0x10];
10784  
10785  	union mlx5_ifc_mcqi_reg_data_bits data[];
10786  };
10787  
10788  struct mlx5_ifc_mcc_reg_bits {
10789  	u8         reserved_at_0[0x4];
10790  	u8         time_elapsed_since_last_cmd[0xc];
10791  	u8         reserved_at_10[0x8];
10792  	u8         instruction[0x8];
10793  
10794  	u8         reserved_at_20[0x10];
10795  	u8         component_index[0x10];
10796  
10797  	u8         reserved_at_40[0x8];
10798  	u8         update_handle[0x18];
10799  
10800  	u8         handle_owner_type[0x4];
10801  	u8         handle_owner_host_id[0x4];
10802  	u8         reserved_at_68[0x1];
10803  	u8         control_progress[0x7];
10804  	u8         error_code[0x8];
10805  	u8         reserved_at_78[0x4];
10806  	u8         control_state[0x4];
10807  
10808  	u8         component_size[0x20];
10809  
10810  	u8         reserved_at_a0[0x60];
10811  };
10812  
10813  struct mlx5_ifc_mcda_reg_bits {
10814  	u8         reserved_at_0[0x8];
10815  	u8         update_handle[0x18];
10816  
10817  	u8         offset[0x20];
10818  
10819  	u8         reserved_at_40[0x10];
10820  	u8         size[0x10];
10821  
10822  	u8         reserved_at_60[0x20];
10823  
10824  	u8         data[][0x20];
10825  };
10826  
10827  enum {
10828  	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10829  	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10830  	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10831  	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
10832  	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10833  	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
10834  };
10835  
10836  enum {
10837  	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10838  	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10839  };
10840  
10841  enum {
10842  	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10843  	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10844  	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10845  };
10846  
10847  struct mlx5_ifc_mfrl_reg_bits {
10848  	u8         reserved_at_0[0x20];
10849  
10850  	u8         reserved_at_20[0x2];
10851  	u8         pci_sync_for_fw_update_start[0x1];
10852  	u8         pci_sync_for_fw_update_resp[0x2];
10853  	u8         rst_type_sel[0x3];
10854  	u8         reserved_at_28[0x4];
10855  	u8         reset_state[0x4];
10856  	u8         reset_type[0x8];
10857  	u8         reset_level[0x8];
10858  };
10859  
10860  struct mlx5_ifc_mirc_reg_bits {
10861  	u8         reserved_at_0[0x18];
10862  	u8         status_code[0x8];
10863  
10864  	u8         reserved_at_20[0x20];
10865  };
10866  
10867  struct mlx5_ifc_pddr_monitor_opcode_bits {
10868  	u8         reserved_at_0[0x10];
10869  	u8         monitor_opcode[0x10];
10870  };
10871  
10872  union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10873  	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10874  	u8         reserved_at_0[0x20];
10875  };
10876  
10877  enum {
10878  	/* Monitor opcodes */
10879  	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10880  };
10881  
10882  struct mlx5_ifc_pddr_troubleshooting_page_bits {
10883  	u8         reserved_at_0[0x10];
10884  	u8         group_opcode[0x10];
10885  
10886  	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10887  
10888  	u8         reserved_at_40[0x20];
10889  
10890  	u8         status_message[59][0x20];
10891  };
10892  
10893  union mlx5_ifc_pddr_reg_page_data_auto_bits {
10894  	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10895  	u8         reserved_at_0[0x7c0];
10896  };
10897  
10898  enum {
10899  	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10900  };
10901  
10902  struct mlx5_ifc_pddr_reg_bits {
10903  	u8         reserved_at_0[0x8];
10904  	u8         local_port[0x8];
10905  	u8         pnat[0x2];
10906  	u8         reserved_at_12[0xe];
10907  
10908  	u8         reserved_at_20[0x18];
10909  	u8         page_select[0x8];
10910  
10911  	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10912  };
10913  
10914  struct mlx5_ifc_mrtc_reg_bits {
10915  	u8         time_synced[0x1];
10916  	u8         reserved_at_1[0x1f];
10917  
10918  	u8         reserved_at_20[0x20];
10919  
10920  	u8         time_h[0x20];
10921  
10922  	u8         time_l[0x20];
10923  };
10924  
10925  struct mlx5_ifc_mtcap_reg_bits {
10926  	u8         reserved_at_0[0x19];
10927  	u8         sensor_count[0x7];
10928  
10929  	u8         reserved_at_20[0x20];
10930  
10931  	u8         sensor_map[0x40];
10932  };
10933  
10934  struct mlx5_ifc_mtmp_reg_bits {
10935  	u8         reserved_at_0[0x14];
10936  	u8         sensor_index[0xc];
10937  
10938  	u8         reserved_at_20[0x10];
10939  	u8         temperature[0x10];
10940  
10941  	u8         mte[0x1];
10942  	u8         mtr[0x1];
10943  	u8         reserved_at_42[0xe];
10944  	u8         max_temperature[0x10];
10945  
10946  	u8         tee[0x2];
10947  	u8         reserved_at_62[0xe];
10948  	u8         temp_threshold_hi[0x10];
10949  
10950  	u8         reserved_at_80[0x10];
10951  	u8         temp_threshold_lo[0x10];
10952  
10953  	u8         reserved_at_a0[0x20];
10954  
10955  	u8         sensor_name_hi[0x20];
10956  	u8         sensor_name_lo[0x20];
10957  };
10958  
10959  union mlx5_ifc_ports_control_registers_document_bits {
10960  	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10961  	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10962  	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10963  	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10964  	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10965  	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10966  	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10967  	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10968  	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10969  	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10970  	struct mlx5_ifc_pamp_reg_bits pamp_reg;
10971  	struct mlx5_ifc_paos_reg_bits paos_reg;
10972  	struct mlx5_ifc_pcap_reg_bits pcap_reg;
10973  	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10974  	struct mlx5_ifc_pddr_reg_bits pddr_reg;
10975  	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10976  	struct mlx5_ifc_peir_reg_bits peir_reg;
10977  	struct mlx5_ifc_pelc_reg_bits pelc_reg;
10978  	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10979  	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10980  	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10981  	struct mlx5_ifc_pifr_reg_bits pifr_reg;
10982  	struct mlx5_ifc_pipg_reg_bits pipg_reg;
10983  	struct mlx5_ifc_plbf_reg_bits plbf_reg;
10984  	struct mlx5_ifc_plib_reg_bits plib_reg;
10985  	struct mlx5_ifc_plpc_reg_bits plpc_reg;
10986  	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10987  	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10988  	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10989  	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10990  	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10991  	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10992  	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10993  	struct mlx5_ifc_ppad_reg_bits ppad_reg;
10994  	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10995  	struct mlx5_ifc_mpein_reg_bits mpein_reg;
10996  	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10997  	struct mlx5_ifc_pplm_reg_bits pplm_reg;
10998  	struct mlx5_ifc_pplr_reg_bits pplr_reg;
10999  	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11000  	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11001  	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11002  	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11003  	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11004  	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11005  	struct mlx5_ifc_pude_reg_bits pude_reg;
11006  	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11007  	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11008  	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11009  	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11010  	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11011  	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11012  	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11013  	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11014  	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11015  	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11016  	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11017  	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11018  	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11019  	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11020  	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11021  	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11022  	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11023  	u8         reserved_at_0[0x60e0];
11024  };
11025  
11026  union mlx5_ifc_debug_enhancements_document_bits {
11027  	struct mlx5_ifc_health_buffer_bits health_buffer;
11028  	u8         reserved_at_0[0x200];
11029  };
11030  
11031  union mlx5_ifc_uplink_pci_interface_document_bits {
11032  	struct mlx5_ifc_initial_seg_bits initial_seg;
11033  	u8         reserved_at_0[0x20060];
11034  };
11035  
11036  struct mlx5_ifc_set_flow_table_root_out_bits {
11037  	u8         status[0x8];
11038  	u8         reserved_at_8[0x18];
11039  
11040  	u8         syndrome[0x20];
11041  
11042  	u8         reserved_at_40[0x40];
11043  };
11044  
11045  struct mlx5_ifc_set_flow_table_root_in_bits {
11046  	u8         opcode[0x10];
11047  	u8         reserved_at_10[0x10];
11048  
11049  	u8         reserved_at_20[0x10];
11050  	u8         op_mod[0x10];
11051  
11052  	u8         other_vport[0x1];
11053  	u8         reserved_at_41[0xf];
11054  	u8         vport_number[0x10];
11055  
11056  	u8         reserved_at_60[0x20];
11057  
11058  	u8         table_type[0x8];
11059  	u8         reserved_at_88[0x7];
11060  	u8         table_of_other_vport[0x1];
11061  	u8         table_vport_number[0x10];
11062  
11063  	u8         reserved_at_a0[0x8];
11064  	u8         table_id[0x18];
11065  
11066  	u8         reserved_at_c0[0x8];
11067  	u8         underlay_qpn[0x18];
11068  	u8         table_eswitch_owner_vhca_id_valid[0x1];
11069  	u8         reserved_at_e1[0xf];
11070  	u8         table_eswitch_owner_vhca_id[0x10];
11071  	u8         reserved_at_100[0x100];
11072  };
11073  
11074  enum {
11075  	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11076  	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11077  };
11078  
11079  struct mlx5_ifc_modify_flow_table_out_bits {
11080  	u8         status[0x8];
11081  	u8         reserved_at_8[0x18];
11082  
11083  	u8         syndrome[0x20];
11084  
11085  	u8         reserved_at_40[0x40];
11086  };
11087  
11088  struct mlx5_ifc_modify_flow_table_in_bits {
11089  	u8         opcode[0x10];
11090  	u8         reserved_at_10[0x10];
11091  
11092  	u8         reserved_at_20[0x10];
11093  	u8         op_mod[0x10];
11094  
11095  	u8         other_vport[0x1];
11096  	u8         reserved_at_41[0xf];
11097  	u8         vport_number[0x10];
11098  
11099  	u8         reserved_at_60[0x10];
11100  	u8         modify_field_select[0x10];
11101  
11102  	u8         table_type[0x8];
11103  	u8         reserved_at_88[0x18];
11104  
11105  	u8         reserved_at_a0[0x8];
11106  	u8         table_id[0x18];
11107  
11108  	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11109  };
11110  
11111  struct mlx5_ifc_ets_tcn_config_reg_bits {
11112  	u8         g[0x1];
11113  	u8         b[0x1];
11114  	u8         r[0x1];
11115  	u8         reserved_at_3[0x9];
11116  	u8         group[0x4];
11117  	u8         reserved_at_10[0x9];
11118  	u8         bw_allocation[0x7];
11119  
11120  	u8         reserved_at_20[0xc];
11121  	u8         max_bw_units[0x4];
11122  	u8         reserved_at_30[0x8];
11123  	u8         max_bw_value[0x8];
11124  };
11125  
11126  struct mlx5_ifc_ets_global_config_reg_bits {
11127  	u8         reserved_at_0[0x2];
11128  	u8         r[0x1];
11129  	u8         reserved_at_3[0x1d];
11130  
11131  	u8         reserved_at_20[0xc];
11132  	u8         max_bw_units[0x4];
11133  	u8         reserved_at_30[0x8];
11134  	u8         max_bw_value[0x8];
11135  };
11136  
11137  struct mlx5_ifc_qetc_reg_bits {
11138  	u8                                         reserved_at_0[0x8];
11139  	u8                                         port_number[0x8];
11140  	u8                                         reserved_at_10[0x30];
11141  
11142  	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11143  	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11144  };
11145  
11146  struct mlx5_ifc_qpdpm_dscp_reg_bits {
11147  	u8         e[0x1];
11148  	u8         reserved_at_01[0x0b];
11149  	u8         prio[0x04];
11150  };
11151  
11152  struct mlx5_ifc_qpdpm_reg_bits {
11153  	u8                                     reserved_at_0[0x8];
11154  	u8                                     local_port[0x8];
11155  	u8                                     reserved_at_10[0x10];
11156  	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11157  };
11158  
11159  struct mlx5_ifc_qpts_reg_bits {
11160  	u8         reserved_at_0[0x8];
11161  	u8         local_port[0x8];
11162  	u8         reserved_at_10[0x2d];
11163  	u8         trust_state[0x3];
11164  };
11165  
11166  struct mlx5_ifc_pptb_reg_bits {
11167  	u8         reserved_at_0[0x2];
11168  	u8         mm[0x2];
11169  	u8         reserved_at_4[0x4];
11170  	u8         local_port[0x8];
11171  	u8         reserved_at_10[0x6];
11172  	u8         cm[0x1];
11173  	u8         um[0x1];
11174  	u8         pm[0x8];
11175  
11176  	u8         prio_x_buff[0x20];
11177  
11178  	u8         pm_msb[0x8];
11179  	u8         reserved_at_48[0x10];
11180  	u8         ctrl_buff[0x4];
11181  	u8         untagged_buff[0x4];
11182  };
11183  
11184  struct mlx5_ifc_sbcam_reg_bits {
11185  	u8         reserved_at_0[0x8];
11186  	u8         feature_group[0x8];
11187  	u8         reserved_at_10[0x8];
11188  	u8         access_reg_group[0x8];
11189  
11190  	u8         reserved_at_20[0x20];
11191  
11192  	u8         sb_access_reg_cap_mask[4][0x20];
11193  
11194  	u8         reserved_at_c0[0x80];
11195  
11196  	u8         sb_feature_cap_mask[4][0x20];
11197  
11198  	u8         reserved_at_1c0[0x40];
11199  
11200  	u8         cap_total_buffer_size[0x20];
11201  
11202  	u8         cap_cell_size[0x10];
11203  	u8         cap_max_pg_buffers[0x8];
11204  	u8         cap_num_pool_supported[0x8];
11205  
11206  	u8         reserved_at_240[0x8];
11207  	u8         cap_sbsr_stat_size[0x8];
11208  	u8         cap_max_tclass_data[0x8];
11209  	u8         cap_max_cpu_ingress_tclass_sb[0x8];
11210  };
11211  
11212  struct mlx5_ifc_pbmc_reg_bits {
11213  	u8         reserved_at_0[0x8];
11214  	u8         local_port[0x8];
11215  	u8         reserved_at_10[0x10];
11216  
11217  	u8         xoff_timer_value[0x10];
11218  	u8         xoff_refresh[0x10];
11219  
11220  	u8         reserved_at_40[0x9];
11221  	u8         fullness_threshold[0x7];
11222  	u8         port_buffer_size[0x10];
11223  
11224  	struct mlx5_ifc_bufferx_reg_bits buffer[10];
11225  
11226  	u8         reserved_at_2e0[0x80];
11227  };
11228  
11229  struct mlx5_ifc_sbpr_reg_bits {
11230  	u8         desc[0x1];
11231  	u8         snap[0x1];
11232  	u8         reserved_at_2[0x4];
11233  	u8         dir[0x2];
11234  	u8         reserved_at_8[0x14];
11235  	u8         pool[0x4];
11236  
11237  	u8         infi_size[0x1];
11238  	u8         reserved_at_21[0x7];
11239  	u8         size[0x18];
11240  
11241  	u8         reserved_at_40[0x1c];
11242  	u8         mode[0x4];
11243  
11244  	u8         reserved_at_60[0x8];
11245  	u8         buff_occupancy[0x18];
11246  
11247  	u8         clr[0x1];
11248  	u8         reserved_at_81[0x7];
11249  	u8         max_buff_occupancy[0x18];
11250  
11251  	u8         reserved_at_a0[0x8];
11252  	u8         ext_buff_occupancy[0x18];
11253  };
11254  
11255  struct mlx5_ifc_sbcm_reg_bits {
11256  	u8         desc[0x1];
11257  	u8         snap[0x1];
11258  	u8         reserved_at_2[0x6];
11259  	u8         local_port[0x8];
11260  	u8         pnat[0x2];
11261  	u8         pg_buff[0x6];
11262  	u8         reserved_at_18[0x6];
11263  	u8         dir[0x2];
11264  
11265  	u8         reserved_at_20[0x1f];
11266  	u8         exc[0x1];
11267  
11268  	u8         reserved_at_40[0x40];
11269  
11270  	u8         reserved_at_80[0x8];
11271  	u8         buff_occupancy[0x18];
11272  
11273  	u8         clr[0x1];
11274  	u8         reserved_at_a1[0x7];
11275  	u8         max_buff_occupancy[0x18];
11276  
11277  	u8         reserved_at_c0[0x8];
11278  	u8         min_buff[0x18];
11279  
11280  	u8         infi_max[0x1];
11281  	u8         reserved_at_e1[0x7];
11282  	u8         max_buff[0x18];
11283  
11284  	u8         reserved_at_100[0x20];
11285  
11286  	u8         reserved_at_120[0x1c];
11287  	u8         pool[0x4];
11288  };
11289  
11290  struct mlx5_ifc_qtct_reg_bits {
11291  	u8         reserved_at_0[0x8];
11292  	u8         port_number[0x8];
11293  	u8         reserved_at_10[0xd];
11294  	u8         prio[0x3];
11295  
11296  	u8         reserved_at_20[0x1d];
11297  	u8         tclass[0x3];
11298  };
11299  
11300  struct mlx5_ifc_mcia_reg_bits {
11301  	u8         l[0x1];
11302  	u8         reserved_at_1[0x7];
11303  	u8         module[0x8];
11304  	u8         reserved_at_10[0x8];
11305  	u8         status[0x8];
11306  
11307  	u8         i2c_device_address[0x8];
11308  	u8         page_number[0x8];
11309  	u8         device_address[0x10];
11310  
11311  	u8         reserved_at_40[0x10];
11312  	u8         size[0x10];
11313  
11314  	u8         reserved_at_60[0x20];
11315  
11316  	u8         dword_0[0x20];
11317  	u8         dword_1[0x20];
11318  	u8         dword_2[0x20];
11319  	u8         dword_3[0x20];
11320  	u8         dword_4[0x20];
11321  	u8         dword_5[0x20];
11322  	u8         dword_6[0x20];
11323  	u8         dword_7[0x20];
11324  	u8         dword_8[0x20];
11325  	u8         dword_9[0x20];
11326  	u8         dword_10[0x20];
11327  	u8         dword_11[0x20];
11328  };
11329  
11330  struct mlx5_ifc_dcbx_param_bits {
11331  	u8         dcbx_cee_cap[0x1];
11332  	u8         dcbx_ieee_cap[0x1];
11333  	u8         dcbx_standby_cap[0x1];
11334  	u8         reserved_at_3[0x5];
11335  	u8         port_number[0x8];
11336  	u8         reserved_at_10[0xa];
11337  	u8         max_application_table_size[6];
11338  	u8         reserved_at_20[0x15];
11339  	u8         version_oper[0x3];
11340  	u8         reserved_at_38[5];
11341  	u8         version_admin[0x3];
11342  	u8         willing_admin[0x1];
11343  	u8         reserved_at_41[0x3];
11344  	u8         pfc_cap_oper[0x4];
11345  	u8         reserved_at_48[0x4];
11346  	u8         pfc_cap_admin[0x4];
11347  	u8         reserved_at_50[0x4];
11348  	u8         num_of_tc_oper[0x4];
11349  	u8         reserved_at_58[0x4];
11350  	u8         num_of_tc_admin[0x4];
11351  	u8         remote_willing[0x1];
11352  	u8         reserved_at_61[3];
11353  	u8         remote_pfc_cap[4];
11354  	u8         reserved_at_68[0x14];
11355  	u8         remote_num_of_tc[0x4];
11356  	u8         reserved_at_80[0x18];
11357  	u8         error[0x8];
11358  	u8         reserved_at_a0[0x160];
11359  };
11360  
11361  enum {
11362  	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11363  	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11364  	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11365  };
11366  
11367  struct mlx5_ifc_lagc_bits {
11368  	u8         fdb_selection_mode[0x1];
11369  	u8         reserved_at_1[0x14];
11370  	u8         port_select_mode[0x3];
11371  	u8         reserved_at_18[0x5];
11372  	u8         lag_state[0x3];
11373  
11374  	u8         reserved_at_20[0xc];
11375  	u8         active_port[0x4];
11376  	u8         reserved_at_30[0x4];
11377  	u8         tx_remap_affinity_2[0x4];
11378  	u8         reserved_at_38[0x4];
11379  	u8         tx_remap_affinity_1[0x4];
11380  };
11381  
11382  struct mlx5_ifc_create_lag_out_bits {
11383  	u8         status[0x8];
11384  	u8         reserved_at_8[0x18];
11385  
11386  	u8         syndrome[0x20];
11387  
11388  	u8         reserved_at_40[0x40];
11389  };
11390  
11391  struct mlx5_ifc_create_lag_in_bits {
11392  	u8         opcode[0x10];
11393  	u8         reserved_at_10[0x10];
11394  
11395  	u8         reserved_at_20[0x10];
11396  	u8         op_mod[0x10];
11397  
11398  	struct mlx5_ifc_lagc_bits ctx;
11399  };
11400  
11401  struct mlx5_ifc_modify_lag_out_bits {
11402  	u8         status[0x8];
11403  	u8         reserved_at_8[0x18];
11404  
11405  	u8         syndrome[0x20];
11406  
11407  	u8         reserved_at_40[0x40];
11408  };
11409  
11410  struct mlx5_ifc_modify_lag_in_bits {
11411  	u8         opcode[0x10];
11412  	u8         reserved_at_10[0x10];
11413  
11414  	u8         reserved_at_20[0x10];
11415  	u8         op_mod[0x10];
11416  
11417  	u8         reserved_at_40[0x20];
11418  	u8         field_select[0x20];
11419  
11420  	struct mlx5_ifc_lagc_bits ctx;
11421  };
11422  
11423  struct mlx5_ifc_query_lag_out_bits {
11424  	u8         status[0x8];
11425  	u8         reserved_at_8[0x18];
11426  
11427  	u8         syndrome[0x20];
11428  
11429  	struct mlx5_ifc_lagc_bits ctx;
11430  };
11431  
11432  struct mlx5_ifc_query_lag_in_bits {
11433  	u8         opcode[0x10];
11434  	u8         reserved_at_10[0x10];
11435  
11436  	u8         reserved_at_20[0x10];
11437  	u8         op_mod[0x10];
11438  
11439  	u8         reserved_at_40[0x40];
11440  };
11441  
11442  struct mlx5_ifc_destroy_lag_out_bits {
11443  	u8         status[0x8];
11444  	u8         reserved_at_8[0x18];
11445  
11446  	u8         syndrome[0x20];
11447  
11448  	u8         reserved_at_40[0x40];
11449  };
11450  
11451  struct mlx5_ifc_destroy_lag_in_bits {
11452  	u8         opcode[0x10];
11453  	u8         reserved_at_10[0x10];
11454  
11455  	u8         reserved_at_20[0x10];
11456  	u8         op_mod[0x10];
11457  
11458  	u8         reserved_at_40[0x40];
11459  };
11460  
11461  struct mlx5_ifc_create_vport_lag_out_bits {
11462  	u8         status[0x8];
11463  	u8         reserved_at_8[0x18];
11464  
11465  	u8         syndrome[0x20];
11466  
11467  	u8         reserved_at_40[0x40];
11468  };
11469  
11470  struct mlx5_ifc_create_vport_lag_in_bits {
11471  	u8         opcode[0x10];
11472  	u8         reserved_at_10[0x10];
11473  
11474  	u8         reserved_at_20[0x10];
11475  	u8         op_mod[0x10];
11476  
11477  	u8         reserved_at_40[0x40];
11478  };
11479  
11480  struct mlx5_ifc_destroy_vport_lag_out_bits {
11481  	u8         status[0x8];
11482  	u8         reserved_at_8[0x18];
11483  
11484  	u8         syndrome[0x20];
11485  
11486  	u8         reserved_at_40[0x40];
11487  };
11488  
11489  struct mlx5_ifc_destroy_vport_lag_in_bits {
11490  	u8         opcode[0x10];
11491  	u8         reserved_at_10[0x10];
11492  
11493  	u8         reserved_at_20[0x10];
11494  	u8         op_mod[0x10];
11495  
11496  	u8         reserved_at_40[0x40];
11497  };
11498  
11499  enum {
11500  	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11501  	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11502  };
11503  
11504  struct mlx5_ifc_modify_memic_in_bits {
11505  	u8         opcode[0x10];
11506  	u8         uid[0x10];
11507  
11508  	u8         reserved_at_20[0x10];
11509  	u8         op_mod[0x10];
11510  
11511  	u8         reserved_at_40[0x20];
11512  
11513  	u8         reserved_at_60[0x18];
11514  	u8         memic_operation_type[0x8];
11515  
11516  	u8         memic_start_addr[0x40];
11517  
11518  	u8         reserved_at_c0[0x140];
11519  };
11520  
11521  struct mlx5_ifc_modify_memic_out_bits {
11522  	u8         status[0x8];
11523  	u8         reserved_at_8[0x18];
11524  
11525  	u8         syndrome[0x20];
11526  
11527  	u8         reserved_at_40[0x40];
11528  
11529  	u8         memic_operation_addr[0x40];
11530  
11531  	u8         reserved_at_c0[0x140];
11532  };
11533  
11534  struct mlx5_ifc_alloc_memic_in_bits {
11535  	u8         opcode[0x10];
11536  	u8         reserved_at_10[0x10];
11537  
11538  	u8         reserved_at_20[0x10];
11539  	u8         op_mod[0x10];
11540  
11541  	u8         reserved_at_30[0x20];
11542  
11543  	u8	   reserved_at_40[0x18];
11544  	u8	   log_memic_addr_alignment[0x8];
11545  
11546  	u8         range_start_addr[0x40];
11547  
11548  	u8         range_size[0x20];
11549  
11550  	u8         memic_size[0x20];
11551  };
11552  
11553  struct mlx5_ifc_alloc_memic_out_bits {
11554  	u8         status[0x8];
11555  	u8         reserved_at_8[0x18];
11556  
11557  	u8         syndrome[0x20];
11558  
11559  	u8         memic_start_addr[0x40];
11560  };
11561  
11562  struct mlx5_ifc_dealloc_memic_in_bits {
11563  	u8         opcode[0x10];
11564  	u8         reserved_at_10[0x10];
11565  
11566  	u8         reserved_at_20[0x10];
11567  	u8         op_mod[0x10];
11568  
11569  	u8         reserved_at_40[0x40];
11570  
11571  	u8         memic_start_addr[0x40];
11572  
11573  	u8         memic_size[0x20];
11574  
11575  	u8         reserved_at_e0[0x20];
11576  };
11577  
11578  struct mlx5_ifc_dealloc_memic_out_bits {
11579  	u8         status[0x8];
11580  	u8         reserved_at_8[0x18];
11581  
11582  	u8         syndrome[0x20];
11583  
11584  	u8         reserved_at_40[0x40];
11585  };
11586  
11587  struct mlx5_ifc_umem_bits {
11588  	u8         reserved_at_0[0x80];
11589  
11590  	u8         ats[0x1];
11591  	u8         reserved_at_81[0x1a];
11592  	u8         log_page_size[0x5];
11593  
11594  	u8         page_offset[0x20];
11595  
11596  	u8         num_of_mtt[0x40];
11597  
11598  	struct mlx5_ifc_mtt_bits  mtt[];
11599  };
11600  
11601  struct mlx5_ifc_uctx_bits {
11602  	u8         cap[0x20];
11603  
11604  	u8         reserved_at_20[0x160];
11605  };
11606  
11607  struct mlx5_ifc_sw_icm_bits {
11608  	u8         modify_field_select[0x40];
11609  
11610  	u8	   reserved_at_40[0x18];
11611  	u8         log_sw_icm_size[0x8];
11612  
11613  	u8         reserved_at_60[0x20];
11614  
11615  	u8         sw_icm_start_addr[0x40];
11616  
11617  	u8         reserved_at_c0[0x140];
11618  };
11619  
11620  struct mlx5_ifc_geneve_tlv_option_bits {
11621  	u8         modify_field_select[0x40];
11622  
11623  	u8         reserved_at_40[0x18];
11624  	u8         geneve_option_fte_index[0x8];
11625  
11626  	u8         option_class[0x10];
11627  	u8         option_type[0x8];
11628  	u8         reserved_at_78[0x3];
11629  	u8         option_data_length[0x5];
11630  
11631  	u8         reserved_at_80[0x180];
11632  };
11633  
11634  struct mlx5_ifc_create_umem_in_bits {
11635  	u8         opcode[0x10];
11636  	u8         uid[0x10];
11637  
11638  	u8         reserved_at_20[0x10];
11639  	u8         op_mod[0x10];
11640  
11641  	u8         reserved_at_40[0x40];
11642  
11643  	struct mlx5_ifc_umem_bits  umem;
11644  };
11645  
11646  struct mlx5_ifc_create_umem_out_bits {
11647  	u8         status[0x8];
11648  	u8         reserved_at_8[0x18];
11649  
11650  	u8         syndrome[0x20];
11651  
11652  	u8         reserved_at_40[0x8];
11653  	u8         umem_id[0x18];
11654  
11655  	u8         reserved_at_60[0x20];
11656  };
11657  
11658  struct mlx5_ifc_destroy_umem_in_bits {
11659  	u8        opcode[0x10];
11660  	u8        uid[0x10];
11661  
11662  	u8        reserved_at_20[0x10];
11663  	u8        op_mod[0x10];
11664  
11665  	u8        reserved_at_40[0x8];
11666  	u8        umem_id[0x18];
11667  
11668  	u8        reserved_at_60[0x20];
11669  };
11670  
11671  struct mlx5_ifc_destroy_umem_out_bits {
11672  	u8        status[0x8];
11673  	u8        reserved_at_8[0x18];
11674  
11675  	u8        syndrome[0x20];
11676  
11677  	u8        reserved_at_40[0x40];
11678  };
11679  
11680  struct mlx5_ifc_create_uctx_in_bits {
11681  	u8         opcode[0x10];
11682  	u8         reserved_at_10[0x10];
11683  
11684  	u8         reserved_at_20[0x10];
11685  	u8         op_mod[0x10];
11686  
11687  	u8         reserved_at_40[0x40];
11688  
11689  	struct mlx5_ifc_uctx_bits  uctx;
11690  };
11691  
11692  struct mlx5_ifc_create_uctx_out_bits {
11693  	u8         status[0x8];
11694  	u8         reserved_at_8[0x18];
11695  
11696  	u8         syndrome[0x20];
11697  
11698  	u8         reserved_at_40[0x10];
11699  	u8         uid[0x10];
11700  
11701  	u8         reserved_at_60[0x20];
11702  };
11703  
11704  struct mlx5_ifc_destroy_uctx_in_bits {
11705  	u8         opcode[0x10];
11706  	u8         reserved_at_10[0x10];
11707  
11708  	u8         reserved_at_20[0x10];
11709  	u8         op_mod[0x10];
11710  
11711  	u8         reserved_at_40[0x10];
11712  	u8         uid[0x10];
11713  
11714  	u8         reserved_at_60[0x20];
11715  };
11716  
11717  struct mlx5_ifc_destroy_uctx_out_bits {
11718  	u8         status[0x8];
11719  	u8         reserved_at_8[0x18];
11720  
11721  	u8         syndrome[0x20];
11722  
11723  	u8          reserved_at_40[0x40];
11724  };
11725  
11726  struct mlx5_ifc_create_sw_icm_in_bits {
11727  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11728  	struct mlx5_ifc_sw_icm_bits		      sw_icm;
11729  };
11730  
11731  struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11732  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11733  	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
11734  };
11735  
11736  struct mlx5_ifc_mtrc_string_db_param_bits {
11737  	u8         string_db_base_address[0x20];
11738  
11739  	u8         reserved_at_20[0x8];
11740  	u8         string_db_size[0x18];
11741  };
11742  
11743  struct mlx5_ifc_mtrc_cap_bits {
11744  	u8         trace_owner[0x1];
11745  	u8         trace_to_memory[0x1];
11746  	u8         reserved_at_2[0x4];
11747  	u8         trc_ver[0x2];
11748  	u8         reserved_at_8[0x14];
11749  	u8         num_string_db[0x4];
11750  
11751  	u8         first_string_trace[0x8];
11752  	u8         num_string_trace[0x8];
11753  	u8         reserved_at_30[0x28];
11754  
11755  	u8         log_max_trace_buffer_size[0x8];
11756  
11757  	u8         reserved_at_60[0x20];
11758  
11759  	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11760  
11761  	u8         reserved_at_280[0x180];
11762  };
11763  
11764  struct mlx5_ifc_mtrc_conf_bits {
11765  	u8         reserved_at_0[0x1c];
11766  	u8         trace_mode[0x4];
11767  	u8         reserved_at_20[0x18];
11768  	u8         log_trace_buffer_size[0x8];
11769  	u8         trace_mkey[0x20];
11770  	u8         reserved_at_60[0x3a0];
11771  };
11772  
11773  struct mlx5_ifc_mtrc_stdb_bits {
11774  	u8         string_db_index[0x4];
11775  	u8         reserved_at_4[0x4];
11776  	u8         read_size[0x18];
11777  	u8         start_offset[0x20];
11778  	u8         string_db_data[];
11779  };
11780  
11781  struct mlx5_ifc_mtrc_ctrl_bits {
11782  	u8         trace_status[0x2];
11783  	u8         reserved_at_2[0x2];
11784  	u8         arm_event[0x1];
11785  	u8         reserved_at_5[0xb];
11786  	u8         modify_field_select[0x10];
11787  	u8         reserved_at_20[0x2b];
11788  	u8         current_timestamp52_32[0x15];
11789  	u8         current_timestamp31_0[0x20];
11790  	u8         reserved_at_80[0x180];
11791  };
11792  
11793  struct mlx5_ifc_host_params_context_bits {
11794  	u8         host_number[0x8];
11795  	u8         reserved_at_8[0x7];
11796  	u8         host_pf_disabled[0x1];
11797  	u8         host_num_of_vfs[0x10];
11798  
11799  	u8         host_total_vfs[0x10];
11800  	u8         host_pci_bus[0x10];
11801  
11802  	u8         reserved_at_40[0x10];
11803  	u8         host_pci_device[0x10];
11804  
11805  	u8         reserved_at_60[0x10];
11806  	u8         host_pci_function[0x10];
11807  
11808  	u8         reserved_at_80[0x180];
11809  };
11810  
11811  struct mlx5_ifc_query_esw_functions_in_bits {
11812  	u8         opcode[0x10];
11813  	u8         reserved_at_10[0x10];
11814  
11815  	u8         reserved_at_20[0x10];
11816  	u8         op_mod[0x10];
11817  
11818  	u8         reserved_at_40[0x40];
11819  };
11820  
11821  struct mlx5_ifc_query_esw_functions_out_bits {
11822  	u8         status[0x8];
11823  	u8         reserved_at_8[0x18];
11824  
11825  	u8         syndrome[0x20];
11826  
11827  	u8         reserved_at_40[0x40];
11828  
11829  	struct mlx5_ifc_host_params_context_bits host_params_context;
11830  
11831  	u8         reserved_at_280[0x180];
11832  	u8         host_sf_enable[][0x40];
11833  };
11834  
11835  struct mlx5_ifc_sf_partition_bits {
11836  	u8         reserved_at_0[0x10];
11837  	u8         log_num_sf[0x8];
11838  	u8         log_sf_bar_size[0x8];
11839  };
11840  
11841  struct mlx5_ifc_query_sf_partitions_out_bits {
11842  	u8         status[0x8];
11843  	u8         reserved_at_8[0x18];
11844  
11845  	u8         syndrome[0x20];
11846  
11847  	u8         reserved_at_40[0x18];
11848  	u8         num_sf_partitions[0x8];
11849  
11850  	u8         reserved_at_60[0x20];
11851  
11852  	struct mlx5_ifc_sf_partition_bits sf_partition[];
11853  };
11854  
11855  struct mlx5_ifc_query_sf_partitions_in_bits {
11856  	u8         opcode[0x10];
11857  	u8         reserved_at_10[0x10];
11858  
11859  	u8         reserved_at_20[0x10];
11860  	u8         op_mod[0x10];
11861  
11862  	u8         reserved_at_40[0x40];
11863  };
11864  
11865  struct mlx5_ifc_dealloc_sf_out_bits {
11866  	u8         status[0x8];
11867  	u8         reserved_at_8[0x18];
11868  
11869  	u8         syndrome[0x20];
11870  
11871  	u8         reserved_at_40[0x40];
11872  };
11873  
11874  struct mlx5_ifc_dealloc_sf_in_bits {
11875  	u8         opcode[0x10];
11876  	u8         reserved_at_10[0x10];
11877  
11878  	u8         reserved_at_20[0x10];
11879  	u8         op_mod[0x10];
11880  
11881  	u8         reserved_at_40[0x10];
11882  	u8         function_id[0x10];
11883  
11884  	u8         reserved_at_60[0x20];
11885  };
11886  
11887  struct mlx5_ifc_alloc_sf_out_bits {
11888  	u8         status[0x8];
11889  	u8         reserved_at_8[0x18];
11890  
11891  	u8         syndrome[0x20];
11892  
11893  	u8         reserved_at_40[0x40];
11894  };
11895  
11896  struct mlx5_ifc_alloc_sf_in_bits {
11897  	u8         opcode[0x10];
11898  	u8         reserved_at_10[0x10];
11899  
11900  	u8         reserved_at_20[0x10];
11901  	u8         op_mod[0x10];
11902  
11903  	u8         reserved_at_40[0x10];
11904  	u8         function_id[0x10];
11905  
11906  	u8         reserved_at_60[0x20];
11907  };
11908  
11909  struct mlx5_ifc_affiliated_event_header_bits {
11910  	u8         reserved_at_0[0x10];
11911  	u8         obj_type[0x10];
11912  
11913  	u8         obj_id[0x20];
11914  };
11915  
11916  enum {
11917  	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11918  	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11919  	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11920  	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
11921  };
11922  
11923  enum {
11924  	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11925  	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11926  	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11927  	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
11928  	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
11929  	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
11930  };
11931  
11932  enum {
11933  	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11934  };
11935  
11936  enum {
11937  	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
11938  	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
11939  	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
11940  	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
11941  };
11942  
11943  enum {
11944  	MLX5_IPSEC_ASO_MODE              = 0x0,
11945  	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
11946  	MLX5_IPSEC_ASO_INC_SN            = 0x2,
11947  };
11948  
11949  enum {
11950  	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
11951  	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
11952  	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
11953  	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
11954  };
11955  
11956  struct mlx5_ifc_ipsec_aso_bits {
11957  	u8         valid[0x1];
11958  	u8         reserved_at_201[0x1];
11959  	u8         mode[0x2];
11960  	u8         window_sz[0x2];
11961  	u8         soft_lft_arm[0x1];
11962  	u8         hard_lft_arm[0x1];
11963  	u8         remove_flow_enable[0x1];
11964  	u8         esn_event_arm[0x1];
11965  	u8         reserved_at_20a[0x16];
11966  
11967  	u8         remove_flow_pkt_cnt[0x20];
11968  
11969  	u8         remove_flow_soft_lft[0x20];
11970  
11971  	u8         reserved_at_260[0x80];
11972  
11973  	u8         mode_parameter[0x20];
11974  
11975  	u8         replay_protection_window[0x100];
11976  };
11977  
11978  struct mlx5_ifc_ipsec_obj_bits {
11979  	u8         modify_field_select[0x40];
11980  	u8         full_offload[0x1];
11981  	u8         reserved_at_41[0x1];
11982  	u8         esn_en[0x1];
11983  	u8         esn_overlap[0x1];
11984  	u8         reserved_at_44[0x2];
11985  	u8         icv_length[0x2];
11986  	u8         reserved_at_48[0x4];
11987  	u8         aso_return_reg[0x4];
11988  	u8         reserved_at_50[0x10];
11989  
11990  	u8         esn_msb[0x20];
11991  
11992  	u8         reserved_at_80[0x8];
11993  	u8         dekn[0x18];
11994  
11995  	u8         salt[0x20];
11996  
11997  	u8         implicit_iv[0x40];
11998  
11999  	u8         reserved_at_100[0x8];
12000  	u8         ipsec_aso_access_pd[0x18];
12001  	u8         reserved_at_120[0xe0];
12002  
12003  	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12004  };
12005  
12006  struct mlx5_ifc_create_ipsec_obj_in_bits {
12007  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12008  	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12009  };
12010  
12011  enum {
12012  	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12013  	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12014  };
12015  
12016  struct mlx5_ifc_query_ipsec_obj_out_bits {
12017  	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12018  	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12019  };
12020  
12021  struct mlx5_ifc_modify_ipsec_obj_in_bits {
12022  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12023  	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12024  };
12025  
12026  enum {
12027  	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12028  };
12029  
12030  enum {
12031  	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12032  	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12033  	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12034  	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12035  };
12036  
12037  #define MLX5_MACSEC_ASO_INC_SN  0x2
12038  #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12039  
12040  struct mlx5_ifc_macsec_aso_bits {
12041  	u8    valid[0x1];
12042  	u8    reserved_at_1[0x1];
12043  	u8    mode[0x2];
12044  	u8    window_size[0x2];
12045  	u8    soft_lifetime_arm[0x1];
12046  	u8    hard_lifetime_arm[0x1];
12047  	u8    remove_flow_enable[0x1];
12048  	u8    epn_event_arm[0x1];
12049  	u8    reserved_at_a[0x16];
12050  
12051  	u8    remove_flow_packet_count[0x20];
12052  
12053  	u8    remove_flow_soft_lifetime[0x20];
12054  
12055  	u8    reserved_at_60[0x80];
12056  
12057  	u8    mode_parameter[0x20];
12058  
12059  	u8    replay_protection_window[8][0x20];
12060  };
12061  
12062  struct mlx5_ifc_macsec_offload_obj_bits {
12063  	u8    modify_field_select[0x40];
12064  
12065  	u8    confidentiality_en[0x1];
12066  	u8    reserved_at_41[0x1];
12067  	u8    epn_en[0x1];
12068  	u8    epn_overlap[0x1];
12069  	u8    reserved_at_44[0x2];
12070  	u8    confidentiality_offset[0x2];
12071  	u8    reserved_at_48[0x4];
12072  	u8    aso_return_reg[0x4];
12073  	u8    reserved_at_50[0x10];
12074  
12075  	u8    epn_msb[0x20];
12076  
12077  	u8    reserved_at_80[0x8];
12078  	u8    dekn[0x18];
12079  
12080  	u8    reserved_at_a0[0x20];
12081  
12082  	u8    sci[0x40];
12083  
12084  	u8    reserved_at_100[0x8];
12085  	u8    macsec_aso_access_pd[0x18];
12086  
12087  	u8    reserved_at_120[0x60];
12088  
12089  	u8    salt[3][0x20];
12090  
12091  	u8    reserved_at_1e0[0x20];
12092  
12093  	struct mlx5_ifc_macsec_aso_bits macsec_aso;
12094  };
12095  
12096  struct mlx5_ifc_create_macsec_obj_in_bits {
12097  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12098  	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12099  };
12100  
12101  struct mlx5_ifc_modify_macsec_obj_in_bits {
12102  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12103  	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12104  };
12105  
12106  enum {
12107  	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12108  	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12109  };
12110  
12111  struct mlx5_ifc_query_macsec_obj_out_bits {
12112  	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12113  	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12114  };
12115  
12116  struct mlx5_ifc_wrapped_dek_bits {
12117  	u8         gcm_iv[0x60];
12118  
12119  	u8         reserved_at_60[0x20];
12120  
12121  	u8         const0[0x1];
12122  	u8         key_size[0x1];
12123  	u8         reserved_at_82[0x2];
12124  	u8         key2_invalid[0x1];
12125  	u8         reserved_at_85[0x3];
12126  	u8         pd[0x18];
12127  
12128  	u8         key_purpose[0x5];
12129  	u8         reserved_at_a5[0x13];
12130  	u8         kek_id[0x8];
12131  
12132  	u8         reserved_at_c0[0x40];
12133  
12134  	u8         key1[0x8][0x20];
12135  
12136  	u8         key2[0x8][0x20];
12137  
12138  	u8         reserved_at_300[0x40];
12139  
12140  	u8         const1[0x1];
12141  	u8         reserved_at_341[0x1f];
12142  
12143  	u8         reserved_at_360[0x20];
12144  
12145  	u8         auth_tag[0x80];
12146  };
12147  
12148  struct mlx5_ifc_encryption_key_obj_bits {
12149  	u8         modify_field_select[0x40];
12150  
12151  	u8         state[0x8];
12152  	u8         sw_wrapped[0x1];
12153  	u8         reserved_at_49[0xb];
12154  	u8         key_size[0x4];
12155  	u8         reserved_at_58[0x4];
12156  	u8         key_purpose[0x4];
12157  
12158  	u8         reserved_at_60[0x8];
12159  	u8         pd[0x18];
12160  
12161  	u8         reserved_at_80[0x100];
12162  
12163  	u8         opaque[0x40];
12164  
12165  	u8         reserved_at_1c0[0x40];
12166  
12167  	u8         key[8][0x80];
12168  
12169  	u8         sw_wrapped_dek[8][0x80];
12170  
12171  	u8         reserved_at_a00[0x600];
12172  };
12173  
12174  struct mlx5_ifc_create_encryption_key_in_bits {
12175  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12176  	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12177  };
12178  
12179  struct mlx5_ifc_modify_encryption_key_in_bits {
12180  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12181  	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12182  };
12183  
12184  enum {
12185  	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH		= 0x0,
12186  	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2		= 0x1,
12187  	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG	= 0x2,
12188  	MLX5_FLOW_METER_MODE_NUM_PACKETS		= 0x3,
12189  };
12190  
12191  struct mlx5_ifc_flow_meter_parameters_bits {
12192  	u8         valid[0x1];
12193  	u8         bucket_overflow[0x1];
12194  	u8         start_color[0x2];
12195  	u8         both_buckets_on_green[0x1];
12196  	u8         reserved_at_5[0x1];
12197  	u8         meter_mode[0x2];
12198  	u8         reserved_at_8[0x18];
12199  
12200  	u8         reserved_at_20[0x20];
12201  
12202  	u8         reserved_at_40[0x3];
12203  	u8         cbs_exponent[0x5];
12204  	u8         cbs_mantissa[0x8];
12205  	u8         reserved_at_50[0x3];
12206  	u8         cir_exponent[0x5];
12207  	u8         cir_mantissa[0x8];
12208  
12209  	u8         reserved_at_60[0x20];
12210  
12211  	u8         reserved_at_80[0x3];
12212  	u8         ebs_exponent[0x5];
12213  	u8         ebs_mantissa[0x8];
12214  	u8         reserved_at_90[0x3];
12215  	u8         eir_exponent[0x5];
12216  	u8         eir_mantissa[0x8];
12217  
12218  	u8         reserved_at_a0[0x60];
12219  };
12220  
12221  struct mlx5_ifc_flow_meter_aso_obj_bits {
12222  	u8         modify_field_select[0x40];
12223  
12224  	u8         reserved_at_40[0x40];
12225  
12226  	u8         reserved_at_80[0x8];
12227  	u8         meter_aso_access_pd[0x18];
12228  
12229  	u8         reserved_at_a0[0x160];
12230  
12231  	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12232  };
12233  
12234  struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12235  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12236  	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12237  };
12238  
12239  struct mlx5_ifc_int_kek_obj_bits {
12240  	u8         modify_field_select[0x40];
12241  
12242  	u8         state[0x8];
12243  	u8         auto_gen[0x1];
12244  	u8         reserved_at_49[0xb];
12245  	u8         key_size[0x4];
12246  	u8         reserved_at_58[0x8];
12247  
12248  	u8         reserved_at_60[0x8];
12249  	u8         pd[0x18];
12250  
12251  	u8         reserved_at_80[0x180];
12252  	u8         key[8][0x80];
12253  
12254  	u8         reserved_at_600[0x200];
12255  };
12256  
12257  struct mlx5_ifc_create_int_kek_obj_in_bits {
12258  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12259  	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12260  };
12261  
12262  struct mlx5_ifc_create_int_kek_obj_out_bits {
12263  	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12264  	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12265  };
12266  
12267  struct mlx5_ifc_sampler_obj_bits {
12268  	u8         modify_field_select[0x40];
12269  
12270  	u8         table_type[0x8];
12271  	u8         level[0x8];
12272  	u8         reserved_at_50[0xf];
12273  	u8         ignore_flow_level[0x1];
12274  
12275  	u8         sample_ratio[0x20];
12276  
12277  	u8         reserved_at_80[0x8];
12278  	u8         sample_table_id[0x18];
12279  
12280  	u8         reserved_at_a0[0x8];
12281  	u8         default_table_id[0x18];
12282  
12283  	u8         sw_steering_icm_address_rx[0x40];
12284  	u8         sw_steering_icm_address_tx[0x40];
12285  
12286  	u8         reserved_at_140[0xa0];
12287  };
12288  
12289  struct mlx5_ifc_create_sampler_obj_in_bits {
12290  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12291  	struct mlx5_ifc_sampler_obj_bits sampler_object;
12292  };
12293  
12294  struct mlx5_ifc_query_sampler_obj_out_bits {
12295  	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12296  	struct mlx5_ifc_sampler_obj_bits sampler_object;
12297  };
12298  
12299  enum {
12300  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12301  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12302  };
12303  
12304  enum {
12305  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12306  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12307  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12308  };
12309  
12310  struct mlx5_ifc_tls_static_params_bits {
12311  	u8         const_2[0x2];
12312  	u8         tls_version[0x4];
12313  	u8         const_1[0x2];
12314  	u8         reserved_at_8[0x14];
12315  	u8         encryption_standard[0x4];
12316  
12317  	u8         reserved_at_20[0x20];
12318  
12319  	u8         initial_record_number[0x40];
12320  
12321  	u8         resync_tcp_sn[0x20];
12322  
12323  	u8         gcm_iv[0x20];
12324  
12325  	u8         implicit_iv[0x40];
12326  
12327  	u8         reserved_at_100[0x8];
12328  	u8         dek_index[0x18];
12329  
12330  	u8         reserved_at_120[0xe0];
12331  };
12332  
12333  struct mlx5_ifc_tls_progress_params_bits {
12334  	u8         next_record_tcp_sn[0x20];
12335  
12336  	u8         hw_resync_tcp_sn[0x20];
12337  
12338  	u8         record_tracker_state[0x2];
12339  	u8         auth_state[0x2];
12340  	u8         reserved_at_44[0x4];
12341  	u8         hw_offset_record_number[0x18];
12342  };
12343  
12344  enum {
12345  	MLX5_MTT_PERM_READ	= 1 << 0,
12346  	MLX5_MTT_PERM_WRITE	= 1 << 1,
12347  	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12348  };
12349  
12350  enum {
12351  	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
12352  	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
12353  };
12354  
12355  struct mlx5_ifc_suspend_vhca_in_bits {
12356  	u8         opcode[0x10];
12357  	u8         uid[0x10];
12358  
12359  	u8         reserved_at_20[0x10];
12360  	u8         op_mod[0x10];
12361  
12362  	u8         reserved_at_40[0x10];
12363  	u8         vhca_id[0x10];
12364  
12365  	u8         reserved_at_60[0x20];
12366  };
12367  
12368  struct mlx5_ifc_suspend_vhca_out_bits {
12369  	u8         status[0x8];
12370  	u8         reserved_at_8[0x18];
12371  
12372  	u8         syndrome[0x20];
12373  
12374  	u8         reserved_at_40[0x40];
12375  };
12376  
12377  enum {
12378  	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
12379  	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
12380  };
12381  
12382  struct mlx5_ifc_resume_vhca_in_bits {
12383  	u8         opcode[0x10];
12384  	u8         uid[0x10];
12385  
12386  	u8         reserved_at_20[0x10];
12387  	u8         op_mod[0x10];
12388  
12389  	u8         reserved_at_40[0x10];
12390  	u8         vhca_id[0x10];
12391  
12392  	u8         reserved_at_60[0x20];
12393  };
12394  
12395  struct mlx5_ifc_resume_vhca_out_bits {
12396  	u8         status[0x8];
12397  	u8         reserved_at_8[0x18];
12398  
12399  	u8         syndrome[0x20];
12400  
12401  	u8         reserved_at_40[0x40];
12402  };
12403  
12404  struct mlx5_ifc_query_vhca_migration_state_in_bits {
12405  	u8         opcode[0x10];
12406  	u8         uid[0x10];
12407  
12408  	u8         reserved_at_20[0x10];
12409  	u8         op_mod[0x10];
12410  
12411  	u8         incremental[0x1];
12412  	u8         reserved_at_41[0xf];
12413  	u8         vhca_id[0x10];
12414  
12415  	u8         reserved_at_60[0x20];
12416  };
12417  
12418  struct mlx5_ifc_query_vhca_migration_state_out_bits {
12419  	u8         status[0x8];
12420  	u8         reserved_at_8[0x18];
12421  
12422  	u8         syndrome[0x20];
12423  
12424  	u8         reserved_at_40[0x40];
12425  
12426  	u8         required_umem_size[0x20];
12427  
12428  	u8         reserved_at_a0[0x160];
12429  };
12430  
12431  struct mlx5_ifc_save_vhca_state_in_bits {
12432  	u8         opcode[0x10];
12433  	u8         uid[0x10];
12434  
12435  	u8         reserved_at_20[0x10];
12436  	u8         op_mod[0x10];
12437  
12438  	u8         incremental[0x1];
12439  	u8         set_track[0x1];
12440  	u8         reserved_at_42[0xe];
12441  	u8         vhca_id[0x10];
12442  
12443  	u8         reserved_at_60[0x20];
12444  
12445  	u8         va[0x40];
12446  
12447  	u8         mkey[0x20];
12448  
12449  	u8         size[0x20];
12450  };
12451  
12452  struct mlx5_ifc_save_vhca_state_out_bits {
12453  	u8         status[0x8];
12454  	u8         reserved_at_8[0x18];
12455  
12456  	u8         syndrome[0x20];
12457  
12458  	u8         actual_image_size[0x20];
12459  
12460  	u8         reserved_at_60[0x20];
12461  };
12462  
12463  struct mlx5_ifc_load_vhca_state_in_bits {
12464  	u8         opcode[0x10];
12465  	u8         uid[0x10];
12466  
12467  	u8         reserved_at_20[0x10];
12468  	u8         op_mod[0x10];
12469  
12470  	u8         reserved_at_40[0x10];
12471  	u8         vhca_id[0x10];
12472  
12473  	u8         reserved_at_60[0x20];
12474  
12475  	u8         va[0x40];
12476  
12477  	u8         mkey[0x20];
12478  
12479  	u8         size[0x20];
12480  };
12481  
12482  struct mlx5_ifc_load_vhca_state_out_bits {
12483  	u8         status[0x8];
12484  	u8         reserved_at_8[0x18];
12485  
12486  	u8         syndrome[0x20];
12487  
12488  	u8         reserved_at_40[0x40];
12489  };
12490  
12491  struct mlx5_ifc_adv_virtualization_cap_bits {
12492  	u8         reserved_at_0[0x3];
12493  	u8         pg_track_log_max_num[0x5];
12494  	u8         pg_track_max_num_range[0x8];
12495  	u8         pg_track_log_min_addr_space[0x8];
12496  	u8         pg_track_log_max_addr_space[0x8];
12497  
12498  	u8         reserved_at_20[0x3];
12499  	u8         pg_track_log_min_msg_size[0x5];
12500  	u8         reserved_at_28[0x3];
12501  	u8         pg_track_log_max_msg_size[0x5];
12502  	u8         reserved_at_30[0x3];
12503  	u8         pg_track_log_min_page_size[0x5];
12504  	u8         reserved_at_38[0x3];
12505  	u8         pg_track_log_max_page_size[0x5];
12506  
12507  	u8         reserved_at_40[0x7c0];
12508  };
12509  
12510  struct mlx5_ifc_page_track_report_entry_bits {
12511  	u8         dirty_address_high[0x20];
12512  
12513  	u8         dirty_address_low[0x20];
12514  };
12515  
12516  enum {
12517  	MLX5_PAGE_TRACK_STATE_TRACKING,
12518  	MLX5_PAGE_TRACK_STATE_REPORTING,
12519  	MLX5_PAGE_TRACK_STATE_ERROR,
12520  };
12521  
12522  struct mlx5_ifc_page_track_range_bits {
12523  	u8         start_address[0x40];
12524  
12525  	u8         length[0x40];
12526  };
12527  
12528  struct mlx5_ifc_page_track_bits {
12529  	u8         modify_field_select[0x40];
12530  
12531  	u8         reserved_at_40[0x10];
12532  	u8         vhca_id[0x10];
12533  
12534  	u8         reserved_at_60[0x20];
12535  
12536  	u8         state[0x4];
12537  	u8         track_type[0x4];
12538  	u8         log_addr_space_size[0x8];
12539  	u8         reserved_at_90[0x3];
12540  	u8         log_page_size[0x5];
12541  	u8         reserved_at_98[0x3];
12542  	u8         log_msg_size[0x5];
12543  
12544  	u8         reserved_at_a0[0x8];
12545  	u8         reporting_qpn[0x18];
12546  
12547  	u8         reserved_at_c0[0x18];
12548  	u8         num_ranges[0x8];
12549  
12550  	u8         reserved_at_e0[0x20];
12551  
12552  	u8         range_start_address[0x40];
12553  
12554  	u8         length[0x40];
12555  
12556  	struct     mlx5_ifc_page_track_range_bits track_range[0];
12557  };
12558  
12559  struct mlx5_ifc_create_page_track_obj_in_bits {
12560  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12561  	struct mlx5_ifc_page_track_bits obj_context;
12562  };
12563  
12564  struct mlx5_ifc_modify_page_track_obj_in_bits {
12565  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12566  	struct mlx5_ifc_page_track_bits obj_context;
12567  };
12568  
12569  #endif /* MLX5_IFC_H */
12570