1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 gpcdma: dma-controller@2600000 { 77 compatible = "nvidia,tegra186-gpcdma"; 78 reg = <0x0 0x2600000 0x0 0x210000>; 79 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80 reset-names = "gpcdma"; 81 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 113 #dma-cells = <1>; 114 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 115 dma-coherent; 116 dma-channel-mask = <0xfffffffe>; 117 status = "okay"; 118 }; 119 120 aconnect@2900000 { 121 compatible = "nvidia,tegra186-aconnect", 122 "nvidia,tegra210-aconnect"; 123 clocks = <&bpmp TEGRA186_CLK_APE>, 124 <&bpmp TEGRA186_CLK_APB2APE>; 125 clock-names = "ape", "apb2ape"; 126 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 127 #address-cells = <1>; 128 #size-cells = <1>; 129 ranges = <0x02900000 0x0 0x02900000 0x200000>; 130 status = "disabled"; 131 132 tegra_ahub: ahub@2900800 { 133 compatible = "nvidia,tegra186-ahub"; 134 reg = <0x02900800 0x800>; 135 clocks = <&bpmp TEGRA186_CLK_AHUB>; 136 clock-names = "ahub"; 137 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 139 assigned-clock-rates = <81600000>; 140 #address-cells = <1>; 141 #size-cells = <1>; 142 ranges = <0x02900800 0x02900800 0x11800>; 143 status = "disabled"; 144 145 tegra_i2s1: i2s@2901000 { 146 compatible = "nvidia,tegra186-i2s", 147 "nvidia,tegra210-i2s"; 148 reg = <0x2901000 0x100>; 149 clocks = <&bpmp TEGRA186_CLK_I2S1>, 150 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 151 clock-names = "i2s", "sync_input"; 152 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 153 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 154 assigned-clock-rates = <1536000>; 155 sound-name-prefix = "I2S1"; 156 status = "disabled"; 157 }; 158 159 tegra_i2s2: i2s@2901100 { 160 compatible = "nvidia,tegra186-i2s", 161 "nvidia,tegra210-i2s"; 162 reg = <0x2901100 0x100>; 163 clocks = <&bpmp TEGRA186_CLK_I2S2>, 164 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 165 clock-names = "i2s", "sync_input"; 166 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 167 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 168 assigned-clock-rates = <1536000>; 169 sound-name-prefix = "I2S2"; 170 status = "disabled"; 171 }; 172 173 tegra_i2s3: i2s@2901200 { 174 compatible = "nvidia,tegra186-i2s", 175 "nvidia,tegra210-i2s"; 176 reg = <0x2901200 0x100>; 177 clocks = <&bpmp TEGRA186_CLK_I2S3>, 178 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 179 clock-names = "i2s", "sync_input"; 180 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 181 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 182 assigned-clock-rates = <1536000>; 183 sound-name-prefix = "I2S3"; 184 status = "disabled"; 185 }; 186 187 tegra_i2s4: i2s@2901300 { 188 compatible = "nvidia,tegra186-i2s", 189 "nvidia,tegra210-i2s"; 190 reg = <0x2901300 0x100>; 191 clocks = <&bpmp TEGRA186_CLK_I2S4>, 192 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 193 clock-names = "i2s", "sync_input"; 194 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 195 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 196 assigned-clock-rates = <1536000>; 197 sound-name-prefix = "I2S4"; 198 status = "disabled"; 199 }; 200 201 tegra_i2s5: i2s@2901400 { 202 compatible = "nvidia,tegra186-i2s", 203 "nvidia,tegra210-i2s"; 204 reg = <0x2901400 0x100>; 205 clocks = <&bpmp TEGRA186_CLK_I2S5>, 206 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 207 clock-names = "i2s", "sync_input"; 208 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 209 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 210 assigned-clock-rates = <1536000>; 211 sound-name-prefix = "I2S5"; 212 status = "disabled"; 213 }; 214 215 tegra_i2s6: i2s@2901500 { 216 compatible = "nvidia,tegra186-i2s", 217 "nvidia,tegra210-i2s"; 218 reg = <0x2901500 0x100>; 219 clocks = <&bpmp TEGRA186_CLK_I2S6>, 220 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 221 clock-names = "i2s", "sync_input"; 222 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 223 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 224 assigned-clock-rates = <1536000>; 225 sound-name-prefix = "I2S6"; 226 status = "disabled"; 227 }; 228 229 tegra_sfc1: sfc@2902000 { 230 compatible = "nvidia,tegra186-sfc", 231 "nvidia,tegra210-sfc"; 232 reg = <0x2902000 0x200>; 233 sound-name-prefix = "SFC1"; 234 status = "disabled"; 235 }; 236 237 tegra_sfc2: sfc@2902200 { 238 compatible = "nvidia,tegra186-sfc", 239 "nvidia,tegra210-sfc"; 240 reg = <0x2902200 0x200>; 241 sound-name-prefix = "SFC2"; 242 status = "disabled"; 243 }; 244 245 tegra_sfc3: sfc@2902400 { 246 compatible = "nvidia,tegra186-sfc", 247 "nvidia,tegra210-sfc"; 248 reg = <0x2902400 0x200>; 249 sound-name-prefix = "SFC3"; 250 status = "disabled"; 251 }; 252 253 tegra_sfc4: sfc@2902600 { 254 compatible = "nvidia,tegra186-sfc", 255 "nvidia,tegra210-sfc"; 256 reg = <0x2902600 0x200>; 257 sound-name-prefix = "SFC4"; 258 status = "disabled"; 259 }; 260 261 tegra_amx1: amx@2903000 { 262 compatible = "nvidia,tegra186-amx", 263 "nvidia,tegra210-amx"; 264 reg = <0x2903000 0x100>; 265 sound-name-prefix = "AMX1"; 266 status = "disabled"; 267 }; 268 269 tegra_amx2: amx@2903100 { 270 compatible = "nvidia,tegra186-amx", 271 "nvidia,tegra210-amx"; 272 reg = <0x2903100 0x100>; 273 sound-name-prefix = "AMX2"; 274 status = "disabled"; 275 }; 276 277 tegra_amx3: amx@2903200 { 278 compatible = "nvidia,tegra186-amx", 279 "nvidia,tegra210-amx"; 280 reg = <0x2903200 0x100>; 281 sound-name-prefix = "AMX3"; 282 status = "disabled"; 283 }; 284 285 tegra_amx4: amx@2903300 { 286 compatible = "nvidia,tegra186-amx", 287 "nvidia,tegra210-amx"; 288 reg = <0x2903300 0x100>; 289 sound-name-prefix = "AMX4"; 290 status = "disabled"; 291 }; 292 293 tegra_adx1: adx@2903800 { 294 compatible = "nvidia,tegra186-adx", 295 "nvidia,tegra210-adx"; 296 reg = <0x2903800 0x100>; 297 sound-name-prefix = "ADX1"; 298 status = "disabled"; 299 }; 300 301 tegra_adx2: adx@2903900 { 302 compatible = "nvidia,tegra186-adx", 303 "nvidia,tegra210-adx"; 304 reg = <0x2903900 0x100>; 305 sound-name-prefix = "ADX2"; 306 status = "disabled"; 307 }; 308 309 tegra_adx3: adx@2903a00 { 310 compatible = "nvidia,tegra186-adx", 311 "nvidia,tegra210-adx"; 312 reg = <0x2903a00 0x100>; 313 sound-name-prefix = "ADX3"; 314 status = "disabled"; 315 }; 316 317 tegra_adx4: adx@2903b00 { 318 compatible = "nvidia,tegra186-adx", 319 "nvidia,tegra210-adx"; 320 reg = <0x2903b00 0x100>; 321 sound-name-prefix = "ADX4"; 322 status = "disabled"; 323 }; 324 325 tegra_dmic1: dmic@2904000 { 326 compatible = "nvidia,tegra210-dmic"; 327 reg = <0x2904000 0x100>; 328 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 329 clock-names = "dmic"; 330 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 331 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 332 assigned-clock-rates = <3072000>; 333 sound-name-prefix = "DMIC1"; 334 status = "disabled"; 335 }; 336 337 tegra_dmic2: dmic@2904100 { 338 compatible = "nvidia,tegra210-dmic"; 339 reg = <0x2904100 0x100>; 340 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 341 clock-names = "dmic"; 342 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 343 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 344 assigned-clock-rates = <3072000>; 345 sound-name-prefix = "DMIC2"; 346 status = "disabled"; 347 }; 348 349 tegra_dmic3: dmic@2904200 { 350 compatible = "nvidia,tegra210-dmic"; 351 reg = <0x2904200 0x100>; 352 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 353 clock-names = "dmic"; 354 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 355 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 356 assigned-clock-rates = <3072000>; 357 sound-name-prefix = "DMIC3"; 358 status = "disabled"; 359 }; 360 361 tegra_dmic4: dmic@2904300 { 362 compatible = "nvidia,tegra210-dmic"; 363 reg = <0x2904300 0x100>; 364 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 365 clock-names = "dmic"; 366 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 367 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 368 assigned-clock-rates = <3072000>; 369 sound-name-prefix = "DMIC4"; 370 status = "disabled"; 371 }; 372 373 tegra_dspk1: dspk@2905000 { 374 compatible = "nvidia,tegra186-dspk"; 375 reg = <0x2905000 0x100>; 376 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 377 clock-names = "dspk"; 378 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 379 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 380 assigned-clock-rates = <12288000>; 381 sound-name-prefix = "DSPK1"; 382 status = "disabled"; 383 }; 384 385 tegra_dspk2: dspk@2905100 { 386 compatible = "nvidia,tegra186-dspk"; 387 reg = <0x2905100 0x100>; 388 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 389 clock-names = "dspk"; 390 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 391 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 392 assigned-clock-rates = <12288000>; 393 sound-name-prefix = "DSPK2"; 394 status = "disabled"; 395 }; 396 397 tegra_ope1: processing-engine@2908000 { 398 compatible = "nvidia,tegra186-ope", 399 "nvidia,tegra210-ope"; 400 reg = <0x2908000 0x100>; 401 #address-cells = <1>; 402 #size-cells = <1>; 403 ranges; 404 sound-name-prefix = "OPE1"; 405 status = "disabled"; 406 407 equalizer@2908100 { 408 compatible = "nvidia,tegra186-peq", 409 "nvidia,tegra210-peq"; 410 reg = <0x2908100 0x100>; 411 }; 412 413 dynamic-range-compressor@2908200 { 414 compatible = "nvidia,tegra186-mbdrc", 415 "nvidia,tegra210-mbdrc"; 416 reg = <0x2908200 0x200>; 417 }; 418 }; 419 420 tegra_mvc1: mvc@290a000 { 421 compatible = "nvidia,tegra186-mvc", 422 "nvidia,tegra210-mvc"; 423 reg = <0x290a000 0x200>; 424 sound-name-prefix = "MVC1"; 425 status = "disabled"; 426 }; 427 428 tegra_mvc2: mvc@290a200 { 429 compatible = "nvidia,tegra186-mvc", 430 "nvidia,tegra210-mvc"; 431 reg = <0x290a200 0x200>; 432 sound-name-prefix = "MVC2"; 433 status = "disabled"; 434 }; 435 436 tegra_amixer: amixer@290bb00 { 437 compatible = "nvidia,tegra186-amixer", 438 "nvidia,tegra210-amixer"; 439 reg = <0x290bb00 0x800>; 440 sound-name-prefix = "MIXER1"; 441 status = "disabled"; 442 }; 443 444 tegra_admaif: admaif@290f000 { 445 compatible = "nvidia,tegra186-admaif"; 446 reg = <0x0290f000 0x1000>; 447 dmas = <&adma 1>, <&adma 1>, 448 <&adma 2>, <&adma 2>, 449 <&adma 3>, <&adma 3>, 450 <&adma 4>, <&adma 4>, 451 <&adma 5>, <&adma 5>, 452 <&adma 6>, <&adma 6>, 453 <&adma 7>, <&adma 7>, 454 <&adma 8>, <&adma 8>, 455 <&adma 9>, <&adma 9>, 456 <&adma 10>, <&adma 10>, 457 <&adma 11>, <&adma 11>, 458 <&adma 12>, <&adma 12>, 459 <&adma 13>, <&adma 13>, 460 <&adma 14>, <&adma 14>, 461 <&adma 15>, <&adma 15>, 462 <&adma 16>, <&adma 16>, 463 <&adma 17>, <&adma 17>, 464 <&adma 18>, <&adma 18>, 465 <&adma 19>, <&adma 19>, 466 <&adma 20>, <&adma 20>; 467 dma-names = "rx1", "tx1", 468 "rx2", "tx2", 469 "rx3", "tx3", 470 "rx4", "tx4", 471 "rx5", "tx5", 472 "rx6", "tx6", 473 "rx7", "tx7", 474 "rx8", "tx8", 475 "rx9", "tx9", 476 "rx10", "tx10", 477 "rx11", "tx11", 478 "rx12", "tx12", 479 "rx13", "tx13", 480 "rx14", "tx14", 481 "rx15", "tx15", 482 "rx16", "tx16", 483 "rx17", "tx17", 484 "rx18", "tx18", 485 "rx19", "tx19", 486 "rx20", "tx20"; 487 status = "disabled"; 488 }; 489 490 tegra_asrc: asrc@2910000 { 491 compatible = "nvidia,tegra186-asrc"; 492 reg = <0x2910000 0x2000>; 493 sound-name-prefix = "ASRC1"; 494 status = "disabled"; 495 }; 496 }; 497 498 adma: dma-controller@2930000 { 499 compatible = "nvidia,tegra186-adma"; 500 reg = <0x02930000 0x20000>; 501 interrupt-parent = <&agic>; 502 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 534 #dma-cells = <1>; 535 clocks = <&bpmp TEGRA186_CLK_AHUB>; 536 clock-names = "d_audio"; 537 status = "disabled"; 538 }; 539 540 agic: interrupt-controller@2a40000 { 541 compatible = "nvidia,tegra186-agic", 542 "nvidia,tegra210-agic"; 543 #interrupt-cells = <3>; 544 interrupt-controller; 545 reg = <0x02a41000 0x1000>, 546 <0x02a42000 0x2000>; 547 interrupts = <GIC_SPI 145 548 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 549 clocks = <&bpmp TEGRA186_CLK_APE>; 550 clock-names = "clk"; 551 status = "disabled"; 552 }; 553 }; 554 555 mc: memory-controller@2c00000 { 556 compatible = "nvidia,tegra186-mc"; 557 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 558 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 559 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 560 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 561 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 562 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 563 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 564 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 565 status = "disabled"; 566 567 #interconnect-cells = <1>; 568 #address-cells = <2>; 569 #size-cells = <2>; 570 571 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 572 573 /* 574 * Memory clients have access to all 40 bits that the memory 575 * controller can address. 576 */ 577 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 578 579 emc: external-memory-controller@2c60000 { 580 compatible = "nvidia,tegra186-emc"; 581 reg = <0x0 0x02c60000 0x0 0x50000>; 582 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&bpmp TEGRA186_CLK_EMC>; 584 clock-names = "emc"; 585 586 #interconnect-cells = <0>; 587 588 nvidia,bpmp = <&bpmp>; 589 }; 590 }; 591 592 timer@3010000 { 593 compatible = "nvidia,tegra186-timer"; 594 reg = <0x0 0x03010000 0x0 0x000e0000>; 595 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 605 status = "okay"; 606 }; 607 608 uarta: serial@3100000 { 609 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 610 reg = <0x0 0x03100000 0x0 0x40>; 611 reg-shift = <2>; 612 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&bpmp TEGRA186_CLK_UARTA>; 614 resets = <&bpmp TEGRA186_RESET_UARTA>; 615 status = "disabled"; 616 }; 617 618 uartb: serial@3110000 { 619 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 620 reg = <0x0 0x03110000 0x0 0x40>; 621 reg-shift = <2>; 622 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&bpmp TEGRA186_CLK_UARTB>; 624 resets = <&bpmp TEGRA186_RESET_UARTB>; 625 status = "disabled"; 626 }; 627 628 uartd: serial@3130000 { 629 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 630 reg = <0x0 0x03130000 0x0 0x40>; 631 reg-shift = <2>; 632 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&bpmp TEGRA186_CLK_UARTD>; 634 resets = <&bpmp TEGRA186_RESET_UARTD>; 635 status = "disabled"; 636 }; 637 638 uarte: serial@3140000 { 639 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 640 reg = <0x0 0x03140000 0x0 0x40>; 641 reg-shift = <2>; 642 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&bpmp TEGRA186_CLK_UARTE>; 644 resets = <&bpmp TEGRA186_RESET_UARTE>; 645 status = "disabled"; 646 }; 647 648 uartf: serial@3150000 { 649 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 650 reg = <0x0 0x03150000 0x0 0x40>; 651 reg-shift = <2>; 652 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&bpmp TEGRA186_CLK_UARTF>; 654 resets = <&bpmp TEGRA186_RESET_UARTF>; 655 status = "disabled"; 656 }; 657 658 gen1_i2c: i2c@3160000 { 659 compatible = "nvidia,tegra186-i2c"; 660 reg = <0x0 0x03160000 0x0 0x10000>; 661 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 clocks = <&bpmp TEGRA186_CLK_I2C1>; 665 clock-names = "div-clk"; 666 resets = <&bpmp TEGRA186_RESET_I2C1>; 667 reset-names = "i2c"; 668 dmas = <&gpcdma 21>, <&gpcdma 21>; 669 dma-names = "rx", "tx"; 670 status = "disabled"; 671 }; 672 673 cam_i2c: i2c@3180000 { 674 compatible = "nvidia,tegra186-i2c"; 675 reg = <0x0 0x03180000 0x0 0x10000>; 676 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 clocks = <&bpmp TEGRA186_CLK_I2C3>; 680 clock-names = "div-clk"; 681 resets = <&bpmp TEGRA186_RESET_I2C3>; 682 reset-names = "i2c"; 683 dmas = <&gpcdma 23>, <&gpcdma 23>; 684 dma-names = "rx", "tx"; 685 status = "disabled"; 686 }; 687 688 /* shares pads with dpaux1 */ 689 dp_aux_ch1_i2c: i2c@3190000 { 690 compatible = "nvidia,tegra186-i2c"; 691 reg = <0x0 0x03190000 0x0 0x10000>; 692 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 clocks = <&bpmp TEGRA186_CLK_I2C4>; 696 clock-names = "div-clk"; 697 resets = <&bpmp TEGRA186_RESET_I2C4>; 698 reset-names = "i2c"; 699 pinctrl-names = "default", "idle"; 700 pinctrl-0 = <&state_dpaux1_i2c>; 701 pinctrl-1 = <&state_dpaux1_off>; 702 dmas = <&gpcdma 26>, <&gpcdma 26>; 703 dma-names = "rx", "tx"; 704 status = "disabled"; 705 }; 706 707 /* controlled by BPMP, should not be enabled */ 708 pwr_i2c: i2c@31a0000 { 709 compatible = "nvidia,tegra186-i2c"; 710 reg = <0x0 0x031a0000 0x0 0x10000>; 711 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 clocks = <&bpmp TEGRA186_CLK_I2C5>; 715 clock-names = "div-clk"; 716 resets = <&bpmp TEGRA186_RESET_I2C5>; 717 reset-names = "i2c"; 718 status = "disabled"; 719 }; 720 721 /* shares pads with dpaux0 */ 722 dp_aux_ch0_i2c: i2c@31b0000 { 723 compatible = "nvidia,tegra186-i2c"; 724 reg = <0x0 0x031b0000 0x0 0x10000>; 725 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 clocks = <&bpmp TEGRA186_CLK_I2C6>; 729 clock-names = "div-clk"; 730 resets = <&bpmp TEGRA186_RESET_I2C6>; 731 reset-names = "i2c"; 732 pinctrl-names = "default", "idle"; 733 pinctrl-0 = <&state_dpaux_i2c>; 734 pinctrl-1 = <&state_dpaux_off>; 735 dmas = <&gpcdma 30>, <&gpcdma 30>; 736 dma-names = "rx", "tx"; 737 status = "disabled"; 738 }; 739 740 gen7_i2c: i2c@31c0000 { 741 compatible = "nvidia,tegra186-i2c"; 742 reg = <0x0 0x031c0000 0x0 0x10000>; 743 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 clocks = <&bpmp TEGRA186_CLK_I2C7>; 747 clock-names = "div-clk"; 748 resets = <&bpmp TEGRA186_RESET_I2C7>; 749 reset-names = "i2c"; 750 dmas = <&gpcdma 27>, <&gpcdma 27>; 751 dma-names = "rx", "tx"; 752 status = "disabled"; 753 }; 754 755 gen9_i2c: i2c@31e0000 { 756 compatible = "nvidia,tegra186-i2c"; 757 reg = <0x0 0x031e0000 0x0 0x10000>; 758 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 clocks = <&bpmp TEGRA186_CLK_I2C9>; 762 clock-names = "div-clk"; 763 resets = <&bpmp TEGRA186_RESET_I2C9>; 764 reset-names = "i2c"; 765 dmas = <&gpcdma 31>, <&gpcdma 31>; 766 dma-names = "rx", "tx"; 767 status = "disabled"; 768 }; 769 770 pwm1: pwm@3280000 { 771 compatible = "nvidia,tegra186-pwm"; 772 reg = <0x0 0x3280000 0x0 0x10000>; 773 clocks = <&bpmp TEGRA186_CLK_PWM1>; 774 resets = <&bpmp TEGRA186_RESET_PWM1>; 775 reset-names = "pwm"; 776 status = "disabled"; 777 #pwm-cells = <2>; 778 }; 779 780 pwm2: pwm@3290000 { 781 compatible = "nvidia,tegra186-pwm"; 782 reg = <0x0 0x3290000 0x0 0x10000>; 783 clocks = <&bpmp TEGRA186_CLK_PWM2>; 784 resets = <&bpmp TEGRA186_RESET_PWM2>; 785 reset-names = "pwm"; 786 status = "disabled"; 787 #pwm-cells = <2>; 788 }; 789 790 pwm3: pwm@32a0000 { 791 compatible = "nvidia,tegra186-pwm"; 792 reg = <0x0 0x32a0000 0x0 0x10000>; 793 clocks = <&bpmp TEGRA186_CLK_PWM3>; 794 resets = <&bpmp TEGRA186_RESET_PWM3>; 795 reset-names = "pwm"; 796 status = "disabled"; 797 #pwm-cells = <2>; 798 }; 799 800 pwm5: pwm@32c0000 { 801 compatible = "nvidia,tegra186-pwm"; 802 reg = <0x0 0x32c0000 0x0 0x10000>; 803 clocks = <&bpmp TEGRA186_CLK_PWM5>; 804 resets = <&bpmp TEGRA186_RESET_PWM5>; 805 reset-names = "pwm"; 806 status = "disabled"; 807 #pwm-cells = <2>; 808 }; 809 810 pwm6: pwm@32d0000 { 811 compatible = "nvidia,tegra186-pwm"; 812 reg = <0x0 0x32d0000 0x0 0x10000>; 813 clocks = <&bpmp TEGRA186_CLK_PWM6>; 814 resets = <&bpmp TEGRA186_RESET_PWM6>; 815 reset-names = "pwm"; 816 status = "disabled"; 817 #pwm-cells = <2>; 818 }; 819 820 pwm7: pwm@32e0000 { 821 compatible = "nvidia,tegra186-pwm"; 822 reg = <0x0 0x32e0000 0x0 0x10000>; 823 clocks = <&bpmp TEGRA186_CLK_PWM7>; 824 resets = <&bpmp TEGRA186_RESET_PWM7>; 825 reset-names = "pwm"; 826 status = "disabled"; 827 #pwm-cells = <2>; 828 }; 829 830 pwm8: pwm@32f0000 { 831 compatible = "nvidia,tegra186-pwm"; 832 reg = <0x0 0x32f0000 0x0 0x10000>; 833 clocks = <&bpmp TEGRA186_CLK_PWM8>; 834 resets = <&bpmp TEGRA186_RESET_PWM8>; 835 reset-names = "pwm"; 836 status = "disabled"; 837 #pwm-cells = <2>; 838 }; 839 840 sdmmc1: mmc@3400000 { 841 compatible = "nvidia,tegra186-sdhci"; 842 reg = <0x0 0x03400000 0x0 0x10000>; 843 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 845 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 846 clock-names = "sdhci", "tmclk"; 847 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 848 reset-names = "sdhci"; 849 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 850 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 851 interconnect-names = "dma-mem", "write"; 852 iommus = <&smmu TEGRA186_SID_SDMMC1>; 853 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 854 pinctrl-0 = <&sdmmc1_3v3>; 855 pinctrl-1 = <&sdmmc1_1v8>; 856 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 857 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 858 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 859 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 860 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 861 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 862 nvidia,default-tap = <0x5>; 863 nvidia,default-trim = <0xb>; 864 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 865 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 866 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 867 status = "disabled"; 868 }; 869 870 sdmmc2: mmc@3420000 { 871 compatible = "nvidia,tegra186-sdhci"; 872 reg = <0x0 0x03420000 0x0 0x10000>; 873 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 875 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 876 clock-names = "sdhci", "tmclk"; 877 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 878 reset-names = "sdhci"; 879 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 880 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 881 interconnect-names = "dma-mem", "write"; 882 iommus = <&smmu TEGRA186_SID_SDMMC2>; 883 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 884 pinctrl-0 = <&sdmmc2_3v3>; 885 pinctrl-1 = <&sdmmc2_1v8>; 886 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 887 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 888 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 889 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 890 nvidia,default-tap = <0x5>; 891 nvidia,default-trim = <0xb>; 892 status = "disabled"; 893 }; 894 895 sdmmc3: mmc@3440000 { 896 compatible = "nvidia,tegra186-sdhci"; 897 reg = <0x0 0x03440000 0x0 0x10000>; 898 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 900 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 901 clock-names = "sdhci", "tmclk"; 902 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 903 reset-names = "sdhci"; 904 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 905 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 906 interconnect-names = "dma-mem", "write"; 907 iommus = <&smmu TEGRA186_SID_SDMMC3>; 908 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 909 pinctrl-0 = <&sdmmc3_3v3>; 910 pinctrl-1 = <&sdmmc3_1v8>; 911 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 912 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 913 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 914 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 915 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 916 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 917 nvidia,default-tap = <0x5>; 918 nvidia,default-trim = <0xb>; 919 status = "disabled"; 920 }; 921 922 sdmmc4: mmc@3460000 { 923 compatible = "nvidia,tegra186-sdhci"; 924 reg = <0x0 0x03460000 0x0 0x10000>; 925 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 927 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 928 clock-names = "sdhci", "tmclk"; 929 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 930 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 931 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 932 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 933 reset-names = "sdhci"; 934 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 935 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 936 interconnect-names = "dma-mem", "write"; 937 iommus = <&smmu TEGRA186_SID_SDMMC4>; 938 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 939 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 940 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 941 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 942 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 943 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 944 nvidia,default-tap = <0x9>; 945 nvidia,default-trim = <0x5>; 946 nvidia,dqs-trim = <63>; 947 mmc-hs400-1_8v; 948 supports-cqe; 949 status = "disabled"; 950 }; 951 952 sata@3507000 { 953 compatible = "nvidia,tegra186-ahci"; 954 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 955 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 956 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 957 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 958 959 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 960 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 961 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 962 interconnect-names = "dma-mem", "write"; 963 iommus = <&smmu TEGRA186_SID_SATA>; 964 965 clocks = <&bpmp TEGRA186_CLK_SATA>, 966 <&bpmp TEGRA186_CLK_SATA_OOB>; 967 clock-names = "sata", "sata-oob"; 968 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 969 <&bpmp TEGRA186_CLK_SATA_OOB>; 970 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 971 <&bpmp TEGRA186_CLK_PLLP>; 972 assigned-clock-rates = <102000000>, 973 <204000000>; 974 resets = <&bpmp TEGRA186_RESET_SATA>, 975 <&bpmp TEGRA186_RESET_SATACOLD>; 976 reset-names = "sata", "sata-cold"; 977 status = "disabled"; 978 }; 979 980 hda@3510000 { 981 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 982 reg = <0x0 0x03510000 0x0 0x10000>; 983 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&bpmp TEGRA186_CLK_HDA>, 985 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 986 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 987 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 988 resets = <&bpmp TEGRA186_RESET_HDA>, 989 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 990 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 991 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 992 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 993 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 994 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 995 interconnect-names = "dma-mem", "write"; 996 iommus = <&smmu TEGRA186_SID_HDA>; 997 status = "disabled"; 998 }; 999 1000 padctl: padctl@3520000 { 1001 compatible = "nvidia,tegra186-xusb-padctl"; 1002 reg = <0x0 0x03520000 0x0 0x1000>, 1003 <0x0 0x03540000 0x0 0x1000>; 1004 reg-names = "padctl", "ao"; 1005 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1006 1007 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 1008 reset-names = "padctl"; 1009 1010 status = "disabled"; 1011 1012 pads { 1013 usb2 { 1014 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 1015 clock-names = "trk"; 1016 status = "disabled"; 1017 1018 lanes { 1019 usb2-0 { 1020 status = "disabled"; 1021 #phy-cells = <0>; 1022 }; 1023 1024 usb2-1 { 1025 status = "disabled"; 1026 #phy-cells = <0>; 1027 }; 1028 1029 usb2-2 { 1030 status = "disabled"; 1031 #phy-cells = <0>; 1032 }; 1033 }; 1034 }; 1035 1036 hsic { 1037 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 1038 clock-names = "trk"; 1039 status = "disabled"; 1040 1041 lanes { 1042 hsic-0 { 1043 status = "disabled"; 1044 #phy-cells = <0>; 1045 }; 1046 }; 1047 }; 1048 1049 usb3 { 1050 status = "disabled"; 1051 1052 lanes { 1053 usb3-0 { 1054 status = "disabled"; 1055 #phy-cells = <0>; 1056 }; 1057 1058 usb3-1 { 1059 status = "disabled"; 1060 #phy-cells = <0>; 1061 }; 1062 1063 usb3-2 { 1064 status = "disabled"; 1065 #phy-cells = <0>; 1066 }; 1067 }; 1068 }; 1069 }; 1070 1071 ports { 1072 usb2-0 { 1073 status = "disabled"; 1074 }; 1075 1076 usb2-1 { 1077 status = "disabled"; 1078 }; 1079 1080 usb2-2 { 1081 status = "disabled"; 1082 }; 1083 1084 hsic-0 { 1085 status = "disabled"; 1086 }; 1087 1088 usb3-0 { 1089 status = "disabled"; 1090 }; 1091 1092 usb3-1 { 1093 status = "disabled"; 1094 }; 1095 1096 usb3-2 { 1097 status = "disabled"; 1098 }; 1099 }; 1100 }; 1101 1102 usb@3530000 { 1103 compatible = "nvidia,tegra186-xusb"; 1104 reg = <0x0 0x03530000 0x0 0x8000>, 1105 <0x0 0x03538000 0x0 0x1000>; 1106 reg-names = "hcd", "fpci"; 1107 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1109 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 1110 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 1111 <&bpmp TEGRA186_CLK_XUSB_SS>, 1112 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1113 <&bpmp TEGRA186_CLK_CLK_M>, 1114 <&bpmp TEGRA186_CLK_XUSB_FS>, 1115 <&bpmp TEGRA186_CLK_PLLU>, 1116 <&bpmp TEGRA186_CLK_CLK_M>, 1117 <&bpmp TEGRA186_CLK_PLLE>; 1118 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 1119 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 1120 "pll_u_480m", "clk_m", "pll_e"; 1121 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 1122 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1123 power-domain-names = "xusb_host", "xusb_ss"; 1124 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1125 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1126 interconnect-names = "dma-mem", "write"; 1127 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 status = "disabled"; 1131 1132 nvidia,xusb-padctl = <&padctl>; 1133 }; 1134 1135 usb@3550000 { 1136 compatible = "nvidia,tegra186-xudc"; 1137 reg = <0x0 0x03550000 0x0 0x8000>, 1138 <0x0 0x03558000 0x0 0x1000>; 1139 reg-names = "base", "fpci"; 1140 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1141 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1142 <&bpmp TEGRA186_CLK_XUSB_SS>, 1143 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1144 <&bpmp TEGRA186_CLK_XUSB_FS>; 1145 clock-names = "dev", "ss", "ss_src", "fs_src"; 1146 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1147 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1148 interconnect-names = "dma-mem", "write"; 1149 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1150 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1151 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1152 power-domain-names = "dev", "ss"; 1153 nvidia,xusb-padctl = <&padctl>; 1154 status = "disabled"; 1155 }; 1156 1157 fuse@3820000 { 1158 compatible = "nvidia,tegra186-efuse"; 1159 reg = <0x0 0x03820000 0x0 0x10000>; 1160 clocks = <&bpmp TEGRA186_CLK_FUSE>; 1161 clock-names = "fuse"; 1162 }; 1163 1164 gic: interrupt-controller@3881000 { 1165 compatible = "arm,gic-400"; 1166 #interrupt-cells = <3>; 1167 interrupt-controller; 1168 reg = <0x0 0x03881000 0x0 0x1000>, 1169 <0x0 0x03882000 0x0 0x2000>, 1170 <0x0 0x03884000 0x0 0x2000>, 1171 <0x0 0x03886000 0x0 0x2000>; 1172 interrupts = <GIC_PPI 9 1173 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1174 interrupt-parent = <&gic>; 1175 }; 1176 1177 cec@3960000 { 1178 compatible = "nvidia,tegra186-cec"; 1179 reg = <0x0 0x03960000 0x0 0x10000>; 1180 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1181 clocks = <&bpmp TEGRA186_CLK_CEC>; 1182 clock-names = "cec"; 1183 status = "disabled"; 1184 }; 1185 1186 hsp_top0: hsp@3c00000 { 1187 compatible = "nvidia,tegra186-hsp"; 1188 reg = <0x0 0x03c00000 0x0 0xa0000>; 1189 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1190 interrupt-names = "doorbell"; 1191 #mbox-cells = <2>; 1192 status = "disabled"; 1193 }; 1194 1195 gen2_i2c: i2c@c240000 { 1196 compatible = "nvidia,tegra186-i2c"; 1197 reg = <0x0 0x0c240000 0x0 0x10000>; 1198 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 clocks = <&bpmp TEGRA186_CLK_I2C2>; 1202 clock-names = "div-clk"; 1203 resets = <&bpmp TEGRA186_RESET_I2C2>; 1204 reset-names = "i2c"; 1205 dmas = <&gpcdma 22>, <&gpcdma 22>; 1206 dma-names = "rx", "tx"; 1207 status = "disabled"; 1208 }; 1209 1210 gen8_i2c: i2c@c250000 { 1211 compatible = "nvidia,tegra186-i2c"; 1212 reg = <0x0 0x0c250000 0x0 0x10000>; 1213 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 clocks = <&bpmp TEGRA186_CLK_I2C8>; 1217 clock-names = "div-clk"; 1218 resets = <&bpmp TEGRA186_RESET_I2C8>; 1219 reset-names = "i2c"; 1220 dmas = <&gpcdma 0>, <&gpcdma 0>; 1221 dma-names = "rx", "tx"; 1222 status = "disabled"; 1223 }; 1224 1225 uartc: serial@c280000 { 1226 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1227 reg = <0x0 0x0c280000 0x0 0x40>; 1228 reg-shift = <2>; 1229 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1230 clocks = <&bpmp TEGRA186_CLK_UARTC>; 1231 resets = <&bpmp TEGRA186_RESET_UARTC>; 1232 status = "disabled"; 1233 }; 1234 1235 uartg: serial@c290000 { 1236 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1237 reg = <0x0 0x0c290000 0x0 0x40>; 1238 reg-shift = <2>; 1239 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&bpmp TEGRA186_CLK_UARTG>; 1241 resets = <&bpmp TEGRA186_RESET_UARTG>; 1242 status = "disabled"; 1243 }; 1244 1245 rtc: rtc@c2a0000 { 1246 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1247 reg = <0 0x0c2a0000 0 0x10000>; 1248 interrupt-parent = <&pmc>; 1249 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1251 clock-names = "rtc"; 1252 status = "disabled"; 1253 }; 1254 1255 gpio_aon: gpio@c2f0000 { 1256 compatible = "nvidia,tegra186-gpio-aon"; 1257 reg-names = "security", "gpio"; 1258 reg = <0x0 0xc2f0000 0x0 0x1000>, 1259 <0x0 0xc2f1000 0x0 0x1000>; 1260 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1261 gpio-controller; 1262 #gpio-cells = <2>; 1263 interrupt-controller; 1264 #interrupt-cells = <2>; 1265 }; 1266 1267 pwm4: pwm@c340000 { 1268 compatible = "nvidia,tegra186-pwm"; 1269 reg = <0x0 0xc340000 0x0 0x10000>; 1270 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1271 resets = <&bpmp TEGRA186_RESET_PWM4>; 1272 reset-names = "pwm"; 1273 status = "disabled"; 1274 #pwm-cells = <2>; 1275 }; 1276 1277 pmc: pmc@c360000 { 1278 compatible = "nvidia,tegra186-pmc"; 1279 reg = <0 0x0c360000 0 0x10000>, 1280 <0 0x0c370000 0 0x10000>, 1281 <0 0x0c380000 0 0x10000>, 1282 <0 0x0c390000 0 0x10000>; 1283 reg-names = "pmc", "wake", "aotag", "scratch"; 1284 1285 #interrupt-cells = <2>; 1286 interrupt-controller; 1287 1288 sdmmc1_1v8: sdmmc1-1v8 { 1289 pins = "sdmmc1-hv"; 1290 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1291 }; 1292 1293 sdmmc1_3v3: sdmmc1-3v3 { 1294 pins = "sdmmc1-hv"; 1295 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1296 }; 1297 1298 sdmmc2_1v8: sdmmc2-1v8 { 1299 pins = "sdmmc2-hv"; 1300 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1301 }; 1302 1303 sdmmc2_3v3: sdmmc2-3v3 { 1304 pins = "sdmmc2-hv"; 1305 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1306 }; 1307 1308 sdmmc3_1v8: sdmmc3-1v8 { 1309 pins = "sdmmc3-hv"; 1310 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1311 }; 1312 1313 sdmmc3_3v3: sdmmc3-3v3 { 1314 pins = "sdmmc3-hv"; 1315 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1316 }; 1317 }; 1318 1319 ccplex@e000000 { 1320 compatible = "nvidia,tegra186-ccplex-cluster"; 1321 reg = <0x0 0x0e000000 0x0 0x400000>; 1322 1323 nvidia,bpmp = <&bpmp>; 1324 }; 1325 1326 pcie@10003000 { 1327 compatible = "nvidia,tegra186-pcie"; 1328 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1329 device_type = "pci"; 1330 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1331 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1332 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1333 reg-names = "pads", "afi", "cs"; 1334 1335 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1336 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1337 interrupt-names = "intr", "msi"; 1338 1339 #interrupt-cells = <1>; 1340 interrupt-map-mask = <0 0 0 0>; 1341 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1342 1343 bus-range = <0x00 0xff>; 1344 #address-cells = <3>; 1345 #size-cells = <2>; 1346 1347 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1348 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1349 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1350 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1351 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1352 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1353 1354 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1355 <&bpmp TEGRA186_CLK_AFI>, 1356 <&bpmp TEGRA186_CLK_PLLE>; 1357 clock-names = "pex", "afi", "pll_e"; 1358 1359 resets = <&bpmp TEGRA186_RESET_PCIE>, 1360 <&bpmp TEGRA186_RESET_AFI>, 1361 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1362 reset-names = "pex", "afi", "pcie_x"; 1363 1364 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1365 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1366 interconnect-names = "dma-mem", "write"; 1367 1368 iommus = <&smmu TEGRA186_SID_AFI>; 1369 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1370 iommu-map-mask = <0x0>; 1371 1372 status = "disabled"; 1373 1374 pci@1,0 { 1375 device_type = "pci"; 1376 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1377 reg = <0x000800 0 0 0 0>; 1378 status = "disabled"; 1379 1380 #address-cells = <3>; 1381 #size-cells = <2>; 1382 ranges; 1383 1384 nvidia,num-lanes = <2>; 1385 }; 1386 1387 pci@2,0 { 1388 device_type = "pci"; 1389 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1390 reg = <0x001000 0 0 0 0>; 1391 status = "disabled"; 1392 1393 #address-cells = <3>; 1394 #size-cells = <2>; 1395 ranges; 1396 1397 nvidia,num-lanes = <1>; 1398 }; 1399 1400 pci@3,0 { 1401 device_type = "pci"; 1402 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1403 reg = <0x001800 0 0 0 0>; 1404 status = "disabled"; 1405 1406 #address-cells = <3>; 1407 #size-cells = <2>; 1408 ranges; 1409 1410 nvidia,num-lanes = <1>; 1411 }; 1412 }; 1413 1414 smmu: iommu@12000000 { 1415 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1416 reg = <0 0x12000000 0 0x800000>; 1417 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1482 stream-match-mask = <0x7f80>; 1483 #global-interrupts = <1>; 1484 #iommu-cells = <1>; 1485 1486 nvidia,memory-controller = <&mc>; 1487 }; 1488 1489 host1x@13e00000 { 1490 compatible = "nvidia,tegra186-host1x"; 1491 reg = <0x0 0x13e00000 0x0 0x10000>, 1492 <0x0 0x13e10000 0x0 0x10000>; 1493 reg-names = "hypervisor", "vm"; 1494 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1496 interrupt-names = "syncpt", "host1x"; 1497 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1498 clock-names = "host1x"; 1499 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1500 reset-names = "host1x"; 1501 1502 #address-cells = <1>; 1503 #size-cells = <1>; 1504 1505 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1506 1507 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1508 interconnect-names = "dma-mem"; 1509 1510 iommus = <&smmu TEGRA186_SID_HOST1X>; 1511 1512 /* Context isolation domains */ 1513 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1514 <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1515 <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1516 <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1517 <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1518 <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1519 <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1520 <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1521 1522 dpaux1: dpaux@15040000 { 1523 compatible = "nvidia,tegra186-dpaux"; 1524 reg = <0x15040000 0x10000>; 1525 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1526 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1527 <&bpmp TEGRA186_CLK_PLLDP>; 1528 clock-names = "dpaux", "parent"; 1529 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1530 reset-names = "dpaux"; 1531 status = "disabled"; 1532 1533 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1534 1535 state_dpaux1_aux: pinmux-aux { 1536 groups = "dpaux-io"; 1537 function = "aux"; 1538 }; 1539 1540 state_dpaux1_i2c: pinmux-i2c { 1541 groups = "dpaux-io"; 1542 function = "i2c"; 1543 }; 1544 1545 state_dpaux1_off: pinmux-off { 1546 groups = "dpaux-io"; 1547 function = "off"; 1548 }; 1549 1550 i2c-bus { 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 }; 1554 }; 1555 1556 display-hub@15200000 { 1557 compatible = "nvidia,tegra186-display"; 1558 reg = <0x15200000 0x00040000>; 1559 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1560 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1561 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1562 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1563 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1564 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1565 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1566 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1567 "wgrp3", "wgrp4", "wgrp5"; 1568 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1569 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1570 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1571 clock-names = "disp", "dsc", "hub"; 1572 status = "disabled"; 1573 1574 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1575 1576 #address-cells = <1>; 1577 #size-cells = <1>; 1578 1579 ranges = <0x15200000 0x15200000 0x40000>; 1580 1581 display@15200000 { 1582 compatible = "nvidia,tegra186-dc"; 1583 reg = <0x15200000 0x10000>; 1584 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1585 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1586 clock-names = "dc"; 1587 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1588 reset-names = "dc"; 1589 1590 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1591 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1592 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1593 interconnect-names = "dma-mem", "read-1"; 1594 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1595 1596 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1597 nvidia,head = <0>; 1598 }; 1599 1600 display@15210000 { 1601 compatible = "nvidia,tegra186-dc"; 1602 reg = <0x15210000 0x10000>; 1603 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1604 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1605 clock-names = "dc"; 1606 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1607 reset-names = "dc"; 1608 1609 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1610 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1611 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1612 interconnect-names = "dma-mem", "read-1"; 1613 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1614 1615 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1616 nvidia,head = <1>; 1617 }; 1618 1619 display@15220000 { 1620 compatible = "nvidia,tegra186-dc"; 1621 reg = <0x15220000 0x10000>; 1622 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1624 clock-names = "dc"; 1625 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1626 reset-names = "dc"; 1627 1628 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1629 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1630 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1631 interconnect-names = "dma-mem", "read-1"; 1632 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1633 1634 nvidia,outputs = <&sor0 &sor1>; 1635 nvidia,head = <2>; 1636 }; 1637 }; 1638 1639 dsia: dsi@15300000 { 1640 compatible = "nvidia,tegra186-dsi"; 1641 reg = <0x15300000 0x10000>; 1642 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1643 clocks = <&bpmp TEGRA186_CLK_DSI>, 1644 <&bpmp TEGRA186_CLK_DSIA_LP>, 1645 <&bpmp TEGRA186_CLK_PLLD>; 1646 clock-names = "dsi", "lp", "parent"; 1647 resets = <&bpmp TEGRA186_RESET_DSI>; 1648 reset-names = "dsi"; 1649 status = "disabled"; 1650 1651 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1652 }; 1653 1654 vic@15340000 { 1655 compatible = "nvidia,tegra186-vic"; 1656 reg = <0x15340000 0x40000>; 1657 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1658 clocks = <&bpmp TEGRA186_CLK_VIC>; 1659 clock-names = "vic"; 1660 resets = <&bpmp TEGRA186_RESET_VIC>; 1661 reset-names = "vic"; 1662 1663 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1664 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1665 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1666 interconnect-names = "dma-mem", "write"; 1667 iommus = <&smmu TEGRA186_SID_VIC>; 1668 }; 1669 1670 nvjpg@15380000 { 1671 compatible = "nvidia,tegra186-nvjpg"; 1672 reg = <0x15380000 0x40000>; 1673 clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1674 clock-names = "nvjpg"; 1675 resets = <&bpmp TEGRA186_RESET_NVJPG>; 1676 reset-names = "nvjpg"; 1677 1678 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1679 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1680 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1681 interconnect-names = "dma-mem", "write"; 1682 iommus = <&smmu TEGRA186_SID_NVJPG>; 1683 }; 1684 1685 dsib: dsi@15400000 { 1686 compatible = "nvidia,tegra186-dsi"; 1687 reg = <0x15400000 0x10000>; 1688 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1689 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1690 <&bpmp TEGRA186_CLK_DSIB_LP>, 1691 <&bpmp TEGRA186_CLK_PLLD>; 1692 clock-names = "dsi", "lp", "parent"; 1693 resets = <&bpmp TEGRA186_RESET_DSIB>; 1694 reset-names = "dsi"; 1695 status = "disabled"; 1696 1697 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1698 }; 1699 1700 nvdec@15480000 { 1701 compatible = "nvidia,tegra186-nvdec"; 1702 reg = <0x15480000 0x40000>; 1703 clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1704 clock-names = "nvdec"; 1705 resets = <&bpmp TEGRA186_RESET_NVDEC>; 1706 reset-names = "nvdec"; 1707 1708 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1709 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1710 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1711 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1712 interconnect-names = "dma-mem", "read-1", "write"; 1713 iommus = <&smmu TEGRA186_SID_NVDEC>; 1714 }; 1715 1716 nvenc@154c0000 { 1717 compatible = "nvidia,tegra186-nvenc"; 1718 reg = <0x154c0000 0x40000>; 1719 clocks = <&bpmp TEGRA186_CLK_NVENC>; 1720 clock-names = "nvenc"; 1721 resets = <&bpmp TEGRA186_RESET_NVENC>; 1722 reset-names = "nvenc"; 1723 1724 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1725 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1726 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1727 interconnect-names = "dma-mem", "write"; 1728 iommus = <&smmu TEGRA186_SID_NVENC>; 1729 }; 1730 1731 sor0: sor@15540000 { 1732 compatible = "nvidia,tegra186-sor"; 1733 reg = <0x15540000 0x10000>; 1734 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1735 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1736 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1737 <&bpmp TEGRA186_CLK_PLLD2>, 1738 <&bpmp TEGRA186_CLK_PLLDP>, 1739 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1740 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1741 clock-names = "sor", "out", "parent", "dp", "safe", 1742 "pad"; 1743 resets = <&bpmp TEGRA186_RESET_SOR0>; 1744 reset-names = "sor"; 1745 pinctrl-0 = <&state_dpaux_aux>; 1746 pinctrl-1 = <&state_dpaux_i2c>; 1747 pinctrl-2 = <&state_dpaux_off>; 1748 pinctrl-names = "aux", "i2c", "off"; 1749 status = "disabled"; 1750 1751 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1752 nvidia,interface = <0>; 1753 }; 1754 1755 sor1: sor@15580000 { 1756 compatible = "nvidia,tegra186-sor"; 1757 reg = <0x15580000 0x10000>; 1758 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1759 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1760 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1761 <&bpmp TEGRA186_CLK_PLLD3>, 1762 <&bpmp TEGRA186_CLK_PLLDP>, 1763 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1764 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1765 clock-names = "sor", "out", "parent", "dp", "safe", 1766 "pad"; 1767 resets = <&bpmp TEGRA186_RESET_SOR1>; 1768 reset-names = "sor"; 1769 pinctrl-0 = <&state_dpaux1_aux>; 1770 pinctrl-1 = <&state_dpaux1_i2c>; 1771 pinctrl-2 = <&state_dpaux1_off>; 1772 pinctrl-names = "aux", "i2c", "off"; 1773 status = "disabled"; 1774 1775 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1776 nvidia,interface = <1>; 1777 }; 1778 1779 dpaux: dpaux@155c0000 { 1780 compatible = "nvidia,tegra186-dpaux"; 1781 reg = <0x155c0000 0x10000>; 1782 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1783 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1784 <&bpmp TEGRA186_CLK_PLLDP>; 1785 clock-names = "dpaux", "parent"; 1786 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1787 reset-names = "dpaux"; 1788 status = "disabled"; 1789 1790 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1791 1792 state_dpaux_aux: pinmux-aux { 1793 groups = "dpaux-io"; 1794 function = "aux"; 1795 }; 1796 1797 state_dpaux_i2c: pinmux-i2c { 1798 groups = "dpaux-io"; 1799 function = "i2c"; 1800 }; 1801 1802 state_dpaux_off: pinmux-off { 1803 groups = "dpaux-io"; 1804 function = "off"; 1805 }; 1806 1807 i2c-bus { 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 }; 1811 }; 1812 1813 padctl@15880000 { 1814 compatible = "nvidia,tegra186-dsi-padctl"; 1815 reg = <0x15880000 0x10000>; 1816 resets = <&bpmp TEGRA186_RESET_DSI>; 1817 reset-names = "dsi"; 1818 status = "disabled"; 1819 }; 1820 1821 dsic: dsi@15900000 { 1822 compatible = "nvidia,tegra186-dsi"; 1823 reg = <0x15900000 0x10000>; 1824 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1825 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1826 <&bpmp TEGRA186_CLK_DSIC_LP>, 1827 <&bpmp TEGRA186_CLK_PLLD>; 1828 clock-names = "dsi", "lp", "parent"; 1829 resets = <&bpmp TEGRA186_RESET_DSIC>; 1830 reset-names = "dsi"; 1831 status = "disabled"; 1832 1833 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1834 }; 1835 1836 dsid: dsi@15940000 { 1837 compatible = "nvidia,tegra186-dsi"; 1838 reg = <0x15940000 0x10000>; 1839 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1840 clocks = <&bpmp TEGRA186_CLK_DSID>, 1841 <&bpmp TEGRA186_CLK_DSID_LP>, 1842 <&bpmp TEGRA186_CLK_PLLD>; 1843 clock-names = "dsi", "lp", "parent"; 1844 resets = <&bpmp TEGRA186_RESET_DSID>; 1845 reset-names = "dsi"; 1846 status = "disabled"; 1847 1848 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1849 }; 1850 }; 1851 1852 gpu@17000000 { 1853 compatible = "nvidia,gp10b"; 1854 reg = <0x0 0x17000000 0x0 0x1000000>, 1855 <0x0 0x18000000 0x0 0x1000000>; 1856 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1858 interrupt-names = "stall", "nonstall"; 1859 1860 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1861 <&bpmp TEGRA186_CLK_GPU>; 1862 clock-names = "gpu", "pwr"; 1863 resets = <&bpmp TEGRA186_RESET_GPU>; 1864 reset-names = "gpu"; 1865 status = "disabled"; 1866 1867 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1868 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1869 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1870 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1871 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1872 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1873 }; 1874 1875 sram@30000000 { 1876 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1877 reg = <0x0 0x30000000 0x0 0x50000>; 1878 #address-cells = <1>; 1879 #size-cells = <1>; 1880 ranges = <0x0 0x0 0x30000000 0x50000>; 1881 no-memory-wc; 1882 1883 cpu_bpmp_tx: sram@4e000 { 1884 reg = <0x4e000 0x1000>; 1885 label = "cpu-bpmp-tx"; 1886 pool; 1887 }; 1888 1889 cpu_bpmp_rx: sram@4f000 { 1890 reg = <0x4f000 0x1000>; 1891 label = "cpu-bpmp-rx"; 1892 pool; 1893 }; 1894 }; 1895 1896 bpmp: bpmp { 1897 compatible = "nvidia,tegra186-bpmp"; 1898 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1899 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1900 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1901 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1902 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1903 iommus = <&smmu TEGRA186_SID_BPMP>; 1904 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1905 TEGRA_HSP_DB_MASTER_BPMP>; 1906 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1907 #clock-cells = <1>; 1908 #reset-cells = <1>; 1909 #power-domain-cells = <1>; 1910 1911 bpmp_i2c: i2c { 1912 compatible = "nvidia,tegra186-bpmp-i2c"; 1913 nvidia,bpmp-bus-id = <5>; 1914 #address-cells = <1>; 1915 #size-cells = <0>; 1916 status = "disabled"; 1917 }; 1918 1919 bpmp_thermal: thermal { 1920 compatible = "nvidia,tegra186-bpmp-thermal"; 1921 #thermal-sensor-cells = <1>; 1922 }; 1923 }; 1924 1925 cpus { 1926 #address-cells = <1>; 1927 #size-cells = <0>; 1928 1929 denver_0: cpu@0 { 1930 compatible = "nvidia,tegra186-denver"; 1931 device_type = "cpu"; 1932 i-cache-size = <0x20000>; 1933 i-cache-line-size = <64>; 1934 i-cache-sets = <512>; 1935 d-cache-size = <0x10000>; 1936 d-cache-line-size = <64>; 1937 d-cache-sets = <256>; 1938 next-level-cache = <&L2_DENVER>; 1939 reg = <0x000>; 1940 }; 1941 1942 denver_1: cpu@1 { 1943 compatible = "nvidia,tegra186-denver"; 1944 device_type = "cpu"; 1945 i-cache-size = <0x20000>; 1946 i-cache-line-size = <64>; 1947 i-cache-sets = <512>; 1948 d-cache-size = <0x10000>; 1949 d-cache-line-size = <64>; 1950 d-cache-sets = <256>; 1951 next-level-cache = <&L2_DENVER>; 1952 reg = <0x001>; 1953 }; 1954 1955 ca57_0: cpu@2 { 1956 compatible = "arm,cortex-a57"; 1957 device_type = "cpu"; 1958 i-cache-size = <0xC000>; 1959 i-cache-line-size = <64>; 1960 i-cache-sets = <256>; 1961 d-cache-size = <0x8000>; 1962 d-cache-line-size = <64>; 1963 d-cache-sets = <256>; 1964 next-level-cache = <&L2_A57>; 1965 reg = <0x100>; 1966 }; 1967 1968 ca57_1: cpu@3 { 1969 compatible = "arm,cortex-a57"; 1970 device_type = "cpu"; 1971 i-cache-size = <0xC000>; 1972 i-cache-line-size = <64>; 1973 i-cache-sets = <256>; 1974 d-cache-size = <0x8000>; 1975 d-cache-line-size = <64>; 1976 d-cache-sets = <256>; 1977 next-level-cache = <&L2_A57>; 1978 reg = <0x101>; 1979 }; 1980 1981 ca57_2: cpu@4 { 1982 compatible = "arm,cortex-a57"; 1983 device_type = "cpu"; 1984 i-cache-size = <0xC000>; 1985 i-cache-line-size = <64>; 1986 i-cache-sets = <256>; 1987 d-cache-size = <0x8000>; 1988 d-cache-line-size = <64>; 1989 d-cache-sets = <256>; 1990 next-level-cache = <&L2_A57>; 1991 reg = <0x102>; 1992 }; 1993 1994 ca57_3: cpu@5 { 1995 compatible = "arm,cortex-a57"; 1996 device_type = "cpu"; 1997 i-cache-size = <0xC000>; 1998 i-cache-line-size = <64>; 1999 i-cache-sets = <256>; 2000 d-cache-size = <0x8000>; 2001 d-cache-line-size = <64>; 2002 d-cache-sets = <256>; 2003 next-level-cache = <&L2_A57>; 2004 reg = <0x103>; 2005 }; 2006 2007 L2_DENVER: l2-cache0 { 2008 compatible = "cache"; 2009 cache-unified; 2010 cache-level = <2>; 2011 cache-size = <0x200000>; 2012 cache-line-size = <64>; 2013 cache-sets = <2048>; 2014 }; 2015 2016 L2_A57: l2-cache1 { 2017 compatible = "cache"; 2018 cache-unified; 2019 cache-level = <2>; 2020 cache-size = <0x200000>; 2021 cache-line-size = <64>; 2022 cache-sets = <2048>; 2023 }; 2024 }; 2025 2026 pmu-a57 { 2027 compatible = "arm,cortex-a57-pmu"; 2028 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 2032 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 2033 }; 2034 2035 pmu-denver { 2036 compatible = "nvidia,denver-pmu"; 2037 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2039 interrupt-affinity = <&denver_0 &denver_1>; 2040 }; 2041 2042 sound { 2043 status = "disabled"; 2044 2045 clocks = <&bpmp TEGRA186_CLK_PLLA>, 2046 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2047 clock-names = "pll_a", "plla_out0"; 2048 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2049 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2050 <&bpmp TEGRA186_CLK_AUD_MCLK>; 2051 assigned-clock-parents = <0>, 2052 <&bpmp TEGRA186_CLK_PLLA>, 2053 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2054 /* 2055 * PLLA supports dynamic ramp. Below initial rate is chosen 2056 * for this to work and oscillate between base rates required 2057 * for 8x and 11.025x sample rate streams. 2058 */ 2059 assigned-clock-rates = <258000000>; 2060 2061 iommus = <&smmu TEGRA186_SID_APE>; 2062 }; 2063 2064 thermal-zones { 2065 /* Cortex-A57 cluster */ 2066 cpu-thermal { 2067 polling-delay = <0>; 2068 polling-delay-passive = <1000>; 2069 2070 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 2071 2072 trips { 2073 critical { 2074 temperature = <101000>; 2075 hysteresis = <0>; 2076 type = "critical"; 2077 }; 2078 }; 2079 2080 cooling-maps { 2081 }; 2082 }; 2083 2084 /* Denver cluster */ 2085 aux-thermal { 2086 polling-delay = <0>; 2087 polling-delay-passive = <1000>; 2088 2089 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 2090 2091 trips { 2092 critical { 2093 temperature = <101000>; 2094 hysteresis = <0>; 2095 type = "critical"; 2096 }; 2097 }; 2098 2099 cooling-maps { 2100 }; 2101 }; 2102 2103 gpu-thermal { 2104 polling-delay = <0>; 2105 polling-delay-passive = <1000>; 2106 2107 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 2108 2109 trips { 2110 critical { 2111 temperature = <101000>; 2112 hysteresis = <0>; 2113 type = "critical"; 2114 }; 2115 }; 2116 2117 cooling-maps { 2118 }; 2119 }; 2120 2121 pll-thermal { 2122 polling-delay = <0>; 2123 polling-delay-passive = <1000>; 2124 2125 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 2126 2127 trips { 2128 critical { 2129 temperature = <101000>; 2130 hysteresis = <0>; 2131 type = "critical"; 2132 }; 2133 }; 2134 2135 cooling-maps { 2136 }; 2137 }; 2138 2139 ao-thermal { 2140 polling-delay = <0>; 2141 polling-delay-passive = <1000>; 2142 2143 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 2144 2145 trips { 2146 critical { 2147 temperature = <101000>; 2148 hysteresis = <0>; 2149 type = "critical"; 2150 }; 2151 }; 2152 2153 cooling-maps { 2154 }; 2155 }; 2156 }; 2157 2158 timer { 2159 compatible = "arm,armv8-timer"; 2160 interrupts = <GIC_PPI 13 2161 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2162 <GIC_PPI 14 2163 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2164 <GIC_PPI 11 2165 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2166 <GIC_PPI 10 2167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2168 interrupt-parent = <&gic>; 2169 always-on; 2170 }; 2171}; 2172