1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010 Samsung Electronics 4 * Minkyu Kang <mk7.kang@samsung.com> 5 */ 6 7 #ifndef _EXYNOS4_CPU_H 8 #define _EXYNOS4_CPU_H 9 10 #define DEVICE_NOT_AVAILABLE 0 11 12 #define EXYNOS_CPU_NAME "Exynos" 13 #define EXYNOS4_ADDR_BASE 0x10000000 14 15 /* EXYNOS4 Common*/ 16 #define EXYNOS4_I2C_SPACING 0x10000 17 18 #define EXYNOS4_GPIO_PART3_BASE 0x03860000 19 #define EXYNOS4_PRO_ID 0x10000000 20 #define EXYNOS4_SYSREG_BASE 0x10010000 21 #define EXYNOS4_POWER_BASE 0x10020000 22 #define EXYNOS4_SWRESET 0x10020400 23 #define EXYNOS4_CLOCK_BASE 0x10030000 24 #define EXYNOS4_SYSTIMER_BASE 0x10050000 25 #define EXYNOS4_WATCHDOG_BASE 0x10060000 26 #define EXYNOS4_TZPC_BASE 0x10110000 27 #define EXYNOS4_DMC_CTRL_BASE 0x10400000 28 #define EXYNOS4_MIU_BASE 0x10600000 29 #define EXYNOS4_ACE_SFR_BASE 0x10830000 30 #define EXYNOS4_GPIO_PART2_BASE 0x11000000 31 #define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */ 32 #define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */ 33 #define EXYNOS4_GPIO_PART1_BASE 0x11400000 34 #define EXYNOS4_FIMD_BASE 0x11C00000 35 #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 36 #define EXYNOS4_USBOTG_BASE 0x12480000 37 #define EXYNOS4_MMC_BASE 0x12510000 38 #define EXYNOS4_SROMC_BASE 0x12570000 39 #define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000 40 #define EXYNOS4_USBPHY_BASE 0x125B0000 41 #define EXYNOS4_UART_BASE 0x13800000 42 #define EXYNOS4_I2C_BASE 0x13860000 43 #define EXYNOS4_ADC_BASE 0x13910000 44 #define EXYNOS4_SPI_BASE 0x13920000 45 #define EXYNOS4_PWMTIMER_BASE 0x139D0000 46 #define EXYNOS4_MODEM_BASE 0x13A00000 47 #define EXYNOS4_USBPHY_CONTROL 0x10020704 48 #define EXYNOS4_I2S_BASE 0xE2100000 49 50 #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE 51 #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE 52 #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE 53 #define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE 54 #define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE 55 #define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE 56 #define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE 57 #define EXYNOS4_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE 58 59 /* EXYNOS4X12 */ 60 #define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 61 #define EXYNOS4X12_PRO_ID 0x10000000 62 #define EXYNOS4X12_SYSREG_BASE 0x10010000 63 #define EXYNOS4X12_POWER_BASE 0x10020000 64 #define EXYNOS4X12_SWRESET 0x10020400 65 #define EXYNOS4X12_USBPHY_CONTROL 0x10020704 66 #define EXYNOS4X12_CLOCK_BASE 0x10030000 67 #define EXYNOS4X12_SYSTIMER_BASE 0x10050000 68 #define EXYNOS4X12_WATCHDOG_BASE 0x10060000 69 #define EXYNOS4X12_TZPC_BASE 0x10110000 70 #define EXYNOS4X12_DMC_CTRL_BASE 0x10600000 71 #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 72 #define EXYNOS4X12_ACE_SFR_BASE 0x10830000 73 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 74 #define EXYNOS4X12_GPIO_PART2_0 0x11000000 75 #define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */ 76 #define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */ 77 #define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */ 78 #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 79 #define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */ 80 #define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */ 81 #define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */ 82 #define EXYNOS4X12_FIMD_BASE 0x11C00000 83 #define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 84 #define EXYNOS4X12_USBOTG_BASE 0x12480000 85 #define EXYNOS4X12_MMC_BASE 0x12510000 86 #define EXYNOS4X12_SROMC_BASE 0x12570000 87 #define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000 88 #define EXYNOS4X12_USBPHY_BASE 0x125B0000 89 #define EXYNOS4X12_UART_BASE 0x13800000 90 #define EXYNOS4X12_I2C_BASE 0x13860000 91 #define EXYNOS4X12_PWMTIMER_BASE 0x139D0000 92 93 #define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE 94 #define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE 95 #define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE 96 #define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE 97 #define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE 98 #define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE 99 #define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE 100 #define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE 101 #define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE 102 #define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE 103 #define EXYNOS4X12_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE 104 105 /* EXYNOS5 */ 106 #define EXYNOS5_I2C_SPACING 0x10000 107 108 #define EXYNOS5_AUDIOSS_BASE 0x03810000 109 #define EXYNOS5_GPIO_PART8_BASE 0x03860000 110 #define EXYNOS5_PRO_ID 0x10000000 111 #define EXYNOS5_CLOCK_BASE 0x10010000 112 #define EXYNOS5_POWER_BASE 0x10040000 113 #define EXYNOS5_SWRESET 0x10040400 114 #define EXYNOS5_SYSREG_BASE 0x10050000 115 #define EXYNOS5_TZPC_BASE 0x10100000 116 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 117 #define EXYNOS5_ACE_SFR_BASE 0x10830000 118 #define EXYNOS5_DMC_PHY_BASE 0x10C00000 119 #define EXYNOS5_GPIO_PART5_BASE 0x10D10000 120 #define EXYNOS5_GPIO_PART6_BASE 0x10D10060 121 #define EXYNOS5_GPIO_PART7_BASE 0x10D100C0 122 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 123 #define EXYNOS5_GPIO_PART1_BASE 0x11400000 124 #define EXYNOS5_GPIO_PART2_BASE 0x114002E0 125 #define EXYNOS5_GPIO_PART3_BASE 0x11400C00 126 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 127 #define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000 128 #define EXYNOS5_USB3PHY_BASE 0x12100000 129 #define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 130 #define EXYNOS5_USBPHY_BASE 0x12130000 131 #define EXYNOS5_USBOTG_BASE 0x12140000 132 #define EXYNOS5_MMC_BASE 0x12200000 133 #define EXYNOS5_SROMC_BASE 0x12250000 134 #define EXYNOS5_UART_BASE 0x12C00000 135 #define EXYNOS5_I2C_BASE 0x12C60000 136 #define EXYNOS5_SPI_BASE 0x12D20000 137 #define EXYNOS5_I2S_BASE 0x12D60000 138 #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 139 #define EXYNOS5_SPI_ISP_BASE 0x131A0000 140 #define EXYNOS5_GPIO_PART4_BASE 0x13400000 141 #define EXYNOS5_FIMD_BASE 0x14400000 142 #define EXYNOS5_DP_BASE 0x145B0000 143 144 #define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE 145 #define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE 146 #define EXYNOS5_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE 147 148 /* EXYNOS5420 */ 149 #define EXYNOS5420_AUDIOSS_BASE 0x03810000 150 #define EXYNOS5420_GPIO_PART6_BASE 0x03860000 151 #define EXYNOS5420_PRO_ID 0x10000000 152 #define EXYNOS5420_CLOCK_BASE 0x10010000 153 #define EXYNOS5420_POWER_BASE 0x10040000 154 #define EXYNOS5420_SWRESET 0x10040400 155 #define EXYNOS5420_INFORM_BASE 0x10040800 156 #define EXYNOS5420_SPARE_BASE 0x10040900 157 #define EXYNOS5420_CPU_CONFIG_BASE 0x10042000 158 #define EXYNOS5420_CPU_STATUS_BASE 0x10042004 159 #define EXYNOS5420_SYSREG_BASE 0x10050000 160 #define EXYNOS5420_TZPC_BASE 0x100E0000 161 #define EXYNOS5420_WATCHDOG_BASE 0x101D0000 162 #define EXYNOS5420_ACE_SFR_BASE 0x10830000 163 #define EXYNOS5420_DMC_PHY_BASE 0x10C00000 164 #define EXYNOS5420_DMC_CTRL_BASE 0x10C20000 165 #define EXYNOS5420_DMC_TZASC_BASE 0x10D40000 166 #define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000 167 #define EXYNOS5420_MMC_BASE 0x12200000 168 #define EXYNOS5420_SROMC_BASE 0x12250000 169 #define EXYNOS5420_USB3PHY_BASE 0x12500000 170 #define EXYNOS5420_UART_BASE 0x12C00000 171 #define EXYNOS5420_I2C_BASE 0x12C60000 172 #define EXYNOS5420_I2C_8910_BASE 0x12E00000 173 #define EXYNOS5420_SPI_BASE 0x12D20000 174 #define EXYNOS5420_I2S_BASE 0x12D60000 175 #define EXYNOS5420_PWMTIMER_BASE 0x12DD0000 176 #define EXYNOS5420_SPI_ISP_BASE 0x131A0000 177 #define EXYNOS5420_GPIO_PART2_BASE 0x13400000 178 #define EXYNOS5420_GPIO_PART3_BASE 0x13400C00 179 #define EXYNOS5420_GPIO_PART4_BASE 0x13410000 180 #define EXYNOS5420_GPIO_PART5_BASE 0x14000000 181 #define EXYNOS5420_GPIO_PART1_BASE 0x14010000 182 #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 183 #define EXYNOS5420_DP_BASE 0x145B0000 184 185 #define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE 186 #define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE 187 #define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE 188 #define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE 189 #define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE 190 #define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE 191 192 193 #ifndef __ASSEMBLY__ 194 #include <asm/io.h> 195 /* CPU detection macros */ 196 extern unsigned int s5p_cpu_id; 197 extern unsigned int s5p_cpu_rev; 198 s5p_get_cpu_rev(void)199 static inline int s5p_get_cpu_rev(void) 200 { 201 return s5p_cpu_rev; 202 } 203 s5p_set_cpu_id(void)204 static inline void s5p_set_cpu_id(void) 205 { 206 unsigned int pro_id = readl(EXYNOS4_PRO_ID); 207 unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12; 208 unsigned int cpu_rev = pro_id & 0x000000FF; 209 210 switch (cpu_id) { 211 case 0x200: 212 /* Exynos4210 EVT0 */ 213 s5p_cpu_id = 0x4210; 214 s5p_cpu_rev = 0; 215 break; 216 case 0x210: 217 /* Exynos4210 EVT1 */ 218 s5p_cpu_id = 0x4210; 219 s5p_cpu_rev = cpu_rev; 220 break; 221 case 0x412: 222 /* Exynos4412 */ 223 s5p_cpu_id = 0x4412; 224 s5p_cpu_rev = cpu_rev; 225 break; 226 case 0x520: 227 /* Exynos5250 */ 228 s5p_cpu_id = 0x5250; 229 break; 230 case 0x420: 231 /* Exynos5420 */ 232 s5p_cpu_id = 0x5420; 233 break; 234 case 0x422: 235 /* 236 * Exynos5800 is a variant of Exynos5420 237 * and has product id 0x5422 238 */ 239 s5p_cpu_id = 0x5422; 240 break; 241 } 242 } 243 s5p_get_cpu_name(void)244 static inline char *s5p_get_cpu_name(void) 245 { 246 return EXYNOS_CPU_NAME; 247 } 248 249 #define IS_SAMSUNG_TYPE(type, id) \ 250 static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \ 251 { \ 252 return (s5p_cpu_id >> 12) == id; \ 253 } 254 255 IS_SAMSUNG_TYPE(exynos4, 0x4) 256 IS_SAMSUNG_TYPE(exynos5, 0x5) 257 258 #define IS_EXYNOS_TYPE(type, id) \ 259 static inline int __attribute__((no_instrument_function)) \ 260 proid_is_##type(void) \ 261 { \ 262 return s5p_cpu_id == id; \ 263 } 264 265 IS_EXYNOS_TYPE(exynos4210, 0x4210) 266 IS_EXYNOS_TYPE(exynos4412, 0x4412) 267 IS_EXYNOS_TYPE(exynos5250, 0x5250) 268 IS_EXYNOS_TYPE(exynos5420, 0x5420) 269 IS_EXYNOS_TYPE(exynos5422, 0x5422) 270 271 #define proid_is_exynos542x() (proid_is_exynos5420() || proid_is_exynos5422()) 272 273 #define SAMSUNG_BASE(device, base) \ 274 static inline unsigned long __attribute__((no_instrument_function)) \ 275 samsung_get_base_##device(void) \ 276 { \ 277 if (cpu_is_exynos4()) { \ 278 if (proid_is_exynos4412()) \ 279 return EXYNOS4X12_##base; \ 280 return EXYNOS4_##base; \ 281 } else if (cpu_is_exynos5()) { \ 282 if (proid_is_exynos542x()) \ 283 return EXYNOS5420_##base; \ 284 return EXYNOS5_##base; \ 285 } \ 286 return 0; \ 287 } 288 289 SAMSUNG_BASE(adc, ADC_BASE) 290 SAMSUNG_BASE(clock, CLOCK_BASE) 291 SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) 292 SAMSUNG_BASE(sysreg, SYSREG_BASE) 293 SAMSUNG_BASE(i2c, I2C_BASE) 294 SAMSUNG_BASE(i2s, I2S_BASE) 295 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) 296 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) 297 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) 298 SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE) 299 SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE) 300 SAMSUNG_BASE(pro_id, PRO_ID) 301 SAMSUNG_BASE(mmc, MMC_BASE) 302 SAMSUNG_BASE(modem, MODEM_BASE) 303 SAMSUNG_BASE(sromc, SROMC_BASE) 304 SAMSUNG_BASE(swreset, SWRESET) 305 SAMSUNG_BASE(timer, PWMTIMER_BASE) 306 SAMSUNG_BASE(uart, UART_BASE) 307 SAMSUNG_BASE(usb_phy, USBPHY_BASE) 308 SAMSUNG_BASE(usb3_phy, USB3PHY_BASE) 309 SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE) 310 SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE) 311 SAMSUNG_BASE(usb_otg, USBOTG_BASE) 312 SAMSUNG_BASE(watchdog, WATCHDOG_BASE) 313 SAMSUNG_BASE(power, POWER_BASE) 314 SAMSUNG_BASE(spi, SPI_BASE) 315 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) 316 SAMSUNG_BASE(tzpc, TZPC_BASE) 317 SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE) 318 SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE) 319 SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE) 320 SAMSUNG_BASE(audio_ass, AUDIOSS_BASE) 321 #endif 322 323 #endif /* _EXYNOS4_CPU_H */ 324