xref: /openbmc/linux/drivers/net/ethernet/pensando/ionic/ionic_if.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1  /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
2  /* Copyright (c) 2017-2020 Pensando Systems, Inc.  All rights reserved. */
3  
4  #ifndef _IONIC_IF_H_
5  #define _IONIC_IF_H_
6  
7  #define IONIC_DEV_INFO_SIGNATURE		0x44455649      /* 'DEVI' */
8  #define IONIC_DEV_INFO_VERSION			1
9  #define IONIC_IFNAMSIZ				16
10  
11  /*
12   * enum ionic_cmd_opcode - Device commands
13   */
14  enum ionic_cmd_opcode {
15  	IONIC_CMD_NOP				= 0,
16  
17  	/* Device commands */
18  	IONIC_CMD_IDENTIFY			= 1,
19  	IONIC_CMD_INIT				= 2,
20  	IONIC_CMD_RESET				= 3,
21  	IONIC_CMD_GETATTR			= 4,
22  	IONIC_CMD_SETATTR			= 5,
23  
24  	/* Port commands */
25  	IONIC_CMD_PORT_IDENTIFY			= 10,
26  	IONIC_CMD_PORT_INIT			= 11,
27  	IONIC_CMD_PORT_RESET			= 12,
28  	IONIC_CMD_PORT_GETATTR			= 13,
29  	IONIC_CMD_PORT_SETATTR			= 14,
30  
31  	/* LIF commands */
32  	IONIC_CMD_LIF_IDENTIFY			= 20,
33  	IONIC_CMD_LIF_INIT			= 21,
34  	IONIC_CMD_LIF_RESET			= 22,
35  	IONIC_CMD_LIF_GETATTR			= 23,
36  	IONIC_CMD_LIF_SETATTR			= 24,
37  	IONIC_CMD_LIF_SETPHC			= 25,
38  
39  	IONIC_CMD_RX_MODE_SET			= 30,
40  	IONIC_CMD_RX_FILTER_ADD			= 31,
41  	IONIC_CMD_RX_FILTER_DEL			= 32,
42  
43  	/* Queue commands */
44  	IONIC_CMD_Q_IDENTIFY			= 39,
45  	IONIC_CMD_Q_INIT			= 40,
46  	IONIC_CMD_Q_CONTROL			= 41,
47  
48  	/* RDMA commands */
49  	IONIC_CMD_RDMA_RESET_LIF		= 50,
50  	IONIC_CMD_RDMA_CREATE_EQ		= 51,
51  	IONIC_CMD_RDMA_CREATE_CQ		= 52,
52  	IONIC_CMD_RDMA_CREATE_ADMINQ		= 53,
53  
54  	/* SR/IOV commands */
55  	IONIC_CMD_VF_GETATTR			= 60,
56  	IONIC_CMD_VF_SETATTR			= 61,
57  	IONIC_CMD_VF_CTRL			= 62,
58  
59  	/* QoS commands */
60  	IONIC_CMD_QOS_CLASS_IDENTIFY		= 240,
61  	IONIC_CMD_QOS_CLASS_INIT		= 241,
62  	IONIC_CMD_QOS_CLASS_RESET		= 242,
63  	IONIC_CMD_QOS_CLASS_UPDATE		= 243,
64  	IONIC_CMD_QOS_CLEAR_STATS		= 244,
65  	IONIC_CMD_QOS_RESET			= 245,
66  
67  	/* Firmware commands */
68  	IONIC_CMD_FW_DOWNLOAD                   = 252,
69  	IONIC_CMD_FW_CONTROL                    = 253,
70  	IONIC_CMD_FW_DOWNLOAD_V1		= 254,
71  	IONIC_CMD_FW_CONTROL_V1		        = 255,
72  };
73  
74  /**
75   * enum ionic_status_code - Device command return codes
76   */
77  enum ionic_status_code {
78  	IONIC_RC_SUCCESS	= 0,	/* Success */
79  	IONIC_RC_EVERSION	= 1,	/* Incorrect version for request */
80  	IONIC_RC_EOPCODE	= 2,	/* Invalid cmd opcode */
81  	IONIC_RC_EIO		= 3,	/* I/O error */
82  	IONIC_RC_EPERM		= 4,	/* Permission denied */
83  	IONIC_RC_EQID		= 5,	/* Bad qid */
84  	IONIC_RC_EQTYPE		= 6,	/* Bad qtype */
85  	IONIC_RC_ENOENT		= 7,	/* No such element */
86  	IONIC_RC_EINTR		= 8,	/* operation interrupted */
87  	IONIC_RC_EAGAIN		= 9,	/* Try again */
88  	IONIC_RC_ENOMEM		= 10,	/* Out of memory */
89  	IONIC_RC_EFAULT		= 11,	/* Bad address */
90  	IONIC_RC_EBUSY		= 12,	/* Device or resource busy */
91  	IONIC_RC_EEXIST		= 13,	/* object already exists */
92  	IONIC_RC_EINVAL		= 14,	/* Invalid argument */
93  	IONIC_RC_ENOSPC		= 15,	/* No space left or alloc failure */
94  	IONIC_RC_ERANGE		= 16,	/* Parameter out of range */
95  	IONIC_RC_BAD_ADDR	= 17,	/* Descriptor contains a bad ptr */
96  	IONIC_RC_DEV_CMD	= 18,	/* Device cmd attempted on AdminQ */
97  	IONIC_RC_ENOSUPP	= 19,	/* Operation not supported */
98  	IONIC_RC_ERROR		= 29,	/* Generic error */
99  	IONIC_RC_ERDMA		= 30,	/* Generic RDMA error */
100  	IONIC_RC_EVFID		= 31,	/* VF ID does not exist */
101  	IONIC_RC_EBAD_FW	= 32,	/* FW file is invalid or corrupted */
102  };
103  
104  enum ionic_notifyq_opcode {
105  	IONIC_EVENT_LINK_CHANGE		= 1,
106  	IONIC_EVENT_RESET		= 2,
107  	IONIC_EVENT_HEARTBEAT		= 3,
108  	IONIC_EVENT_LOG			= 4,
109  	IONIC_EVENT_XCVR		= 5,
110  };
111  
112  /**
113   * struct ionic_admin_cmd - General admin command format
114   * @opcode:     Opcode for the command
115   * @lif_index:  LIF index
116   * @cmd_data:   Opcode-specific command bytes
117   */
118  struct ionic_admin_cmd {
119  	u8     opcode;
120  	u8     rsvd;
121  	__le16 lif_index;
122  	u8     cmd_data[60];
123  };
124  
125  /**
126   * struct ionic_admin_comp - General admin command completion format
127   * @status:     Status of the command (enum ionic_status_code)
128   * @comp_index: Index in the descriptor ring for which this is the completion
129   * @cmd_data:   Command-specific bytes
130   * @color:      Color bit (Always 0 for commands issued to the
131   *              Device Cmd Registers)
132   */
133  struct ionic_admin_comp {
134  	u8     status;
135  	u8     rsvd;
136  	__le16 comp_index;
137  	u8     cmd_data[11];
138  	u8     color;
139  #define IONIC_COMP_COLOR_MASK  0x80
140  };
141  
color_match(u8 color,u8 done_color)142  static inline u8 color_match(u8 color, u8 done_color)
143  {
144  	return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;
145  }
146  
147  /**
148   * struct ionic_nop_cmd - NOP command
149   * @opcode: opcode
150   */
151  struct ionic_nop_cmd {
152  	u8 opcode;
153  	u8 rsvd[63];
154  };
155  
156  /**
157   * struct ionic_nop_comp - NOP command completion
158   * @status: Status of the command (enum ionic_status_code)
159   */
160  struct ionic_nop_comp {
161  	u8 status;
162  	u8 rsvd[15];
163  };
164  
165  /**
166   * struct ionic_dev_init_cmd - Device init command
167   * @opcode:    opcode
168   * @type:      Device type
169   */
170  struct ionic_dev_init_cmd {
171  	u8     opcode;
172  	u8     type;
173  	u8     rsvd[62];
174  };
175  
176  /**
177   * struct ionic_dev_init_comp - Device init command completion
178   * @status: Status of the command (enum ionic_status_code)
179   */
180  struct ionic_dev_init_comp {
181  	u8 status;
182  	u8 rsvd[15];
183  };
184  
185  /**
186   * struct ionic_dev_reset_cmd - Device reset command
187   * @opcode: opcode
188   */
189  struct ionic_dev_reset_cmd {
190  	u8 opcode;
191  	u8 rsvd[63];
192  };
193  
194  /**
195   * struct ionic_dev_reset_comp - Reset command completion
196   * @status: Status of the command (enum ionic_status_code)
197   */
198  struct ionic_dev_reset_comp {
199  	u8 status;
200  	u8 rsvd[15];
201  };
202  
203  #define IONIC_IDENTITY_VERSION_1	1
204  #define IONIC_DEV_IDENTITY_VERSION_2	2
205  
206  /**
207   * struct ionic_dev_identify_cmd - Driver/device identify command
208   * @opcode:  opcode
209   * @ver:     Highest version of identify supported by driver
210   */
211  struct ionic_dev_identify_cmd {
212  	u8 opcode;
213  	u8 ver;
214  	u8 rsvd[62];
215  };
216  
217  /**
218   * struct ionic_dev_identify_comp - Driver/device identify command completion
219   * @status: Status of the command (enum ionic_status_code)
220   * @ver:    Version of identify returned by device
221   */
222  struct ionic_dev_identify_comp {
223  	u8 status;
224  	u8 ver;
225  	u8 rsvd[14];
226  };
227  
228  enum ionic_os_type {
229  	IONIC_OS_TYPE_LINUX   = 1,
230  	IONIC_OS_TYPE_WIN     = 2,
231  	IONIC_OS_TYPE_DPDK    = 3,
232  	IONIC_OS_TYPE_FREEBSD = 4,
233  	IONIC_OS_TYPE_IPXE    = 5,
234  	IONIC_OS_TYPE_ESXI    = 6,
235  };
236  
237  /**
238   * union ionic_drv_identity - driver identity information
239   * @os_type:          OS type (see enum ionic_os_type)
240   * @os_dist:          OS distribution, numeric format
241   * @os_dist_str:      OS distribution, string format
242   * @kernel_ver:       Kernel version, numeric format
243   * @kernel_ver_str:   Kernel version, string format
244   * @driver_ver_str:   Driver version, string format
245   */
246  union ionic_drv_identity {
247  	struct {
248  		__le32 os_type;
249  		__le32 os_dist;
250  		char   os_dist_str[128];
251  		__le32 kernel_ver;
252  		char   kernel_ver_str[32];
253  		char   driver_ver_str[32];
254  	};
255  	__le32 words[478];
256  };
257  
258  /**
259   * enum ionic_dev_capability - Device capabilities
260   * @IONIC_DEV_CAP_VF_CTRL:     Device supports VF ctrl operations
261   */
262  enum ionic_dev_capability {
263  	IONIC_DEV_CAP_VF_CTRL        = BIT(0),
264  };
265  
266  /**
267   * union ionic_dev_identity - device identity information
268   * @version:          Version of device identify
269   * @type:             Identify type (0 for now)
270   * @nports:           Number of ports provisioned
271   * @nlifs:            Number of LIFs provisioned
272   * @nintrs:           Number of interrupts provisioned
273   * @ndbpgs_per_lif:   Number of doorbell pages per LIF
274   * @intr_coal_mult:   Interrupt coalescing multiplication factor
275   *                    Scale user-supplied interrupt coalescing
276   *                    value in usecs to device units using:
277   *                    device units = usecs * mult / div
278   * @intr_coal_div:    Interrupt coalescing division factor
279   *                    Scale user-supplied interrupt coalescing
280   *                    value in usecs to device units using:
281   *                    device units = usecs * mult / div
282   * @eq_count:         Number of shared event queues
283   * @hwstamp_mask:     Bitmask for subtraction of hardware tick values.
284   * @hwstamp_mult:     Hardware tick to nanosecond multiplier.
285   * @hwstamp_shift:    Hardware tick to nanosecond divisor (power of two).
286   * @capabilities:     Device capabilities
287   */
288  union ionic_dev_identity {
289  	struct {
290  		u8     version;
291  		u8     type;
292  		u8     rsvd[2];
293  		u8     nports;
294  		u8     rsvd2[3];
295  		__le32 nlifs;
296  		__le32 nintrs;
297  		__le32 ndbpgs_per_lif;
298  		__le32 intr_coal_mult;
299  		__le32 intr_coal_div;
300  		__le32 eq_count;
301  		__le64 hwstamp_mask;
302  		__le32 hwstamp_mult;
303  		__le32 hwstamp_shift;
304  		__le64 capabilities;
305  	};
306  	__le32 words[478];
307  };
308  
309  enum ionic_lif_type {
310  	IONIC_LIF_TYPE_CLASSIC = 0,
311  	IONIC_LIF_TYPE_MACVLAN = 1,
312  	IONIC_LIF_TYPE_NETQUEUE = 2,
313  };
314  
315  /**
316   * struct ionic_lif_identify_cmd - LIF identify command
317   * @opcode:  opcode
318   * @type:    LIF type (enum ionic_lif_type)
319   * @ver:     Version of identify returned by device
320   */
321  struct ionic_lif_identify_cmd {
322  	u8 opcode;
323  	u8 type;
324  	u8 ver;
325  	u8 rsvd[61];
326  };
327  
328  /**
329   * struct ionic_lif_identify_comp - LIF identify command completion
330   * @status:  Status of the command (enum ionic_status_code)
331   * @ver:     Version of identify returned by device
332   */
333  struct ionic_lif_identify_comp {
334  	u8 status;
335  	u8 ver;
336  	u8 rsvd2[14];
337  };
338  
339  /**
340   * enum ionic_lif_capability - LIF capabilities
341   * @IONIC_LIF_CAP_ETH:     LIF supports Ethernet
342   * @IONIC_LIF_CAP_RDMA:    LIF supports RDMA
343   */
344  enum ionic_lif_capability {
345  	IONIC_LIF_CAP_ETH        = BIT(0),
346  	IONIC_LIF_CAP_RDMA       = BIT(1),
347  };
348  
349  /**
350   * enum ionic_logical_qtype - Logical Queue Types
351   * @IONIC_QTYPE_ADMINQ:    Administrative Queue
352   * @IONIC_QTYPE_NOTIFYQ:   Notify Queue
353   * @IONIC_QTYPE_RXQ:       Receive Queue
354   * @IONIC_QTYPE_TXQ:       Transmit Queue
355   * @IONIC_QTYPE_EQ:        Event Queue
356   * @IONIC_QTYPE_MAX:       Max queue type supported
357   */
358  enum ionic_logical_qtype {
359  	IONIC_QTYPE_ADMINQ  = 0,
360  	IONIC_QTYPE_NOTIFYQ = 1,
361  	IONIC_QTYPE_RXQ     = 2,
362  	IONIC_QTYPE_TXQ     = 3,
363  	IONIC_QTYPE_EQ      = 4,
364  	IONIC_QTYPE_MAX     = 16,
365  };
366  
367  /**
368   * enum ionic_q_feature - Common Features for most queue types
369   *
370   * Common features use bits 0-15. Per-queue-type features use higher bits.
371   *
372   * @IONIC_QIDENT_F_CQ:      Queue has completion ring
373   * @IONIC_QIDENT_F_SG:      Queue has scatter/gather ring
374   * @IONIC_QIDENT_F_EQ:      Queue can use event queue
375   * @IONIC_QIDENT_F_CMB:     Queue is in cmb bar
376   * @IONIC_Q_F_2X_DESC:      Double main descriptor size
377   * @IONIC_Q_F_2X_CQ_DESC:   Double cq descriptor size
378   * @IONIC_Q_F_2X_SG_DESC:   Double sg descriptor size
379   * @IONIC_Q_F_4X_DESC:      Quadruple main descriptor size
380   * @IONIC_Q_F_4X_CQ_DESC:   Quadruple cq descriptor size
381   * @IONIC_Q_F_4X_SG_DESC:   Quadruple sg descriptor size
382   */
383  enum ionic_q_feature {
384  	IONIC_QIDENT_F_CQ		= BIT_ULL(0),
385  	IONIC_QIDENT_F_SG		= BIT_ULL(1),
386  	IONIC_QIDENT_F_EQ		= BIT_ULL(2),
387  	IONIC_QIDENT_F_CMB		= BIT_ULL(3),
388  	IONIC_Q_F_2X_DESC		= BIT_ULL(4),
389  	IONIC_Q_F_2X_CQ_DESC		= BIT_ULL(5),
390  	IONIC_Q_F_2X_SG_DESC		= BIT_ULL(6),
391  	IONIC_Q_F_4X_DESC		= BIT_ULL(7),
392  	IONIC_Q_F_4X_CQ_DESC		= BIT_ULL(8),
393  	IONIC_Q_F_4X_SG_DESC		= BIT_ULL(9),
394  };
395  
396  /**
397   * enum ionic_rxq_feature - RXQ-specific Features
398   *
399   * Per-queue-type features use bits 16 and higher.
400   *
401   * @IONIC_RXQ_F_HWSTAMP:   Queue supports Hardware Timestamping
402   */
403  enum ionic_rxq_feature {
404  	IONIC_RXQ_F_HWSTAMP		= BIT_ULL(16),
405  };
406  
407  /**
408   * enum ionic_txq_feature - TXQ-specific Features
409   *
410   * Per-queue-type features use bits 16 and higher.
411   *
412   * @IONIC_TXQ_F_HWSTAMP:   Queue supports Hardware Timestamping
413   */
414  enum ionic_txq_feature {
415  	IONIC_TXQ_F_HWSTAMP		= BIT(16),
416  };
417  
418  /**
419   * struct ionic_hwstamp_bits - Hardware timestamp decoding bits
420   * @IONIC_HWSTAMP_INVALID:          Invalid hardware timestamp value
421   * @IONIC_HWSTAMP_CQ_NEGOFFSET:     Timestamp field negative offset
422   *                                  from the base cq descriptor.
423   */
424  enum ionic_hwstamp_bits {
425  	IONIC_HWSTAMP_INVALID	    = ~0ull,
426  	IONIC_HWSTAMP_CQ_NEGOFFSET  = 8,
427  };
428  
429  /**
430   * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type
431   * @qtype:          Hardware Queue Type
432   * @qid_count:      Number of Queue IDs of the logical type
433   * @qid_base:       Minimum Queue ID of the logical type
434   */
435  struct ionic_lif_logical_qtype {
436  	u8     qtype;
437  	u8     rsvd[3];
438  	__le32 qid_count;
439  	__le32 qid_base;
440  };
441  
442  /**
443   * enum ionic_lif_state - LIF state
444   * @IONIC_LIF_DISABLE:     LIF disabled
445   * @IONIC_LIF_ENABLE:      LIF enabled
446   * @IONIC_LIF_QUIESCE:     LIF Quiesced
447   */
448  enum ionic_lif_state {
449  	IONIC_LIF_QUIESCE	= 0,
450  	IONIC_LIF_ENABLE	= 1,
451  	IONIC_LIF_DISABLE	= 2,
452  };
453  
454  /**
455   * union ionic_lif_config - LIF configuration
456   * @state:          LIF state (enum ionic_lif_state)
457   * @name:           LIF name
458   * @mtu:            MTU
459   * @mac:            Station MAC address
460   * @vlan:           Default Vlan ID
461   * @features:       Features (enum ionic_eth_hw_features)
462   * @queue_count:    Queue counts per queue-type
463   */
464  union ionic_lif_config {
465  	struct {
466  		u8     state;
467  		u8     rsvd[3];
468  		char   name[IONIC_IFNAMSIZ];
469  		__le32 mtu;
470  		u8     mac[6];
471  		__le16 vlan;
472  		__le64 features;
473  		__le32 queue_count[IONIC_QTYPE_MAX];
474  	} __packed;
475  	__le32 words[64];
476  };
477  
478  /**
479   * struct ionic_lif_identity - LIF identity information (type-specific)
480   *
481   * @capabilities:        LIF capabilities
482   *
483   * @eth:                    Ethernet identify structure
484   *     @version:            Ethernet identify structure version
485   *     @max_ucast_filters:  Number of perfect unicast addresses supported
486   *     @max_mcast_filters:  Number of perfect multicast addresses supported
487   *     @min_frame_size:     Minimum size of frames to be sent
488   *     @max_frame_size:     Maximum size of frames to be sent
489   *     @hwstamp_tx_modes:   Bitmask of BIT_ULL(enum ionic_txstamp_mode)
490   *     @hwstamp_rx_filters: Bitmask of enum ionic_pkt_class
491   *     @config:             LIF config struct with features, mtu, mac, q counts
492   *
493   * @rdma:                RDMA identify structure
494   *     @version:         RDMA version of opcodes and queue descriptors
495   *     @qp_opcodes:      Number of RDMA queue pair opcodes supported
496   *     @admin_opcodes:   Number of RDMA admin opcodes supported
497   *     @npts_per_lif:    Page table size per LIF
498   *     @nmrs_per_lif:    Number of memory regions per LIF
499   *     @nahs_per_lif:    Number of address handles per LIF
500   *     @max_stride:      Max work request stride
501   *     @cl_stride:       Cache line stride
502   *     @pte_stride:      Page table entry stride
503   *     @rrq_stride:      Remote RQ work request stride
504   *     @rsq_stride:      Remote SQ work request stride
505   *     @dcqcn_profiles:  Number of DCQCN profiles
506   *     @aq_qtype:        RDMA Admin Qtype
507   *     @sq_qtype:        RDMA Send Qtype
508   *     @rq_qtype:        RDMA Receive Qtype
509   *     @cq_qtype:        RDMA Completion Qtype
510   *     @eq_qtype:        RDMA Event Qtype
511   */
512  union ionic_lif_identity {
513  	struct {
514  		__le64 capabilities;
515  
516  		struct {
517  			u8 version;
518  			u8 rsvd[3];
519  			__le32 max_ucast_filters;
520  			__le32 max_mcast_filters;
521  			__le16 rss_ind_tbl_sz;
522  			__le32 min_frame_size;
523  			__le32 max_frame_size;
524  			u8 rsvd2[2];
525  			__le64 hwstamp_tx_modes;
526  			__le64 hwstamp_rx_filters;
527  			u8 rsvd3[88];
528  			union ionic_lif_config config;
529  		} __packed eth;
530  
531  		struct {
532  			u8 version;
533  			u8 qp_opcodes;
534  			u8 admin_opcodes;
535  			u8 rsvd;
536  			__le32 npts_per_lif;
537  			__le32 nmrs_per_lif;
538  			__le32 nahs_per_lif;
539  			u8 max_stride;
540  			u8 cl_stride;
541  			u8 pte_stride;
542  			u8 rrq_stride;
543  			u8 rsq_stride;
544  			u8 dcqcn_profiles;
545  			u8 rsvd_dimensions[10];
546  			struct ionic_lif_logical_qtype aq_qtype;
547  			struct ionic_lif_logical_qtype sq_qtype;
548  			struct ionic_lif_logical_qtype rq_qtype;
549  			struct ionic_lif_logical_qtype cq_qtype;
550  			struct ionic_lif_logical_qtype eq_qtype;
551  		} __packed rdma;
552  	} __packed;
553  	__le32 words[478];
554  };
555  
556  /**
557   * struct ionic_lif_init_cmd - LIF init command
558   * @opcode:       Opcode
559   * @type:         LIF type (enum ionic_lif_type)
560   * @index:        LIF index
561   * @info_pa:      Destination address for LIF info (struct ionic_lif_info)
562   */
563  struct ionic_lif_init_cmd {
564  	u8     opcode;
565  	u8     type;
566  	__le16 index;
567  	__le32 rsvd;
568  	__le64 info_pa;
569  	u8     rsvd2[48];
570  };
571  
572  /**
573   * struct ionic_lif_init_comp - LIF init command completion
574   * @status:	Status of the command (enum ionic_status_code)
575   * @hw_index:	Hardware index of the initialized LIF
576   */
577  struct ionic_lif_init_comp {
578  	u8 status;
579  	u8 rsvd;
580  	__le16 hw_index;
581  	u8 rsvd2[12];
582  };
583  
584  /**
585   * struct ionic_q_identify_cmd - queue identify command
586   * @opcode:     opcode
587   * @lif_type:   LIF type (enum ionic_lif_type)
588   * @type:       Logical queue type (enum ionic_logical_qtype)
589   * @ver:        Highest queue type version that the driver supports
590   */
591  struct ionic_q_identify_cmd {
592  	u8     opcode;
593  	u8     rsvd;
594  	__le16 lif_type;
595  	u8     type;
596  	u8     ver;
597  	u8     rsvd2[58];
598  };
599  
600  /**
601   * struct ionic_q_identify_comp - queue identify command completion
602   * @status:     Status of the command (enum ionic_status_code)
603   * @comp_index: Index in the descriptor ring for which this is the completion
604   * @ver:        Queue type version that can be used with FW
605   */
606  struct ionic_q_identify_comp {
607  	u8     status;
608  	u8     rsvd;
609  	__le16 comp_index;
610  	u8     ver;
611  	u8     rsvd2[11];
612  };
613  
614  /**
615   * union ionic_q_identity - queue identity information
616   *     @version:        Queue type version that can be used with FW
617   *     @supported:      Bitfield of queue versions, first bit = ver 0
618   *     @features:       Queue features (enum ionic_q_feature, etc)
619   *     @desc_sz:        Descriptor size
620   *     @comp_sz:        Completion descriptor size
621   *     @sg_desc_sz:     Scatter/Gather descriptor size
622   *     @max_sg_elems:   Maximum number of Scatter/Gather elements
623   *     @sg_desc_stride: Number of Scatter/Gather elements per descriptor
624   */
625  union ionic_q_identity {
626  	struct {
627  		u8      version;
628  		u8      supported;
629  		u8      rsvd[6];
630  		__le64  features;
631  		__le16  desc_sz;
632  		__le16  comp_sz;
633  		__le16  sg_desc_sz;
634  		__le16  max_sg_elems;
635  		__le16  sg_desc_stride;
636  	};
637  	__le32 words[478];
638  };
639  
640  /**
641   * struct ionic_q_init_cmd - Queue init command
642   * @opcode:       opcode
643   * @type:         Logical queue type
644   * @ver:          Queue type version
645   * @lif_index:    LIF index
646   * @index:        (LIF, qtype) relative admin queue index
647   * @intr_index:   Interrupt control register index, or Event queue index
648   * @pid:          Process ID
649   * @flags:
650   *    IRQ:        Interrupt requested on completion
651   *    ENA:        Enable the queue.  If ENA=0 the queue is initialized
652   *                but remains disabled, to be later enabled with the
653   *                Queue Enable command.  If ENA=1, then queue is
654   *                initialized and then enabled.
655   *    SG:         Enable Scatter-Gather on the queue.
656   *                in number of descs.  The actual ring size is
657   *                (1 << ring_size).  For example, to
658   *                select a ring size of 64 descriptors write
659   *                ring_size = 6.  The minimum ring_size value is 2
660   *                for a ring size of 4 descriptors.  The maximum
661   *                ring_size value is 16 for a ring size of 64k
662   *                descriptors.  Values of ring_size <2 and >16 are
663   *                reserved.
664   *    EQ:         Enable the Event Queue
665   * @cos:          Class of service for this queue
666   * @ring_size:    Queue ring size, encoded as a log2(size)
667   * @ring_base:    Queue ring base address
668   * @cq_ring_base: Completion queue ring base address
669   * @sg_ring_base: Scatter/Gather ring base address
670   * @features:     Mask of queue features to enable, if not in the flags above.
671   */
672  struct ionic_q_init_cmd {
673  	u8     opcode;
674  	u8     rsvd;
675  	__le16 lif_index;
676  	u8     type;
677  	u8     ver;
678  	u8     rsvd1[2];
679  	__le32 index;
680  	__le16 pid;
681  	__le16 intr_index;
682  	__le16 flags;
683  #define IONIC_QINIT_F_IRQ	0x01	/* Request interrupt on completion */
684  #define IONIC_QINIT_F_ENA	0x02	/* Enable the queue */
685  #define IONIC_QINIT_F_SG	0x04	/* Enable scatter/gather on the queue */
686  #define IONIC_QINIT_F_EQ	0x08	/* Enable event queue */
687  #define IONIC_QINIT_F_CMB	0x10	/* Enable cmb-based queue */
688  #define IONIC_QINIT_F_DEBUG	0x80	/* Enable queue debugging */
689  	u8     cos;
690  	u8     ring_size;
691  	__le64 ring_base;
692  	__le64 cq_ring_base;
693  	__le64 sg_ring_base;
694  	u8     rsvd2[12];
695  	__le64 features;
696  } __packed;
697  
698  /**
699   * struct ionic_q_init_comp - Queue init command completion
700   * @status:     Status of the command (enum ionic_status_code)
701   * @comp_index: Index in the descriptor ring for which this is the completion
702   * @hw_index:   Hardware Queue ID
703   * @hw_type:    Hardware Queue type
704   * @color:      Color
705   */
706  struct ionic_q_init_comp {
707  	u8     status;
708  	u8     rsvd;
709  	__le16 comp_index;
710  	__le32 hw_index;
711  	u8     hw_type;
712  	u8     rsvd2[6];
713  	u8     color;
714  };
715  
716  /* the device's internal addressing uses up to 52 bits */
717  #define IONIC_ADDR_LEN		52
718  #define IONIC_ADDR_MASK		(BIT_ULL(IONIC_ADDR_LEN) - 1)
719  
720  enum ionic_txq_desc_opcode {
721  	IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0,
722  	IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1,
723  	IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2,
724  	IONIC_TXQ_DESC_OPCODE_TSO = 3,
725  };
726  
727  /**
728   * struct ionic_txq_desc - Ethernet Tx queue descriptor format
729   * @cmd:          Tx operation, see IONIC_TXQ_DESC_OPCODE_*:
730   *
731   *                   IONIC_TXQ_DESC_OPCODE_CSUM_NONE:
732   *                      Non-offload send.  No segmentation,
733   *                      fragmentation or checksum calc/insertion is
734   *                      performed by device; packet is prepared
735   *                      to send by software stack and requires
736   *                      no further manipulation from device.
737   *
738   *                   IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL:
739   *                      Offload 16-bit L4 checksum
740   *                      calculation/insertion.  The device will
741   *                      calculate the L4 checksum value and
742   *                      insert the result in the packet's L4
743   *                      header checksum field.  The L4 checksum
744   *                      is calculated starting at @csum_start bytes
745   *                      into the packet to the end of the packet.
746   *                      The checksum insertion position is given
747   *                      in @csum_offset, which is the offset from
748   *                      @csum_start to the checksum field in the L4
749   *                      header.  This feature is only applicable to
750   *                      protocols such as TCP, UDP and ICMP where a
751   *                      standard (i.e. the 'IP-style' checksum)
752   *                      one's complement 16-bit checksum is used,
753   *                      using an IP pseudo-header to seed the
754   *                      calculation.  Software will preload the L4
755   *                      checksum field with the IP pseudo-header
756   *                      checksum.
757   *
758   *                      For tunnel encapsulation, @csum_start and
759   *                      @csum_offset refer to the inner L4
760   *                      header.  Supported tunnels encapsulations
761   *                      are: IPIP, GRE, and UDP.  If the @encap
762   *                      is clear, no further processing by the
763   *                      device is required; software will
764   *                      calculate the outer header checksums.  If
765   *                      the @encap is set, the device will
766   *                      offload the outer header checksums using
767   *                      LCO (local checksum offload) (see
768   *                      Documentation/networking/checksum-offloads.rst
769   *                      for more info).
770   *
771   *                   IONIC_TXQ_DESC_OPCODE_CSUM_HW:
772   *                      Offload 16-bit checksum computation to hardware.
773   *                      If @csum_l3 is set then the packet's L3 checksum is
774   *                      updated. Similarly, if @csum_l4 is set the L4
775   *                      checksum is updated. If @encap is set then encap header
776   *                      checksums are also updated.
777   *
778   *                   IONIC_TXQ_DESC_OPCODE_TSO:
779   *                      Device performs TCP segmentation offload
780   *                      (TSO).  @hdr_len is the number of bytes
781   *                      to the end of TCP header (the offset to
782   *                      the TCP payload).  @mss is the desired
783   *                      MSS, the TCP payload length for each
784   *                      segment.  The device will calculate/
785   *                      insert IP (IPv4 only) and TCP checksums
786   *                      for each segment.  In the first data
787   *                      buffer containing the header template,
788   *                      the driver will set IPv4 checksum to 0
789   *                      and preload TCP checksum with the IP
790   *                      pseudo header calculated with IP length = 0.
791   *
792   *                      Supported tunnel encapsulations are IPIP,
793   *                      layer-3 GRE, and UDP. @hdr_len includes
794   *                      both outer and inner headers.  The driver
795   *                      will set IPv4 checksum to zero and
796   *                      preload TCP checksum with IP pseudo
797   *                      header on the inner header.
798   *
799   *                      TCP ECN offload is supported.  The device
800   *                      will set CWR flag in the first segment if
801   *                      CWR is set in the template header, and
802   *                      clear CWR in remaining segments.
803   * @flags:
804   *                vlan:
805   *                    Insert an L2 VLAN header using @vlan_tci
806   *                encap:
807   *                    Calculate encap header checksum
808   *                csum_l3:
809   *                    Compute L3 header checksum
810   *                csum_l4:
811   *                    Compute L4 header checksum
812   *                tso_sot:
813   *                    TSO start
814   *                tso_eot:
815   *                    TSO end
816   * @num_sg_elems: Number of scatter-gather elements in SG
817   *                descriptor
818   * @addr:         First data buffer's DMA address
819   *                (Subsequent data buffers are on txq_sg_desc)
820   * @len:          First data buffer's length, in bytes
821   * @vlan_tci:     VLAN tag to insert in the packet (if requested
822   *                by @V-bit).  Includes .1p and .1q tags
823   * @hdr_len:      Length of packet headers, including
824   *                encapsulating outer header, if applicable
825   *                Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and
826   *                IONIC_TXQ_DESC_OPCODE_TSO.  Should be set to zero for
827   *                all other modes.  For
828   *                IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length
829   *                of headers up to inner-most L4 header.  For
830   *                IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to
831   *                inner-most L4 payload, so inclusive of
832   *                inner-most L4 header.
833   * @mss:          Desired MSS value for TSO; only applicable for
834   *                IONIC_TXQ_DESC_OPCODE_TSO
835   * @csum_start:   Offset from packet to first byte checked in L4 checksum
836   * @csum_offset:  Offset from csum_start to L4 checksum field
837   */
838  struct ionic_txq_desc {
839  	__le64  cmd;
840  #define IONIC_TXQ_DESC_OPCODE_MASK		0xf
841  #define IONIC_TXQ_DESC_OPCODE_SHIFT		4
842  #define IONIC_TXQ_DESC_FLAGS_MASK		0xf
843  #define IONIC_TXQ_DESC_FLAGS_SHIFT		0
844  #define IONIC_TXQ_DESC_NSGE_MASK		0xf
845  #define IONIC_TXQ_DESC_NSGE_SHIFT		8
846  #define IONIC_TXQ_DESC_ADDR_MASK		(BIT_ULL(IONIC_ADDR_LEN) - 1)
847  #define IONIC_TXQ_DESC_ADDR_SHIFT		12
848  
849  /* common flags */
850  #define IONIC_TXQ_DESC_FLAG_VLAN		0x1
851  #define IONIC_TXQ_DESC_FLAG_ENCAP		0x2
852  
853  /* flags for csum_hw opcode */
854  #define IONIC_TXQ_DESC_FLAG_CSUM_L3		0x4
855  #define IONIC_TXQ_DESC_FLAG_CSUM_L4		0x8
856  
857  /* flags for tso opcode */
858  #define IONIC_TXQ_DESC_FLAG_TSO_SOT		0x4
859  #define IONIC_TXQ_DESC_FLAG_TSO_EOT		0x8
860  
861  	__le16  len;
862  	union {
863  		__le16  vlan_tci;
864  		__le16  hword0;
865  	};
866  	union {
867  		__le16  csum_start;
868  		__le16  hdr_len;
869  		__le16  hword1;
870  	};
871  	union {
872  		__le16  csum_offset;
873  		__le16  mss;
874  		__le16  hword2;
875  	};
876  };
877  
encode_txq_desc_cmd(u8 opcode,u8 flags,u8 nsge,u64 addr)878  static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,
879  				      u8 nsge, u64 addr)
880  {
881  	u64 cmd;
882  
883  	cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT;
884  	cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT;
885  	cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT;
886  	cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT;
887  
888  	return cmd;
889  };
890  
decode_txq_desc_cmd(u64 cmd,u8 * opcode,u8 * flags,u8 * nsge,u64 * addr)891  static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,
892  				       u8 *nsge, u64 *addr)
893  {
894  	*opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK;
895  	*flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK;
896  	*nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK;
897  	*addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK;
898  };
899  
900  /**
901   * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element
902   * @addr:      DMA address of SG element data buffer
903   * @len:       Length of SG element data buffer, in bytes
904   */
905  struct ionic_txq_sg_elem {
906  	__le64 addr;
907  	__le16 len;
908  	__le16 rsvd[3];
909  };
910  
911  /**
912   * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list
913   * @elems:     Scatter-gather elements
914   */
915  struct ionic_txq_sg_desc {
916  #define IONIC_TX_MAX_SG_ELEMS		8
917  #define IONIC_TX_SG_DESC_STRIDE		8
918  	struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS];
919  };
920  
921  struct ionic_txq_sg_desc_v1 {
922  #define IONIC_TX_MAX_SG_ELEMS_V1		15
923  #define IONIC_TX_SG_DESC_STRIDE_V1		16
924  	struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1];
925  };
926  
927  /**
928   * struct ionic_txq_comp - Ethernet transmit queue completion descriptor
929   * @status:     Status of the command (enum ionic_status_code)
930   * @comp_index: Index in the descriptor ring for which this is the completion
931   * @color:      Color bit
932   */
933  struct ionic_txq_comp {
934  	u8     status;
935  	u8     rsvd;
936  	__le16 comp_index;
937  	u8     rsvd2[11];
938  	u8     color;
939  };
940  
941  enum ionic_rxq_desc_opcode {
942  	IONIC_RXQ_DESC_OPCODE_SIMPLE = 0,
943  	IONIC_RXQ_DESC_OPCODE_SG = 1,
944  };
945  
946  /**
947   * struct ionic_rxq_desc - Ethernet Rx queue descriptor format
948   * @opcode:       Rx operation, see IONIC_RXQ_DESC_OPCODE_*:
949   *
950   *                   IONIC_RXQ_DESC_OPCODE_SIMPLE:
951   *                      Receive full packet into data buffer
952   *                      starting at @addr.  Results of
953   *                      receive, including actual bytes received,
954   *                      are recorded in Rx completion descriptor.
955   *
956   * @len:          Data buffer's length, in bytes
957   * @addr:         Data buffer's DMA address
958   */
959  struct ionic_rxq_desc {
960  	u8     opcode;
961  	u8     rsvd[5];
962  	__le16 len;
963  	__le64 addr;
964  };
965  
966  /**
967   * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element
968   * @addr:      DMA address of SG element data buffer
969   * @len:       Length of SG element data buffer, in bytes
970   */
971  struct ionic_rxq_sg_elem {
972  	__le64 addr;
973  	__le16 len;
974  	__le16 rsvd[3];
975  };
976  
977  /**
978   * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list
979   * @elems:     Scatter-gather elements
980   */
981  struct ionic_rxq_sg_desc {
982  #define IONIC_RX_MAX_SG_ELEMS		8
983  #define IONIC_RX_SG_DESC_STRIDE		8
984  	struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE];
985  };
986  
987  /**
988   * struct ionic_rxq_comp - Ethernet receive queue completion descriptor
989   * @status:       Status of the command (enum ionic_status_code)
990   * @num_sg_elems: Number of SG elements used by this descriptor
991   * @comp_index:   Index in the descriptor ring for which this is the completion
992   * @rss_hash:     32-bit RSS hash
993   * @csum:         16-bit sum of the packet's L2 payload
994   *                If the packet's L2 payload is odd length, an extra
995   *                zero-value byte is included in the @csum calculation but
996   *                not included in @len.
997   * @vlan_tci:     VLAN tag stripped from the packet.  Valid if @VLAN is
998   *                set.  Includes .1p and .1q tags.
999   * @len:          Received packet length, in bytes.  Excludes FCS.
1000   * @csum_calc     L2 payload checksum is computed or not
1001   * @csum_flags:   See IONIC_RXQ_COMP_CSUM_F_*:
1002   *
1003   *                  IONIC_RXQ_COMP_CSUM_F_TCP_OK:
1004   *                    The TCP checksum calculated by the device
1005   *                    matched the checksum in the receive packet's
1006   *                    TCP header.
1007   *
1008   *                  IONIC_RXQ_COMP_CSUM_F_TCP_BAD:
1009   *                    The TCP checksum calculated by the device did
1010   *                    not match the checksum in the receive packet's
1011   *                    TCP header.
1012   *
1013   *                  IONIC_RXQ_COMP_CSUM_F_UDP_OK:
1014   *                    The UDP checksum calculated by the device
1015   *                    matched the checksum in the receive packet's
1016   *                    UDP header
1017   *
1018   *                  IONIC_RXQ_COMP_CSUM_F_UDP_BAD:
1019   *                    The UDP checksum calculated by the device did
1020   *                    not match the checksum in the receive packet's
1021   *                    UDP header.
1022   *
1023   *                  IONIC_RXQ_COMP_CSUM_F_IP_OK:
1024   *                    The IPv4 checksum calculated by the device
1025   *                    matched the checksum in the receive packet's
1026   *                    first IPv4 header.  If the receive packet
1027   *                    contains both a tunnel IPv4 header and a
1028   *                    transport IPv4 header, the device validates the
1029   *                    checksum for the both IPv4 headers.
1030   *
1031   *                  IONIC_RXQ_COMP_CSUM_F_IP_BAD:
1032   *                    The IPv4 checksum calculated by the device did
1033   *                    not match the checksum in the receive packet's
1034   *                    first IPv4 header. If the receive packet
1035   *                    contains both a tunnel IPv4 header and a
1036   *                    transport IPv4 header, the device validates the
1037   *                    checksum for both IP headers.
1038   *
1039   *                  IONIC_RXQ_COMP_CSUM_F_VLAN:
1040   *                    The VLAN header was stripped and placed in @vlan_tci.
1041   *
1042   *                  IONIC_RXQ_COMP_CSUM_F_CALC:
1043   *                    The checksum was calculated by the device.
1044   *
1045   * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK
1046   */
1047  struct ionic_rxq_comp {
1048  	u8     status;
1049  	u8     num_sg_elems;
1050  	__le16 comp_index;
1051  	__le32 rss_hash;
1052  	__le16 csum;
1053  	__le16 vlan_tci;
1054  	__le16 len;
1055  	u8     csum_flags;
1056  #define IONIC_RXQ_COMP_CSUM_F_TCP_OK	0x01
1057  #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD	0x02
1058  #define IONIC_RXQ_COMP_CSUM_F_UDP_OK	0x04
1059  #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD	0x08
1060  #define IONIC_RXQ_COMP_CSUM_F_IP_OK	0x10
1061  #define IONIC_RXQ_COMP_CSUM_F_IP_BAD	0x20
1062  #define IONIC_RXQ_COMP_CSUM_F_VLAN	0x40
1063  #define IONIC_RXQ_COMP_CSUM_F_CALC	0x80
1064  	u8     pkt_type_color;
1065  #define IONIC_RXQ_COMP_PKT_TYPE_MASK	0x7f
1066  };
1067  
1068  enum ionic_pkt_type {
1069  	IONIC_PKT_TYPE_NON_IP		= 0x00,
1070  	IONIC_PKT_TYPE_IPV4		= 0x01,
1071  	IONIC_PKT_TYPE_IPV4_TCP		= 0x03,
1072  	IONIC_PKT_TYPE_IPV4_UDP		= 0x05,
1073  	IONIC_PKT_TYPE_IPV6		= 0x08,
1074  	IONIC_PKT_TYPE_IPV6_TCP		= 0x18,
1075  	IONIC_PKT_TYPE_IPV6_UDP		= 0x28,
1076  	/* below types are only used if encap offloads are enabled on lif */
1077  	IONIC_PKT_TYPE_ENCAP_NON_IP	= 0x40,
1078  	IONIC_PKT_TYPE_ENCAP_IPV4	= 0x41,
1079  	IONIC_PKT_TYPE_ENCAP_IPV4_TCP	= 0x43,
1080  	IONIC_PKT_TYPE_ENCAP_IPV4_UDP	= 0x45,
1081  	IONIC_PKT_TYPE_ENCAP_IPV6	= 0x48,
1082  	IONIC_PKT_TYPE_ENCAP_IPV6_TCP	= 0x58,
1083  	IONIC_PKT_TYPE_ENCAP_IPV6_UDP	= 0x68,
1084  };
1085  
1086  enum ionic_eth_hw_features {
1087  	IONIC_ETH_HW_VLAN_TX_TAG	= BIT(0),
1088  	IONIC_ETH_HW_VLAN_RX_STRIP	= BIT(1),
1089  	IONIC_ETH_HW_VLAN_RX_FILTER	= BIT(2),
1090  	IONIC_ETH_HW_RX_HASH		= BIT(3),
1091  	IONIC_ETH_HW_RX_CSUM		= BIT(4),
1092  	IONIC_ETH_HW_TX_SG		= BIT(5),
1093  	IONIC_ETH_HW_RX_SG		= BIT(6),
1094  	IONIC_ETH_HW_TX_CSUM		= BIT(7),
1095  	IONIC_ETH_HW_TSO		= BIT(8),
1096  	IONIC_ETH_HW_TSO_IPV6		= BIT(9),
1097  	IONIC_ETH_HW_TSO_ECN		= BIT(10),
1098  	IONIC_ETH_HW_TSO_GRE		= BIT(11),
1099  	IONIC_ETH_HW_TSO_GRE_CSUM	= BIT(12),
1100  	IONIC_ETH_HW_TSO_IPXIP4		= BIT(13),
1101  	IONIC_ETH_HW_TSO_IPXIP6		= BIT(14),
1102  	IONIC_ETH_HW_TSO_UDP		= BIT(15),
1103  	IONIC_ETH_HW_TSO_UDP_CSUM	= BIT(16),
1104  	IONIC_ETH_HW_RX_CSUM_GENEVE	= BIT(17),
1105  	IONIC_ETH_HW_TX_CSUM_GENEVE	= BIT(18),
1106  	IONIC_ETH_HW_TSO_GENEVE		= BIT(19),
1107  	IONIC_ETH_HW_TIMESTAMP		= BIT(20),
1108  };
1109  
1110  /**
1111   * enum ionic_pkt_class - Packet classification mask.
1112   *
1113   * Used with rx steering filter, packets indicated by the mask can be steered
1114   * toward a specific receive queue.
1115   *
1116   * @IONIC_PKT_CLS_NTP_ALL:          All NTP packets.
1117   * @IONIC_PKT_CLS_PTP1_SYNC:        PTPv1 sync
1118   * @IONIC_PKT_CLS_PTP1_DREQ:        PTPv1 delay-request
1119   * @IONIC_PKT_CLS_PTP1_ALL:         PTPv1 all packets
1120   * @IONIC_PKT_CLS_PTP2_L4_SYNC:     PTPv2-UDP sync
1121   * @IONIC_PKT_CLS_PTP2_L4_DREQ:     PTPv2-UDP delay-request
1122   * @IONIC_PKT_CLS_PTP2_L4_ALL:      PTPv2-UDP all packets
1123   * @IONIC_PKT_CLS_PTP2_L2_SYNC:     PTPv2-ETH sync
1124   * @IONIC_PKT_CLS_PTP2_L2_DREQ:     PTPv2-ETH delay-request
1125   * @IONIC_PKT_CLS_PTP2_L2_ALL:      PTPv2-ETH all packets
1126   * @IONIC_PKT_CLS_PTP2_SYNC:        PTPv2 sync
1127   * @IONIC_PKT_CLS_PTP2_DREQ:        PTPv2 delay-request
1128   * @IONIC_PKT_CLS_PTP2_ALL:         PTPv2 all packets
1129   * @IONIC_PKT_CLS_PTP_SYNC:         PTP sync
1130   * @IONIC_PKT_CLS_PTP_DREQ:         PTP delay-request
1131   * @IONIC_PKT_CLS_PTP_ALL:          PTP all packets
1132   */
1133  enum ionic_pkt_class {
1134  	IONIC_PKT_CLS_NTP_ALL		= BIT(0),
1135  
1136  	IONIC_PKT_CLS_PTP1_SYNC		= BIT(1),
1137  	IONIC_PKT_CLS_PTP1_DREQ		= BIT(2),
1138  	IONIC_PKT_CLS_PTP1_ALL		= BIT(3) |
1139  		IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ,
1140  
1141  	IONIC_PKT_CLS_PTP2_L4_SYNC	= BIT(4),
1142  	IONIC_PKT_CLS_PTP2_L4_DREQ	= BIT(5),
1143  	IONIC_PKT_CLS_PTP2_L4_ALL	= BIT(6) |
1144  		IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ,
1145  
1146  	IONIC_PKT_CLS_PTP2_L2_SYNC	= BIT(7),
1147  	IONIC_PKT_CLS_PTP2_L2_DREQ	= BIT(8),
1148  	IONIC_PKT_CLS_PTP2_L2_ALL	= BIT(9) |
1149  		IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ,
1150  
1151  	IONIC_PKT_CLS_PTP2_SYNC		=
1152  		IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L2_SYNC,
1153  	IONIC_PKT_CLS_PTP2_DREQ		=
1154  		IONIC_PKT_CLS_PTP2_L4_DREQ | IONIC_PKT_CLS_PTP2_L2_DREQ,
1155  	IONIC_PKT_CLS_PTP2_ALL		=
1156  		IONIC_PKT_CLS_PTP2_L4_ALL | IONIC_PKT_CLS_PTP2_L2_ALL,
1157  
1158  	IONIC_PKT_CLS_PTP_SYNC		=
1159  		IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP2_SYNC,
1160  	IONIC_PKT_CLS_PTP_DREQ		=
1161  		IONIC_PKT_CLS_PTP1_DREQ | IONIC_PKT_CLS_PTP2_DREQ,
1162  	IONIC_PKT_CLS_PTP_ALL		=
1163  		IONIC_PKT_CLS_PTP1_ALL | IONIC_PKT_CLS_PTP2_ALL,
1164  };
1165  
1166  /**
1167   * struct ionic_q_control_cmd - Queue control command
1168   * @opcode:     opcode
1169   * @type:       Queue type
1170   * @lif_index:  LIF index
1171   * @index:      Queue index
1172   * @oper:       Operation (enum ionic_q_control_oper)
1173   */
1174  struct ionic_q_control_cmd {
1175  	u8     opcode;
1176  	u8     type;
1177  	__le16 lif_index;
1178  	__le32 index;
1179  	u8     oper;
1180  	u8     rsvd[55];
1181  };
1182  
1183  typedef struct ionic_admin_comp ionic_q_control_comp;
1184  
1185  enum q_control_oper {
1186  	IONIC_Q_DISABLE		= 0,
1187  	IONIC_Q_ENABLE		= 1,
1188  	IONIC_Q_HANG_RESET	= 2,
1189  };
1190  
1191  /**
1192   * enum ionic_phy_type - Physical connection type
1193   * @IONIC_PHY_TYPE_NONE:    No PHY installed
1194   * @IONIC_PHY_TYPE_COPPER:  Copper PHY
1195   * @IONIC_PHY_TYPE_FIBER:   Fiber PHY
1196   */
1197  enum ionic_phy_type {
1198  	IONIC_PHY_TYPE_NONE	= 0,
1199  	IONIC_PHY_TYPE_COPPER	= 1,
1200  	IONIC_PHY_TYPE_FIBER	= 2,
1201  };
1202  
1203  /**
1204   * enum ionic_xcvr_state - Transceiver status
1205   * @IONIC_XCVR_STATE_REMOVED:        Transceiver removed
1206   * @IONIC_XCVR_STATE_INSERTED:       Transceiver inserted
1207   * @IONIC_XCVR_STATE_PENDING:        Transceiver pending
1208   * @IONIC_XCVR_STATE_SPROM_READ:     Transceiver data read
1209   * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error
1210   */
1211  enum ionic_xcvr_state {
1212  	IONIC_XCVR_STATE_REMOVED	 = 0,
1213  	IONIC_XCVR_STATE_INSERTED	 = 1,
1214  	IONIC_XCVR_STATE_PENDING	 = 2,
1215  	IONIC_XCVR_STATE_SPROM_READ	 = 3,
1216  	IONIC_XCVR_STATE_SPROM_READ_ERR	 = 4,
1217  };
1218  
1219  /**
1220   * enum ionic_xcvr_pid - Supported link modes
1221   */
1222  enum ionic_xcvr_pid {
1223  	IONIC_XCVR_PID_UNKNOWN           = 0,
1224  
1225  	/* CU */
1226  	IONIC_XCVR_PID_QSFP_100G_CR4     = 1,
1227  	IONIC_XCVR_PID_QSFP_40GBASE_CR4  = 2,
1228  	IONIC_XCVR_PID_SFP_25GBASE_CR_S  = 3,
1229  	IONIC_XCVR_PID_SFP_25GBASE_CR_L  = 4,
1230  	IONIC_XCVR_PID_SFP_25GBASE_CR_N  = 5,
1231  
1232  	/* Fiber */
1233  	IONIC_XCVR_PID_QSFP_100G_AOC    = 50,
1234  	IONIC_XCVR_PID_QSFP_100G_ACC    = 51,
1235  	IONIC_XCVR_PID_QSFP_100G_SR4    = 52,
1236  	IONIC_XCVR_PID_QSFP_100G_LR4    = 53,
1237  	IONIC_XCVR_PID_QSFP_100G_ER4    = 54,
1238  	IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55,
1239  	IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56,
1240  	IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57,
1241  	IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58,
1242  	IONIC_XCVR_PID_SFP_25GBASE_SR   = 59,
1243  	IONIC_XCVR_PID_SFP_25GBASE_LR   = 60,
1244  	IONIC_XCVR_PID_SFP_25GBASE_ER   = 61,
1245  	IONIC_XCVR_PID_SFP_25GBASE_AOC  = 62,
1246  	IONIC_XCVR_PID_SFP_10GBASE_SR   = 63,
1247  	IONIC_XCVR_PID_SFP_10GBASE_LR   = 64,
1248  	IONIC_XCVR_PID_SFP_10GBASE_LRM  = 65,
1249  	IONIC_XCVR_PID_SFP_10GBASE_ER   = 66,
1250  	IONIC_XCVR_PID_SFP_10GBASE_AOC  = 67,
1251  	IONIC_XCVR_PID_SFP_10GBASE_CU   = 68,
1252  	IONIC_XCVR_PID_QSFP_100G_CWDM4  = 69,
1253  	IONIC_XCVR_PID_QSFP_100G_PSM4   = 70,
1254  	IONIC_XCVR_PID_SFP_25GBASE_ACC  = 71,
1255  	IONIC_XCVR_PID_SFP_10GBASE_T    = 72,
1256  	IONIC_XCVR_PID_SFP_1000BASE_T   = 73,
1257  };
1258  
1259  /**
1260   * enum ionic_port_type - Port types
1261   * @IONIC_PORT_TYPE_NONE:           Port type not configured
1262   * @IONIC_PORT_TYPE_ETH:            Port carries ethernet traffic (inband)
1263   * @IONIC_PORT_TYPE_MGMT:           Port carries mgmt traffic (out-of-band)
1264   */
1265  enum ionic_port_type {
1266  	IONIC_PORT_TYPE_NONE = 0,
1267  	IONIC_PORT_TYPE_ETH  = 1,
1268  	IONIC_PORT_TYPE_MGMT = 2,
1269  };
1270  
1271  /**
1272   * enum ionic_port_admin_state - Port config state
1273   * @IONIC_PORT_ADMIN_STATE_NONE:    Port admin state not configured
1274   * @IONIC_PORT_ADMIN_STATE_DOWN:    Port admin disabled
1275   * @IONIC_PORT_ADMIN_STATE_UP:      Port admin enabled
1276   */
1277  enum ionic_port_admin_state {
1278  	IONIC_PORT_ADMIN_STATE_NONE = 0,
1279  	IONIC_PORT_ADMIN_STATE_DOWN = 1,
1280  	IONIC_PORT_ADMIN_STATE_UP   = 2,
1281  };
1282  
1283  /**
1284   * enum ionic_port_oper_status - Port operational status
1285   * @IONIC_PORT_OPER_STATUS_NONE:    Port disabled
1286   * @IONIC_PORT_OPER_STATUS_UP:      Port link status up
1287   * @IONIC_PORT_OPER_STATUS_DOWN:    Port link status down
1288   */
1289  enum ionic_port_oper_status {
1290  	IONIC_PORT_OPER_STATUS_NONE  = 0,
1291  	IONIC_PORT_OPER_STATUS_UP    = 1,
1292  	IONIC_PORT_OPER_STATUS_DOWN  = 2,
1293  };
1294  
1295  /**
1296   * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes
1297   * @IONIC_PORT_FEC_TYPE_NONE:       FEC Disabled
1298   * @IONIC_PORT_FEC_TYPE_FC:         FireCode FEC
1299   * @IONIC_PORT_FEC_TYPE_RS:         ReedSolomon FEC
1300   */
1301  enum ionic_port_fec_type {
1302  	IONIC_PORT_FEC_TYPE_NONE = 0,
1303  	IONIC_PORT_FEC_TYPE_FC   = 1,
1304  	IONIC_PORT_FEC_TYPE_RS   = 2,
1305  };
1306  
1307  /**
1308   * enum ionic_port_pause_type - Ethernet pause (flow control) modes
1309   * @IONIC_PORT_PAUSE_TYPE_NONE:     Disable Pause
1310   * @IONIC_PORT_PAUSE_TYPE_LINK:     Link level pause
1311   * @IONIC_PORT_PAUSE_TYPE_PFC:      Priority-Flow Control
1312   */
1313  enum ionic_port_pause_type {
1314  	IONIC_PORT_PAUSE_TYPE_NONE = 0,
1315  	IONIC_PORT_PAUSE_TYPE_LINK = 1,
1316  	IONIC_PORT_PAUSE_TYPE_PFC  = 2,
1317  };
1318  
1319  /**
1320   * enum ionic_port_loopback_mode - Loopback modes
1321   * @IONIC_PORT_LOOPBACK_MODE_NONE:  Disable loopback
1322   * @IONIC_PORT_LOOPBACK_MODE_MAC:   MAC loopback
1323   * @IONIC_PORT_LOOPBACK_MODE_PHY:   PHY/SerDes loopback
1324   */
1325  enum ionic_port_loopback_mode {
1326  	IONIC_PORT_LOOPBACK_MODE_NONE = 0,
1327  	IONIC_PORT_LOOPBACK_MODE_MAC  = 1,
1328  	IONIC_PORT_LOOPBACK_MODE_PHY  = 2,
1329  };
1330  
1331  /**
1332   * struct ionic_xcvr_status - Transceiver Status information
1333   * @state:    Transceiver status (enum ionic_xcvr_state)
1334   * @phy:      Physical connection type (enum ionic_phy_type)
1335   * @pid:      Transceiver link mode (enum ionic_xcvr_pid)
1336   * @sprom:    Transceiver sprom contents
1337   */
1338  struct ionic_xcvr_status {
1339  	u8     state;
1340  	u8     phy;
1341  	__le16 pid;
1342  	u8     sprom[256];
1343  };
1344  
1345  /**
1346   * union ionic_port_config - Port configuration
1347   * @speed:              port speed (in Mbps)
1348   * @mtu:                mtu
1349   * @state:              port admin state (enum ionic_port_admin_state)
1350   * @an_enable:          autoneg enable
1351   * @fec_type:           fec type (enum ionic_port_fec_type)
1352   * @pause_type:         pause type (enum ionic_port_pause_type)
1353   * @loopback_mode:      loopback mode (enum ionic_port_loopback_mode)
1354   */
1355  union ionic_port_config {
1356  	struct {
1357  #define IONIC_SPEED_100G	100000	/* 100G in Mbps */
1358  #define IONIC_SPEED_50G		50000	/* 50G in Mbps */
1359  #define IONIC_SPEED_40G		40000	/* 40G in Mbps */
1360  #define IONIC_SPEED_25G		25000	/* 25G in Mbps */
1361  #define IONIC_SPEED_10G		10000	/* 10G in Mbps */
1362  #define IONIC_SPEED_1G		1000	/* 1G in Mbps */
1363  		__le32 speed;
1364  		__le32 mtu;
1365  		u8     state;
1366  		u8     an_enable;
1367  		u8     fec_type;
1368  #define IONIC_PAUSE_TYPE_MASK		0x0f
1369  #define IONIC_PAUSE_FLAGS_MASK		0xf0
1370  #define IONIC_PAUSE_F_TX		0x10
1371  #define IONIC_PAUSE_F_RX		0x20
1372  		u8     pause_type;
1373  		u8     loopback_mode;
1374  	};
1375  	__le32 words[64];
1376  };
1377  
1378  /**
1379   * struct ionic_port_status - Port Status information
1380   * @status:             link status (enum ionic_port_oper_status)
1381   * @id:                 port id
1382   * @speed:              link speed (in Mbps)
1383   * @link_down_count:    number of times link went from up to down
1384   * @fec_type:           fec type (enum ionic_port_fec_type)
1385   * @xcvr:               transceiver status
1386   */
1387  struct ionic_port_status {
1388  	__le32 id;
1389  	__le32 speed;
1390  	u8     status;
1391  	__le16 link_down_count;
1392  	u8     fec_type;
1393  	u8     rsvd[48];
1394  	struct ionic_xcvr_status  xcvr;
1395  } __packed;
1396  
1397  /**
1398   * struct ionic_port_identify_cmd - Port identify command
1399   * @opcode:     opcode
1400   * @index:      port index
1401   * @ver:        Highest version of identify supported by driver
1402   */
1403  struct ionic_port_identify_cmd {
1404  	u8 opcode;
1405  	u8 index;
1406  	u8 ver;
1407  	u8 rsvd[61];
1408  };
1409  
1410  /**
1411   * struct ionic_port_identify_comp - Port identify command completion
1412   * @status: Status of the command (enum ionic_status_code)
1413   * @ver:    Version of identify returned by device
1414   */
1415  struct ionic_port_identify_comp {
1416  	u8 status;
1417  	u8 ver;
1418  	u8 rsvd[14];
1419  };
1420  
1421  /**
1422   * struct ionic_port_init_cmd - Port initialization command
1423   * @opcode:     opcode
1424   * @index:      port index
1425   * @info_pa:    destination address for port info (struct ionic_port_info)
1426   */
1427  struct ionic_port_init_cmd {
1428  	u8     opcode;
1429  	u8     index;
1430  	u8     rsvd[6];
1431  	__le64 info_pa;
1432  	u8     rsvd2[48];
1433  };
1434  
1435  /**
1436   * struct ionic_port_init_comp - Port initialization command completion
1437   * @status: Status of the command (enum ionic_status_code)
1438   */
1439  struct ionic_port_init_comp {
1440  	u8 status;
1441  	u8 rsvd[15];
1442  };
1443  
1444  /**
1445   * struct ionic_port_reset_cmd - Port reset command
1446   * @opcode:     opcode
1447   * @index:      port index
1448   */
1449  struct ionic_port_reset_cmd {
1450  	u8 opcode;
1451  	u8 index;
1452  	u8 rsvd[62];
1453  };
1454  
1455  /**
1456   * struct ionic_port_reset_comp - Port reset command completion
1457   * @status: Status of the command (enum ionic_status_code)
1458   */
1459  struct ionic_port_reset_comp {
1460  	u8 status;
1461  	u8 rsvd[15];
1462  };
1463  
1464  /**
1465   * enum ionic_stats_ctl_cmd - List of commands for stats control
1466   * @IONIC_STATS_CTL_RESET:      Reset statistics
1467   */
1468  enum ionic_stats_ctl_cmd {
1469  	IONIC_STATS_CTL_RESET		= 0,
1470  };
1471  
1472  /**
1473   * enum ionic_txstamp_mode - List of TX Timestamping Modes
1474   * @IONIC_TXSTAMP_OFF:           Disable TX hardware timetamping.
1475   * @IONIC_TXSTAMP_ON:            Enable local TX hardware timetamping.
1476   * @IONIC_TXSTAMP_ONESTEP_SYNC:  Modify TX PTP Sync packets.
1477   * @IONIC_TXSTAMP_ONESTEP_P2P:   Modify TX PTP Sync and PDelayResp.
1478   */
1479  enum ionic_txstamp_mode {
1480  	IONIC_TXSTAMP_OFF		= 0,
1481  	IONIC_TXSTAMP_ON		= 1,
1482  	IONIC_TXSTAMP_ONESTEP_SYNC	= 2,
1483  	IONIC_TXSTAMP_ONESTEP_P2P	= 3,
1484  };
1485  
1486  /**
1487   * enum ionic_port_attr - List of device attributes
1488   * @IONIC_PORT_ATTR_STATE:      Port state attribute
1489   * @IONIC_PORT_ATTR_SPEED:      Port speed attribute
1490   * @IONIC_PORT_ATTR_MTU:        Port MTU attribute
1491   * @IONIC_PORT_ATTR_AUTONEG:    Port autonegotiation attribute
1492   * @IONIC_PORT_ATTR_FEC:        Port FEC attribute
1493   * @IONIC_PORT_ATTR_PAUSE:      Port pause attribute
1494   * @IONIC_PORT_ATTR_LOOPBACK:   Port loopback attribute
1495   * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute
1496   */
1497  enum ionic_port_attr {
1498  	IONIC_PORT_ATTR_STATE		= 0,
1499  	IONIC_PORT_ATTR_SPEED		= 1,
1500  	IONIC_PORT_ATTR_MTU		= 2,
1501  	IONIC_PORT_ATTR_AUTONEG		= 3,
1502  	IONIC_PORT_ATTR_FEC		= 4,
1503  	IONIC_PORT_ATTR_PAUSE		= 5,
1504  	IONIC_PORT_ATTR_LOOPBACK	= 6,
1505  	IONIC_PORT_ATTR_STATS_CTRL	= 7,
1506  };
1507  
1508  /**
1509   * struct ionic_port_setattr_cmd - Set port attributes on the NIC
1510   * @opcode:         Opcode
1511   * @index:          Port index
1512   * @attr:           Attribute type (enum ionic_port_attr)
1513   * @state:          Port state
1514   * @speed:          Port speed
1515   * @mtu:            Port MTU
1516   * @an_enable:      Port autonegotiation setting
1517   * @fec_type:       Port FEC type setting
1518   * @pause_type:     Port pause type setting
1519   * @loopback_mode:  Port loopback mode
1520   * @stats_ctl:      Port stats setting
1521   */
1522  struct ionic_port_setattr_cmd {
1523  	u8     opcode;
1524  	u8     index;
1525  	u8     attr;
1526  	u8     rsvd;
1527  	union {
1528  		u8      state;
1529  		__le32  speed;
1530  		__le32  mtu;
1531  		u8      an_enable;
1532  		u8      fec_type;
1533  		u8      pause_type;
1534  		u8      loopback_mode;
1535  		u8      stats_ctl;
1536  		u8      rsvd2[60];
1537  	};
1538  };
1539  
1540  /**
1541   * struct ionic_port_setattr_comp - Port set attr command completion
1542   * @status:     Status of the command (enum ionic_status_code)
1543   * @color:      Color bit
1544   */
1545  struct ionic_port_setattr_comp {
1546  	u8     status;
1547  	u8     rsvd[14];
1548  	u8     color;
1549  };
1550  
1551  /**
1552   * struct ionic_port_getattr_cmd - Get port attributes from the NIC
1553   * @opcode:     Opcode
1554   * @index:      port index
1555   * @attr:       Attribute type (enum ionic_port_attr)
1556   */
1557  struct ionic_port_getattr_cmd {
1558  	u8     opcode;
1559  	u8     index;
1560  	u8     attr;
1561  	u8     rsvd[61];
1562  };
1563  
1564  /**
1565   * struct ionic_port_getattr_comp - Port get attr command completion
1566   * @status:         Status of the command (enum ionic_status_code)
1567   * @state:          Port state
1568   * @speed:          Port speed
1569   * @mtu:            Port MTU
1570   * @an_enable:      Port autonegotiation setting
1571   * @fec_type:       Port FEC type setting
1572   * @pause_type:     Port pause type setting
1573   * @loopback_mode:  Port loopback mode
1574   * @color:          Color bit
1575   */
1576  struct ionic_port_getattr_comp {
1577  	u8     status;
1578  	u8     rsvd[3];
1579  	union {
1580  		u8      state;
1581  		__le32  speed;
1582  		__le32  mtu;
1583  		u8      an_enable;
1584  		u8      fec_type;
1585  		u8      pause_type;
1586  		u8      loopback_mode;
1587  		u8      rsvd2[11];
1588  	} __packed;
1589  	u8     color;
1590  };
1591  
1592  /**
1593   * struct ionic_lif_status - LIF status register
1594   * @eid:             most recent NotifyQ event id
1595   * @port_num:        port the LIF is connected to
1596   * @link_status:     port status (enum ionic_port_oper_status)
1597   * @link_speed:      speed of link in Mbps
1598   * @link_down_count: number of times link went from up to down
1599   */
1600  struct ionic_lif_status {
1601  	__le64 eid;
1602  	u8     port_num;
1603  	u8     rsvd;
1604  	__le16 link_status;
1605  	__le32 link_speed;		/* units of 1Mbps: eg 10000 = 10Gbps */
1606  	__le16 link_down_count;
1607  	u8      rsvd2[46];
1608  };
1609  
1610  /**
1611   * struct ionic_lif_reset_cmd - LIF reset command
1612   * @opcode:    opcode
1613   * @index:     LIF index
1614   */
1615  struct ionic_lif_reset_cmd {
1616  	u8     opcode;
1617  	u8     rsvd;
1618  	__le16 index;
1619  	__le32 rsvd2[15];
1620  };
1621  
1622  typedef struct ionic_admin_comp ionic_lif_reset_comp;
1623  
1624  enum ionic_dev_state {
1625  	IONIC_DEV_DISABLE	= 0,
1626  	IONIC_DEV_ENABLE	= 1,
1627  	IONIC_DEV_HANG_RESET	= 2,
1628  };
1629  
1630  /**
1631   * enum ionic_dev_attr - List of device attributes
1632   * @IONIC_DEV_ATTR_STATE:     Device state attribute
1633   * @IONIC_DEV_ATTR_NAME:      Device name attribute
1634   * @IONIC_DEV_ATTR_FEATURES:  Device feature attributes
1635   */
1636  enum ionic_dev_attr {
1637  	IONIC_DEV_ATTR_STATE    = 0,
1638  	IONIC_DEV_ATTR_NAME     = 1,
1639  	IONIC_DEV_ATTR_FEATURES = 2,
1640  };
1641  
1642  /**
1643   * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC
1644   * @opcode:     Opcode
1645   * @attr:       Attribute type (enum ionic_dev_attr)
1646   * @state:      Device state (enum ionic_dev_state)
1647   * @name:       The bus info, e.g. PCI slot-device-function, 0 terminated
1648   * @features:   Device features
1649   */
1650  struct ionic_dev_setattr_cmd {
1651  	u8     opcode;
1652  	u8     attr;
1653  	__le16 rsvd;
1654  	union {
1655  		u8      state;
1656  		char    name[IONIC_IFNAMSIZ];
1657  		__le64  features;
1658  		u8      rsvd2[60];
1659  	} __packed;
1660  };
1661  
1662  /**
1663   * struct ionic_dev_setattr_comp - Device set attr command completion
1664   * @status:     Status of the command (enum ionic_status_code)
1665   * @features:   Device features
1666   * @color:      Color bit
1667   */
1668  struct ionic_dev_setattr_comp {
1669  	u8     status;
1670  	u8     rsvd[3];
1671  	union {
1672  		__le64  features;
1673  		u8      rsvd2[11];
1674  	} __packed;
1675  	u8     color;
1676  };
1677  
1678  /**
1679   * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC
1680   * @opcode:     opcode
1681   * @attr:       Attribute type (enum ionic_dev_attr)
1682   */
1683  struct ionic_dev_getattr_cmd {
1684  	u8     opcode;
1685  	u8     attr;
1686  	u8     rsvd[62];
1687  };
1688  
1689  /**
1690   * struct ionic_dev_setattr_comp - Device set attr command completion
1691   * @status:     Status of the command (enum ionic_status_code)
1692   * @features:   Device features
1693   * @color:      Color bit
1694   */
1695  struct ionic_dev_getattr_comp {
1696  	u8     status;
1697  	u8     rsvd[3];
1698  	union {
1699  		__le64  features;
1700  		u8      rsvd2[11];
1701  	} __packed;
1702  	u8     color;
1703  };
1704  
1705  /**
1706   * RSS parameters
1707   */
1708  #define IONIC_RSS_HASH_KEY_SIZE		40
1709  
1710  enum ionic_rss_hash_types {
1711  	IONIC_RSS_TYPE_IPV4	= BIT(0),
1712  	IONIC_RSS_TYPE_IPV4_TCP	= BIT(1),
1713  	IONIC_RSS_TYPE_IPV4_UDP	= BIT(2),
1714  	IONIC_RSS_TYPE_IPV6	= BIT(3),
1715  	IONIC_RSS_TYPE_IPV6_TCP	= BIT(4),
1716  	IONIC_RSS_TYPE_IPV6_UDP	= BIT(5),
1717  };
1718  
1719  /**
1720   * enum ionic_lif_attr - List of LIF attributes
1721   * @IONIC_LIF_ATTR_STATE:       LIF state attribute
1722   * @IONIC_LIF_ATTR_NAME:        LIF name attribute
1723   * @IONIC_LIF_ATTR_MTU:         LIF MTU attribute
1724   * @IONIC_LIF_ATTR_MAC:         LIF MAC attribute
1725   * @IONIC_LIF_ATTR_FEATURES:    LIF features attribute
1726   * @IONIC_LIF_ATTR_RSS:         LIF RSS attribute
1727   * @IONIC_LIF_ATTR_STATS_CTRL:  LIF statistics control attribute
1728   * @IONIC_LIF_ATTR_TXSTAMP:     LIF TX timestamping mode
1729   */
1730  enum ionic_lif_attr {
1731  	IONIC_LIF_ATTR_STATE        = 0,
1732  	IONIC_LIF_ATTR_NAME         = 1,
1733  	IONIC_LIF_ATTR_MTU          = 2,
1734  	IONIC_LIF_ATTR_MAC          = 3,
1735  	IONIC_LIF_ATTR_FEATURES     = 4,
1736  	IONIC_LIF_ATTR_RSS          = 5,
1737  	IONIC_LIF_ATTR_STATS_CTRL   = 6,
1738  	IONIC_LIF_ATTR_TXSTAMP      = 7,
1739  };
1740  
1741  /**
1742   * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC
1743   * @opcode:     Opcode
1744   * @attr:       Attribute type (enum ionic_lif_attr)
1745   * @index:      LIF index
1746   * @state:      LIF state (enum ionic_lif_state)
1747   * @name:       The netdev name string, 0 terminated
1748   * @mtu:        Mtu
1749   * @mac:        Station mac
1750   * @features:   Features (enum ionic_eth_hw_features)
1751   * @rss:        RSS properties
1752   *              @types:     The hash types to enable (see rss_hash_types)
1753   *              @key:       The hash secret key
1754   *              @addr:      Address for the indirection table shared memory
1755   * @stats_ctl:  stats control commands (enum ionic_stats_ctl_cmd)
1756   * @txstamp:    TX Timestamping Mode (enum ionic_txstamp_mode)
1757   */
1758  struct ionic_lif_setattr_cmd {
1759  	u8     opcode;
1760  	u8     attr;
1761  	__le16 index;
1762  	union {
1763  		u8      state;
1764  		char    name[IONIC_IFNAMSIZ];
1765  		__le32  mtu;
1766  		u8      mac[6];
1767  		__le64  features;
1768  		struct {
1769  			__le16 types;
1770  			u8     key[IONIC_RSS_HASH_KEY_SIZE];
1771  			u8     rsvd[6];
1772  			__le64 addr;
1773  		} rss;
1774  		u8      stats_ctl;
1775  		__le16 txstamp_mode;
1776  		u8      rsvd[60];
1777  	} __packed;
1778  };
1779  
1780  /**
1781   * struct ionic_lif_setattr_comp - LIF set attr command completion
1782   * @status:     Status of the command (enum ionic_status_code)
1783   * @comp_index: Index in the descriptor ring for which this is the completion
1784   * @features:   features (enum ionic_eth_hw_features)
1785   * @color:      Color bit
1786   */
1787  struct ionic_lif_setattr_comp {
1788  	u8     status;
1789  	u8     rsvd;
1790  	__le16 comp_index;
1791  	union {
1792  		__le64  features;
1793  		u8      rsvd2[11];
1794  	} __packed;
1795  	u8     color;
1796  };
1797  
1798  /**
1799   * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC
1800   * @opcode:     Opcode
1801   * @attr:       Attribute type (enum ionic_lif_attr)
1802   * @index:      LIF index
1803   */
1804  struct ionic_lif_getattr_cmd {
1805  	u8     opcode;
1806  	u8     attr;
1807  	__le16 index;
1808  	u8     rsvd[60];
1809  };
1810  
1811  /**
1812   * struct ionic_lif_getattr_comp - LIF get attr command completion
1813   * @status:     Status of the command (enum ionic_status_code)
1814   * @comp_index: Index in the descriptor ring for which this is the completion
1815   * @state:      LIF state (enum ionic_lif_state)
1816   * @name:       The netdev name string, 0 terminated
1817   * @mtu:        Mtu
1818   * @mac:        Station mac
1819   * @features:   Features (enum ionic_eth_hw_features)
1820   * @txstamp:    TX Timestamping Mode (enum ionic_txstamp_mode)
1821   * @color:      Color bit
1822   */
1823  struct ionic_lif_getattr_comp {
1824  	u8     status;
1825  	u8     rsvd;
1826  	__le16 comp_index;
1827  	union {
1828  		u8      state;
1829  		__le32  mtu;
1830  		u8      mac[6];
1831  		__le64  features;
1832  		__le16  txstamp_mode;
1833  		u8      rsvd2[11];
1834  	} __packed;
1835  	u8     color;
1836  };
1837  
1838  /**
1839   * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock
1840   * @opcode:     Opcode
1841   * @lif_index:  LIF index
1842   * @tick:       Hardware stamp tick of an instant in time.
1843   * @nsec:       Nanosecond stamp of the same instant.
1844   * @frac:       Fractional nanoseconds at the same instant.
1845   * @mult:       Cycle to nanosecond multiplier.
1846   * @shift:      Cycle to nanosecond divisor (power of two).
1847   */
1848  struct ionic_lif_setphc_cmd {
1849  	u8	opcode;
1850  	u8	rsvd1;
1851  	__le16  lif_index;
1852  	u8      rsvd2[4];
1853  	__le64	tick;
1854  	__le64	nsec;
1855  	__le64	frac;
1856  	__le32	mult;
1857  	__le32	shift;
1858  	u8     rsvd3[24];
1859  };
1860  
1861  enum ionic_rx_mode {
1862  	IONIC_RX_MODE_F_UNICAST		= BIT(0),
1863  	IONIC_RX_MODE_F_MULTICAST	= BIT(1),
1864  	IONIC_RX_MODE_F_BROADCAST	= BIT(2),
1865  	IONIC_RX_MODE_F_PROMISC		= BIT(3),
1866  	IONIC_RX_MODE_F_ALLMULTI	= BIT(4),
1867  	IONIC_RX_MODE_F_RDMA_SNIFFER	= BIT(5),
1868  };
1869  
1870  /**
1871   * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command
1872   * @opcode:     opcode
1873   * @lif_index:  LIF index
1874   * @rx_mode:    Rx mode flags:
1875   *                  IONIC_RX_MODE_F_UNICAST: Accept known unicast packets
1876   *                  IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets
1877   *                  IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets
1878   *                  IONIC_RX_MODE_F_PROMISC: Accept any packets
1879   *                  IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets
1880   *                  IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets
1881   */
1882  struct ionic_rx_mode_set_cmd {
1883  	u8     opcode;
1884  	u8     rsvd;
1885  	__le16 lif_index;
1886  	__le16 rx_mode;
1887  	__le16 rsvd2[29];
1888  };
1889  
1890  typedef struct ionic_admin_comp ionic_rx_mode_set_comp;
1891  
1892  enum ionic_rx_filter_match_type {
1893  	IONIC_RX_FILTER_MATCH_VLAN	= 0x0,
1894  	IONIC_RX_FILTER_MATCH_MAC	= 0x1,
1895  	IONIC_RX_FILTER_MATCH_MAC_VLAN	= 0x2,
1896  	IONIC_RX_FILTER_STEER_PKTCLASS	= 0x10,
1897  };
1898  
1899  /**
1900   * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command
1901   * @opcode:     opcode
1902   * @qtype:      Queue type
1903   * @lif_index:  LIF index
1904   * @qid:        Queue ID
1905   * @match:      Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx)
1906   * @vlan:       VLAN filter
1907   *              @vlan:  VLAN ID
1908   * @mac:        MAC filter
1909   *              @addr:  MAC address (network-byte order)
1910   * @mac_vlan:   MACVLAN filter
1911   *              @vlan:  VLAN ID
1912   *              @addr:  MAC address (network-byte order)
1913   * @pkt_class:  Packet classification filter
1914   */
1915  struct ionic_rx_filter_add_cmd {
1916  	u8     opcode;
1917  	u8     qtype;
1918  	__le16 lif_index;
1919  	__le32 qid;
1920  	__le16 match;
1921  	union {
1922  		struct {
1923  			__le16 vlan;
1924  		} vlan;
1925  		struct {
1926  			u8     addr[6];
1927  		} mac;
1928  		struct {
1929  			__le16 vlan;
1930  			u8     addr[6];
1931  		} mac_vlan;
1932  		__le64 pkt_class;
1933  		u8 rsvd[54];
1934  	} __packed;
1935  };
1936  
1937  /**
1938   * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion
1939   * @status:     Status of the command (enum ionic_status_code)
1940   * @comp_index: Index in the descriptor ring for which this is the completion
1941   * @filter_id:  Filter ID
1942   * @color:      Color bit
1943   */
1944  struct ionic_rx_filter_add_comp {
1945  	u8     status;
1946  	u8     rsvd;
1947  	__le16 comp_index;
1948  	__le32 filter_id;
1949  	u8     rsvd2[7];
1950  	u8     color;
1951  };
1952  
1953  /**
1954   * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command
1955   * @opcode:     opcode
1956   * @lif_index:  LIF index
1957   * @filter_id:  Filter ID
1958   */
1959  struct ionic_rx_filter_del_cmd {
1960  	u8     opcode;
1961  	u8     rsvd;
1962  	__le16 lif_index;
1963  	__le32 filter_id;
1964  	u8     rsvd2[56];
1965  };
1966  
1967  typedef struct ionic_admin_comp ionic_rx_filter_del_comp;
1968  
1969  enum ionic_vf_attr {
1970  	IONIC_VF_ATTR_SPOOFCHK	= 1,
1971  	IONIC_VF_ATTR_TRUST	= 2,
1972  	IONIC_VF_ATTR_MAC	= 3,
1973  	IONIC_VF_ATTR_LINKSTATE	= 4,
1974  	IONIC_VF_ATTR_VLAN	= 5,
1975  	IONIC_VF_ATTR_RATE	= 6,
1976  	IONIC_VF_ATTR_STATSADDR	= 7,
1977  };
1978  
1979  /**
1980   * enum ionic_vf_link_status - Virtual Function link status
1981   * @IONIC_VF_LINK_STATUS_AUTO:   Use link state of the uplink
1982   * @IONIC_VF_LINK_STATUS_UP:     Link always up
1983   * @IONIC_VF_LINK_STATUS_DOWN:   Link always down
1984   */
1985  enum ionic_vf_link_status {
1986  	IONIC_VF_LINK_STATUS_AUTO = 0,
1987  	IONIC_VF_LINK_STATUS_UP   = 1,
1988  	IONIC_VF_LINK_STATUS_DOWN = 2,
1989  };
1990  
1991  /**
1992   * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC
1993   * @opcode:     Opcode
1994   * @attr:       Attribute type (enum ionic_vf_attr)
1995   * @vf_index:   VF index
1996   *	@macaddr:	mac address
1997   *	@vlanid:	vlan ID
1998   *	@maxrate:	max Tx rate in Mbps
1999   *	@spoofchk:	enable address spoof checking
2000   *	@trust:		enable VF trust
2001   *	@linkstate:	set link up or down
2002   *	@stats_pa:	set DMA address for VF stats
2003   */
2004  struct ionic_vf_setattr_cmd {
2005  	u8     opcode;
2006  	u8     attr;
2007  	__le16 vf_index;
2008  	union {
2009  		u8     macaddr[6];
2010  		__le16 vlanid;
2011  		__le32 maxrate;
2012  		u8     spoofchk;
2013  		u8     trust;
2014  		u8     linkstate;
2015  		__le64 stats_pa;
2016  		u8     pad[60];
2017  	} __packed;
2018  };
2019  
2020  struct ionic_vf_setattr_comp {
2021  	u8     status;
2022  	u8     attr;
2023  	__le16 vf_index;
2024  	__le16 comp_index;
2025  	u8     rsvd[9];
2026  	u8     color;
2027  };
2028  
2029  /**
2030   * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC
2031   * @opcode:     Opcode
2032   * @attr:       Attribute type (enum ionic_vf_attr)
2033   * @vf_index:   VF index
2034   */
2035  struct ionic_vf_getattr_cmd {
2036  	u8     opcode;
2037  	u8     attr;
2038  	__le16 vf_index;
2039  	u8     rsvd[60];
2040  };
2041  
2042  struct ionic_vf_getattr_comp {
2043  	u8     status;
2044  	u8     attr;
2045  	__le16 vf_index;
2046  	union {
2047  		u8     macaddr[6];
2048  		__le16 vlanid;
2049  		__le32 maxrate;
2050  		u8     spoofchk;
2051  		u8     trust;
2052  		u8     linkstate;
2053  		__le64 stats_pa;
2054  		u8     pad[11];
2055  	} __packed;
2056  	u8     color;
2057  };
2058  
2059  enum ionic_vf_ctrl_opcode {
2060  	IONIC_VF_CTRL_START_ALL	= 0,
2061  	IONIC_VF_CTRL_START	= 1,
2062  };
2063  
2064  /**
2065   * struct ionic_vf_ctrl_cmd - VF control command
2066   * @opcode:         Opcode for the command
2067   * @vf_index:       VF Index. It is unused if op START_ALL is used.
2068   * @ctrl_opcode:    VF control operation type
2069   */
2070  struct ionic_vf_ctrl_cmd {
2071  	u8	opcode;
2072  	u8	ctrl_opcode;
2073  	__le16	vf_index;
2074  	/* private: */
2075  	u8	rsvd1[60];
2076  };
2077  
2078  /**
2079   * struct ionic_vf_ctrl_comp - VF_CTRL command completion.
2080   * @status:     Status of the command (enum ionic_status_code)
2081   */
2082  struct ionic_vf_ctrl_comp {
2083  	u8	status;
2084  	/* private: */
2085  	u8      rsvd[15];
2086  };
2087  
2088  /**
2089   * struct ionic_qos_identify_cmd - QoS identify command
2090   * @opcode:  opcode
2091   * @ver:     Highest version of identify supported by driver
2092   *
2093   */
2094  struct ionic_qos_identify_cmd {
2095  	u8 opcode;
2096  	u8 ver;
2097  	u8 rsvd[62];
2098  };
2099  
2100  /**
2101   * struct ionic_qos_identify_comp - QoS identify command completion
2102   * @status: Status of the command (enum ionic_status_code)
2103   * @ver:    Version of identify returned by device
2104   */
2105  struct ionic_qos_identify_comp {
2106  	u8 status;
2107  	u8 ver;
2108  	u8 rsvd[14];
2109  };
2110  
2111  #define IONIC_QOS_TC_MAX		8
2112  #define IONIC_QOS_ALL_TC		0xFF
2113  /* Capri max supported, should be renamed. */
2114  #define IONIC_QOS_CLASS_MAX		7
2115  #define IONIC_QOS_PCP_MAX		8
2116  #define IONIC_QOS_CLASS_NAME_SZ	32
2117  #define IONIC_QOS_DSCP_MAX		64
2118  #define IONIC_QOS_ALL_PCP		0xFF
2119  #define IONIC_DSCP_BLOCK_SIZE		8
2120  
2121  /**
2122   * enum ionic_qos_class
2123   */
2124  enum ionic_qos_class {
2125  	IONIC_QOS_CLASS_DEFAULT		= 0,
2126  	IONIC_QOS_CLASS_USER_DEFINED_1	= 1,
2127  	IONIC_QOS_CLASS_USER_DEFINED_2	= 2,
2128  	IONIC_QOS_CLASS_USER_DEFINED_3	= 3,
2129  	IONIC_QOS_CLASS_USER_DEFINED_4	= 4,
2130  	IONIC_QOS_CLASS_USER_DEFINED_5	= 5,
2131  	IONIC_QOS_CLASS_USER_DEFINED_6	= 6,
2132  };
2133  
2134  /**
2135   * enum ionic_qos_class_type - Traffic classification criteria
2136   * @IONIC_QOS_CLASS_TYPE_NONE:    No QoS
2137   * @IONIC_QOS_CLASS_TYPE_PCP:     Dot1Q PCP
2138   * @IONIC_QOS_CLASS_TYPE_DSCP:    IP DSCP
2139   */
2140  enum ionic_qos_class_type {
2141  	IONIC_QOS_CLASS_TYPE_NONE	= 0,
2142  	IONIC_QOS_CLASS_TYPE_PCP	= 1,
2143  	IONIC_QOS_CLASS_TYPE_DSCP	= 2,
2144  };
2145  
2146  /**
2147   * enum ionic_qos_sched_type - QoS class scheduling type
2148   * @IONIC_QOS_SCHED_TYPE_STRICT:  Strict priority
2149   * @IONIC_QOS_SCHED_TYPE_DWRR:    Deficit weighted round-robin
2150   */
2151  enum ionic_qos_sched_type {
2152  	IONIC_QOS_SCHED_TYPE_STRICT	= 0,
2153  	IONIC_QOS_SCHED_TYPE_DWRR	= 1,
2154  };
2155  
2156  /**
2157   * union ionic_qos_config - QoS configuration structure
2158   * @flags:		Configuration flags
2159   *	IONIC_QOS_CONFIG_F_ENABLE		enable
2160   *	IONIC_QOS_CONFIG_F_NO_DROP		drop/nodrop
2161   *	IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP		enable dot1q pcp rewrite
2162   *	IONIC_QOS_CONFIG_F_RW_IP_DSCP		enable ip dscp rewrite
2163   *	IONIC_QOS_CONFIG_F_NON_DISRUPTIVE	Non-disruptive TC update
2164   * @sched_type:		QoS class scheduling type (enum ionic_qos_sched_type)
2165   * @class_type:		QoS class type (enum ionic_qos_class_type)
2166   * @pause_type:		QoS pause type (enum ionic_qos_pause_type)
2167   * @name:		QoS class name
2168   * @mtu:		MTU of the class
2169   * @pfc_cos:		Priority-Flow Control class of service
2170   * @dwrr_weight:	QoS class scheduling weight
2171   * @strict_rlmt:	Rate limit for strict priority scheduling
2172   * @rw_dot1q_pcp:	Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP)
2173   * @rw_ip_dscp:		Rewrite ip dscp to value (valid iff F_RW_IP_DSCP)
2174   * @dot1q_pcp:		Dot1q pcp value
2175   * @ndscp:		Number of valid dscp values in the ip_dscp field
2176   * @ip_dscp:		IP dscp values
2177   */
2178  union ionic_qos_config {
2179  	struct {
2180  #define IONIC_QOS_CONFIG_F_ENABLE		BIT(0)
2181  #define IONIC_QOS_CONFIG_F_NO_DROP		BIT(1)
2182  /* Used to rewrite PCP or DSCP value. */
2183  #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP		BIT(2)
2184  #define IONIC_QOS_CONFIG_F_RW_IP_DSCP		BIT(3)
2185  /* Non-disruptive TC update */
2186  #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE	BIT(4)
2187  		u8      flags;
2188  		u8      sched_type;
2189  		u8      class_type;
2190  		u8      pause_type;
2191  		char    name[IONIC_QOS_CLASS_NAME_SZ];
2192  		__le32  mtu;
2193  		/* flow control */
2194  		u8      pfc_cos;
2195  		/* scheduler */
2196  		union {
2197  			u8      dwrr_weight;
2198  			__le64  strict_rlmt;
2199  		};
2200  		/* marking */
2201  		/* Used to rewrite PCP or DSCP value. */
2202  		union {
2203  			u8      rw_dot1q_pcp;
2204  			u8      rw_ip_dscp;
2205  		};
2206  		/* classification */
2207  		union {
2208  			u8      dot1q_pcp;
2209  			struct {
2210  				u8      ndscp;
2211  				u8      ip_dscp[IONIC_QOS_DSCP_MAX];
2212  			};
2213  		};
2214  	};
2215  	__le32  words[64];
2216  };
2217  
2218  /**
2219   * union ionic_qos_identity - QoS identity structure
2220   * @version:	Version of the identify structure
2221   * @type:	QoS system type
2222   * @nclasses:	Number of usable QoS classes
2223   * @config:	Current configuration of classes
2224   */
2225  union ionic_qos_identity {
2226  	struct {
2227  		u8     version;
2228  		u8     type;
2229  		u8     rsvd[62];
2230  		union ionic_qos_config config[IONIC_QOS_CLASS_MAX];
2231  	};
2232  	__le32 words[478];
2233  };
2234  
2235  /**
2236   * struct ionic_qos_init_cmd - QoS config init command
2237   * @opcode:	Opcode
2238   * @group:	QoS class id
2239   * @info_pa:	destination address for qos info
2240   */
2241  struct ionic_qos_init_cmd {
2242  	u8     opcode;
2243  	u8     group;
2244  	u8     rsvd[6];
2245  	__le64 info_pa;
2246  	u8     rsvd1[48];
2247  };
2248  
2249  typedef struct ionic_admin_comp ionic_qos_init_comp;
2250  
2251  /**
2252   * struct ionic_qos_reset_cmd - QoS config reset command
2253   * @opcode:	Opcode
2254   * @group:	QoS class id
2255   */
2256  struct ionic_qos_reset_cmd {
2257  	u8    opcode;
2258  	u8    group;
2259  	u8    rsvd[62];
2260  };
2261  
2262  /**
2263   * struct ionic_qos_clear_port_stats_cmd - Qos config reset command
2264   * @opcode:	Opcode
2265   */
2266  struct ionic_qos_clear_stats_cmd {
2267  	u8    opcode;
2268  	u8    group_bitmap;
2269  	u8    rsvd[62];
2270  };
2271  
2272  typedef struct ionic_admin_comp ionic_qos_reset_comp;
2273  
2274  /**
2275   * struct ionic_fw_download_cmd - Firmware download command
2276   * @opcode:	opcode
2277   * @addr:	dma address of the firmware buffer
2278   * @offset:	offset of the firmware buffer within the full image
2279   * @length:	number of valid bytes in the firmware buffer
2280   */
2281  struct ionic_fw_download_cmd {
2282  	u8     opcode;
2283  	u8     rsvd[3];
2284  	__le32 offset;
2285  	__le64 addr;
2286  	__le32 length;
2287  };
2288  
2289  typedef struct ionic_admin_comp ionic_fw_download_comp;
2290  
2291  /**
2292   * enum ionic_fw_control_oper - FW control operations
2293   * @IONIC_FW_RESET:		Reset firmware
2294   * @IONIC_FW_INSTALL:		Install firmware
2295   * @IONIC_FW_ACTIVATE:		Activate firmware
2296   * @IONIC_FW_INSTALL_ASYNC:	Install firmware asynchronously
2297   * @IONIC_FW_INSTALL_STATUS:	Firmware installation status
2298   * @IONIC_FW_ACTIVATE_ASYNC:	Activate firmware asynchronously
2299   * @IONIC_FW_ACTIVATE_STATUS:	Firmware activate status
2300   */
2301  enum ionic_fw_control_oper {
2302  	IONIC_FW_RESET			= 0,
2303  	IONIC_FW_INSTALL		= 1,
2304  	IONIC_FW_ACTIVATE		= 2,
2305  	IONIC_FW_INSTALL_ASYNC		= 3,
2306  	IONIC_FW_INSTALL_STATUS		= 4,
2307  	IONIC_FW_ACTIVATE_ASYNC		= 5,
2308  	IONIC_FW_ACTIVATE_STATUS	= 6,
2309  	IONIC_FW_UPDATE_CLEANUP		= 7,
2310  };
2311  
2312  /**
2313   * struct ionic_fw_control_cmd - Firmware control command
2314   * @opcode:    opcode
2315   * @oper:      firmware control operation (enum ionic_fw_control_oper)
2316   * @slot:      slot to activate
2317   */
2318  struct ionic_fw_control_cmd {
2319  	u8  opcode;
2320  	u8  rsvd[3];
2321  	u8  oper;
2322  	u8  slot;
2323  	u8  rsvd1[58];
2324  };
2325  
2326  /**
2327   * struct ionic_fw_control_comp - Firmware control copletion
2328   * @status:     Status of the command (enum ionic_status_code)
2329   * @comp_index: Index in the descriptor ring for which this is the completion
2330   * @slot:       Slot where the firmware was installed
2331   * @color:      Color bit
2332   */
2333  struct ionic_fw_control_comp {
2334  	u8     status;
2335  	u8     rsvd;
2336  	__le16 comp_index;
2337  	u8     slot;
2338  	u8     rsvd1[10];
2339  	u8     color;
2340  };
2341  
2342  /******************************************************************
2343   ******************* RDMA Commands ********************************
2344   ******************************************************************/
2345  
2346  /**
2347   * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd
2348   * @opcode:        opcode
2349   * @lif_index:     LIF index
2350   *
2351   * There is no RDMA specific dev command completion struct.  Completion uses
2352   * the common struct ionic_admin_comp.  Only the status is indicated.
2353   * Nonzero status means the LIF does not support RDMA.
2354   **/
2355  struct ionic_rdma_reset_cmd {
2356  	u8     opcode;
2357  	u8     rsvd;
2358  	__le16 lif_index;
2359  	u8     rsvd2[60];
2360  };
2361  
2362  /**
2363   * struct ionic_rdma_queue_cmd - Create RDMA Queue command
2364   * @opcode:        opcode, 52, 53
2365   * @lif_index:     LIF index
2366   * @qid_ver:       (qid | (RDMA version << 24))
2367   * @cid:           intr, eq_id, or cq_id
2368   * @dbid:          doorbell page id
2369   * @depth_log2:    log base two of queue depth
2370   * @stride_log2:   log base two of queue stride
2371   * @dma_addr:      address of the queue memory
2372   *
2373   * The same command struct is used to create an RDMA event queue, completion
2374   * queue, or RDMA admin queue.  The cid is an interrupt number for an event
2375   * queue, an event queue id for a completion queue, or a completion queue id
2376   * for an RDMA admin queue.
2377   *
2378   * The queue created via a dev command must be contiguous in dma space.
2379   *
2380   * The dev commands are intended only to be used during driver initialization,
2381   * to create queues supporting the RDMA admin queue.  Other queues, and other
2382   * types of RDMA resources like memory regions, will be created and registered
2383   * via the RDMA admin queue, and will support a more complete interface
2384   * providing scatter gather lists for larger, scattered queue buffers and
2385   * memory registration.
2386   *
2387   * There is no RDMA specific dev command completion struct.  Completion uses
2388   * the common struct ionic_admin_comp.  Only the status is indicated.
2389   **/
2390  struct ionic_rdma_queue_cmd {
2391  	u8     opcode;
2392  	u8     rsvd;
2393  	__le16 lif_index;
2394  	__le32 qid_ver;
2395  	__le32 cid;
2396  	__le16 dbid;
2397  	u8     depth_log2;
2398  	u8     stride_log2;
2399  	__le64 dma_addr;
2400  	u8     rsvd2[40];
2401  };
2402  
2403  /******************************************************************
2404   ******************* Notify Events ********************************
2405   ******************************************************************/
2406  
2407  /**
2408   * struct ionic_notifyq_event - Generic event reporting structure
2409   * @eid:   event number
2410   * @ecode: event code
2411   * @data:  unspecified data about the event
2412   *
2413   * This is the generic event report struct from which the other
2414   * actual events will be formed.
2415   */
2416  struct ionic_notifyq_event {
2417  	__le64 eid;
2418  	__le16 ecode;
2419  	u8     data[54];
2420  };
2421  
2422  /**
2423   * struct ionic_link_change_event - Link change event notification
2424   * @eid:		event number
2425   * @ecode:		event code = IONIC_EVENT_LINK_CHANGE
2426   * @link_status:	link up/down, with error bits (enum ionic_port_status)
2427   * @link_speed:		speed of the network link
2428   *
2429   * Sent when the network link state changes between UP and DOWN
2430   */
2431  struct ionic_link_change_event {
2432  	__le64 eid;
2433  	__le16 ecode;
2434  	__le16 link_status;
2435  	__le32 link_speed;	/* units of 1Mbps: e.g. 10000 = 10Gbps */
2436  	u8     rsvd[48];
2437  };
2438  
2439  /**
2440   * struct ionic_reset_event - Reset event notification
2441   * @eid:		event number
2442   * @ecode:		event code = IONIC_EVENT_RESET
2443   * @reset_code:		reset type
2444   * @state:		0=pending, 1=complete, 2=error
2445   *
2446   * Sent when the NIC or some subsystem is going to be or
2447   * has been reset.
2448   */
2449  struct ionic_reset_event {
2450  	__le64 eid;
2451  	__le16 ecode;
2452  	u8     reset_code;
2453  	u8     state;
2454  	u8     rsvd[52];
2455  };
2456  
2457  /**
2458   * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health
2459   * @eid:	event number
2460   * @ecode:	event code = IONIC_EVENT_HEARTBEAT
2461   */
2462  struct ionic_heartbeat_event {
2463  	__le64 eid;
2464  	__le16 ecode;
2465  	u8     rsvd[54];
2466  };
2467  
2468  /**
2469   * struct ionic_log_event - Sent to notify the driver of an internal error
2470   * @eid:	event number
2471   * @ecode:	event code = IONIC_EVENT_LOG
2472   * @data:	log data
2473   */
2474  struct ionic_log_event {
2475  	__le64 eid;
2476  	__le16 ecode;
2477  	u8     data[54];
2478  };
2479  
2480  /**
2481   * struct ionic_xcvr_event - Transceiver change event
2482   * @eid:	event number
2483   * @ecode:	event code = IONIC_EVENT_XCVR
2484   */
2485  struct ionic_xcvr_event {
2486  	__le64 eid;
2487  	__le16 ecode;
2488  	u8     rsvd[54];
2489  };
2490  
2491  /**
2492   * struct ionic_port_stats - Port statistics structure
2493   */
2494  struct ionic_port_stats {
2495  	__le64 frames_rx_ok;
2496  	__le64 frames_rx_all;
2497  	__le64 frames_rx_bad_fcs;
2498  	__le64 frames_rx_bad_all;
2499  	__le64 octets_rx_ok;
2500  	__le64 octets_rx_all;
2501  	__le64 frames_rx_unicast;
2502  	__le64 frames_rx_multicast;
2503  	__le64 frames_rx_broadcast;
2504  	__le64 frames_rx_pause;
2505  	__le64 frames_rx_bad_length;
2506  	__le64 frames_rx_undersized;
2507  	__le64 frames_rx_oversized;
2508  	__le64 frames_rx_fragments;
2509  	__le64 frames_rx_jabber;
2510  	__le64 frames_rx_pripause;
2511  	__le64 frames_rx_stomped_crc;
2512  	__le64 frames_rx_too_long;
2513  	__le64 frames_rx_vlan_good;
2514  	__le64 frames_rx_dropped;
2515  	__le64 frames_rx_less_than_64b;
2516  	__le64 frames_rx_64b;
2517  	__le64 frames_rx_65b_127b;
2518  	__le64 frames_rx_128b_255b;
2519  	__le64 frames_rx_256b_511b;
2520  	__le64 frames_rx_512b_1023b;
2521  	__le64 frames_rx_1024b_1518b;
2522  	__le64 frames_rx_1519b_2047b;
2523  	__le64 frames_rx_2048b_4095b;
2524  	__le64 frames_rx_4096b_8191b;
2525  	__le64 frames_rx_8192b_9215b;
2526  	__le64 frames_rx_other;
2527  	__le64 frames_tx_ok;
2528  	__le64 frames_tx_all;
2529  	__le64 frames_tx_bad;
2530  	__le64 octets_tx_ok;
2531  	__le64 octets_tx_total;
2532  	__le64 frames_tx_unicast;
2533  	__le64 frames_tx_multicast;
2534  	__le64 frames_tx_broadcast;
2535  	__le64 frames_tx_pause;
2536  	__le64 frames_tx_pripause;
2537  	__le64 frames_tx_vlan;
2538  	__le64 frames_tx_less_than_64b;
2539  	__le64 frames_tx_64b;
2540  	__le64 frames_tx_65b_127b;
2541  	__le64 frames_tx_128b_255b;
2542  	__le64 frames_tx_256b_511b;
2543  	__le64 frames_tx_512b_1023b;
2544  	__le64 frames_tx_1024b_1518b;
2545  	__le64 frames_tx_1519b_2047b;
2546  	__le64 frames_tx_2048b_4095b;
2547  	__le64 frames_tx_4096b_8191b;
2548  	__le64 frames_tx_8192b_9215b;
2549  	__le64 frames_tx_other;
2550  	__le64 frames_tx_pri_0;
2551  	__le64 frames_tx_pri_1;
2552  	__le64 frames_tx_pri_2;
2553  	__le64 frames_tx_pri_3;
2554  	__le64 frames_tx_pri_4;
2555  	__le64 frames_tx_pri_5;
2556  	__le64 frames_tx_pri_6;
2557  	__le64 frames_tx_pri_7;
2558  	__le64 frames_rx_pri_0;
2559  	__le64 frames_rx_pri_1;
2560  	__le64 frames_rx_pri_2;
2561  	__le64 frames_rx_pri_3;
2562  	__le64 frames_rx_pri_4;
2563  	__le64 frames_rx_pri_5;
2564  	__le64 frames_rx_pri_6;
2565  	__le64 frames_rx_pri_7;
2566  	__le64 tx_pripause_0_1us_count;
2567  	__le64 tx_pripause_1_1us_count;
2568  	__le64 tx_pripause_2_1us_count;
2569  	__le64 tx_pripause_3_1us_count;
2570  	__le64 tx_pripause_4_1us_count;
2571  	__le64 tx_pripause_5_1us_count;
2572  	__le64 tx_pripause_6_1us_count;
2573  	__le64 tx_pripause_7_1us_count;
2574  	__le64 rx_pripause_0_1us_count;
2575  	__le64 rx_pripause_1_1us_count;
2576  	__le64 rx_pripause_2_1us_count;
2577  	__le64 rx_pripause_3_1us_count;
2578  	__le64 rx_pripause_4_1us_count;
2579  	__le64 rx_pripause_5_1us_count;
2580  	__le64 rx_pripause_6_1us_count;
2581  	__le64 rx_pripause_7_1us_count;
2582  	__le64 rx_pause_1us_count;
2583  	__le64 frames_tx_truncated;
2584  };
2585  
2586  struct ionic_mgmt_port_stats {
2587  	__le64 frames_rx_ok;
2588  	__le64 frames_rx_all;
2589  	__le64 frames_rx_bad_fcs;
2590  	__le64 frames_rx_bad_all;
2591  	__le64 octets_rx_ok;
2592  	__le64 octets_rx_all;
2593  	__le64 frames_rx_unicast;
2594  	__le64 frames_rx_multicast;
2595  	__le64 frames_rx_broadcast;
2596  	__le64 frames_rx_pause;
2597  	__le64 frames_rx_bad_length;
2598  	__le64 frames_rx_undersized;
2599  	__le64 frames_rx_oversized;
2600  	__le64 frames_rx_fragments;
2601  	__le64 frames_rx_jabber;
2602  	__le64 frames_rx_64b;
2603  	__le64 frames_rx_65b_127b;
2604  	__le64 frames_rx_128b_255b;
2605  	__le64 frames_rx_256b_511b;
2606  	__le64 frames_rx_512b_1023b;
2607  	__le64 frames_rx_1024b_1518b;
2608  	__le64 frames_rx_gt_1518b;
2609  	__le64 frames_rx_fifo_full;
2610  	__le64 frames_tx_ok;
2611  	__le64 frames_tx_all;
2612  	__le64 frames_tx_bad;
2613  	__le64 octets_tx_ok;
2614  	__le64 octets_tx_total;
2615  	__le64 frames_tx_unicast;
2616  	__le64 frames_tx_multicast;
2617  	__le64 frames_tx_broadcast;
2618  	__le64 frames_tx_pause;
2619  };
2620  
2621  enum ionic_pb_buffer_drop_stats {
2622  	IONIC_BUFFER_INTRINSIC_DROP = 0,
2623  	IONIC_BUFFER_DISCARDED,
2624  	IONIC_BUFFER_ADMITTED,
2625  	IONIC_BUFFER_OUT_OF_CELLS_DROP,
2626  	IONIC_BUFFER_OUT_OF_CELLS_DROP_2,
2627  	IONIC_BUFFER_OUT_OF_CREDIT_DROP,
2628  	IONIC_BUFFER_TRUNCATION_DROP,
2629  	IONIC_BUFFER_PORT_DISABLED_DROP,
2630  	IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP,
2631  	IONIC_BUFFER_SPAN_TAIL_DROP,
2632  	IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP,
2633  	IONIC_BUFFER_ENQUEUE_ERROR_DROP,
2634  	IONIC_BUFFER_INVALID_PORT_DROP,
2635  	IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP,
2636  	IONIC_BUFFER_DROP_MAX,
2637  };
2638  
2639  enum ionic_oflow_drop_stats {
2640  	IONIC_OFLOW_OCCUPANCY_DROP,
2641  	IONIC_OFLOW_EMERGENCY_STOP_DROP,
2642  	IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP,
2643  	IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP,
2644  	IONIC_OFLOW_WRITE_BUFFER_FULL_DROP,
2645  	IONIC_OFLOW_CONTROL_FIFO_FULL_DROP,
2646  	IONIC_OFLOW_DROP_MAX,
2647  };
2648  
2649  /**
2650   * struct port_pb_stats - packet buffers system stats
2651   * uses ionic_pb_buffer_drop_stats for drop_counts[]
2652   */
2653  struct ionic_port_pb_stats {
2654  	__le64 sop_count_in;
2655  	__le64 eop_count_in;
2656  	__le64 sop_count_out;
2657  	__le64 eop_count_out;
2658  	__le64 drop_counts[IONIC_BUFFER_DROP_MAX];
2659  	__le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2660  	__le64 input_queue_port_monitor[IONIC_QOS_TC_MAX];
2661  	__le64 output_queue_port_monitor[IONIC_QOS_TC_MAX];
2662  	__le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX];
2663  	__le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX];
2664  	__le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX];
2665  	__le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX];
2666  	__le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX];
2667  	__le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX];
2668  	__le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX];
2669  	__le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2670  };
2671  
2672  /**
2673   * struct ionic_port_identity - port identity structure
2674   * @version:        identity structure version
2675   * @type:           type of port (enum ionic_port_type)
2676   * @num_lanes:      number of lanes for the port
2677   * @autoneg:        autoneg supported
2678   * @min_frame_size: minimum frame size supported
2679   * @max_frame_size: maximum frame size supported
2680   * @fec_type:       supported fec types
2681   * @pause_type:     supported pause types
2682   * @loopback_mode:  supported loopback mode
2683   * @speeds:         supported speeds
2684   * @config:         current port configuration
2685   */
2686  union ionic_port_identity {
2687  	struct {
2688  		u8     version;
2689  		u8     type;
2690  		u8     num_lanes;
2691  		u8     autoneg;
2692  		__le32 min_frame_size;
2693  		__le32 max_frame_size;
2694  		u8     fec_type[4];
2695  		u8     pause_type[2];
2696  		u8     loopback_mode[2];
2697  		__le32 speeds[16];
2698  		u8     rsvd2[44];
2699  		union ionic_port_config config;
2700  	};
2701  	__le32 words[478];
2702  };
2703  
2704  /**
2705   * struct ionic_port_info - port info structure
2706   * @config:          Port configuration data
2707   * @status:          Port status data
2708   * @stats:           Port statistics data
2709   * @mgmt_stats:      Port management statistics data
2710   * @port_pb_drop_stats:   uplink pb drop stats
2711   */
2712  struct ionic_port_info {
2713  	union ionic_port_config config;
2714  	struct ionic_port_status status;
2715  	union {
2716  		struct ionic_port_stats      stats;
2717  		struct ionic_mgmt_port_stats mgmt_stats;
2718  	};
2719  	/* room for pb_stats to start at 2k offset */
2720  	u8                          rsvd[760];
2721  	struct ionic_port_pb_stats  pb_stats;
2722  };
2723  
2724  /**
2725   * struct ionic_lif_stats - LIF statistics structure
2726   */
2727  struct ionic_lif_stats {
2728  	/* RX */
2729  	__le64 rx_ucast_bytes;
2730  	__le64 rx_ucast_packets;
2731  	__le64 rx_mcast_bytes;
2732  	__le64 rx_mcast_packets;
2733  	__le64 rx_bcast_bytes;
2734  	__le64 rx_bcast_packets;
2735  	__le64 rsvd0;
2736  	__le64 rsvd1;
2737  	/* RX drops */
2738  	__le64 rx_ucast_drop_bytes;
2739  	__le64 rx_ucast_drop_packets;
2740  	__le64 rx_mcast_drop_bytes;
2741  	__le64 rx_mcast_drop_packets;
2742  	__le64 rx_bcast_drop_bytes;
2743  	__le64 rx_bcast_drop_packets;
2744  	__le64 rx_dma_error;
2745  	__le64 rsvd2;
2746  	/* TX */
2747  	__le64 tx_ucast_bytes;
2748  	__le64 tx_ucast_packets;
2749  	__le64 tx_mcast_bytes;
2750  	__le64 tx_mcast_packets;
2751  	__le64 tx_bcast_bytes;
2752  	__le64 tx_bcast_packets;
2753  	__le64 rsvd3;
2754  	__le64 rsvd4;
2755  	/* TX drops */
2756  	__le64 tx_ucast_drop_bytes;
2757  	__le64 tx_ucast_drop_packets;
2758  	__le64 tx_mcast_drop_bytes;
2759  	__le64 tx_mcast_drop_packets;
2760  	__le64 tx_bcast_drop_bytes;
2761  	__le64 tx_bcast_drop_packets;
2762  	__le64 tx_dma_error;
2763  	__le64 rsvd5;
2764  	/* Rx Queue/Ring drops */
2765  	__le64 rx_queue_disabled;
2766  	__le64 rx_queue_empty;
2767  	__le64 rx_queue_error;
2768  	__le64 rx_desc_fetch_error;
2769  	__le64 rx_desc_data_error;
2770  	__le64 rsvd6;
2771  	__le64 rsvd7;
2772  	__le64 rsvd8;
2773  	/* Tx Queue/Ring drops */
2774  	__le64 tx_queue_disabled;
2775  	__le64 tx_queue_error;
2776  	__le64 tx_desc_fetch_error;
2777  	__le64 tx_desc_data_error;
2778  	__le64 tx_queue_empty;
2779  	__le64 rsvd10;
2780  	__le64 rsvd11;
2781  	__le64 rsvd12;
2782  
2783  	/* RDMA/ROCE TX */
2784  	__le64 tx_rdma_ucast_bytes;
2785  	__le64 tx_rdma_ucast_packets;
2786  	__le64 tx_rdma_mcast_bytes;
2787  	__le64 tx_rdma_mcast_packets;
2788  	__le64 tx_rdma_cnp_packets;
2789  	__le64 rsvd13;
2790  	__le64 rsvd14;
2791  	__le64 rsvd15;
2792  
2793  	/* RDMA/ROCE RX */
2794  	__le64 rx_rdma_ucast_bytes;
2795  	__le64 rx_rdma_ucast_packets;
2796  	__le64 rx_rdma_mcast_bytes;
2797  	__le64 rx_rdma_mcast_packets;
2798  	__le64 rx_rdma_cnp_packets;
2799  	__le64 rx_rdma_ecn_packets;
2800  	__le64 rsvd16;
2801  	__le64 rsvd17;
2802  
2803  	__le64 rsvd18;
2804  	__le64 rsvd19;
2805  	__le64 rsvd20;
2806  	__le64 rsvd21;
2807  	__le64 rsvd22;
2808  	__le64 rsvd23;
2809  	__le64 rsvd24;
2810  	__le64 rsvd25;
2811  
2812  	__le64 rsvd26;
2813  	__le64 rsvd27;
2814  	__le64 rsvd28;
2815  	__le64 rsvd29;
2816  	__le64 rsvd30;
2817  	__le64 rsvd31;
2818  	__le64 rsvd32;
2819  	__le64 rsvd33;
2820  
2821  	__le64 rsvd34;
2822  	__le64 rsvd35;
2823  	__le64 rsvd36;
2824  	__le64 rsvd37;
2825  	__le64 rsvd38;
2826  	__le64 rsvd39;
2827  	__le64 rsvd40;
2828  	__le64 rsvd41;
2829  
2830  	__le64 rsvd42;
2831  	__le64 rsvd43;
2832  	__le64 rsvd44;
2833  	__le64 rsvd45;
2834  	__le64 rsvd46;
2835  	__le64 rsvd47;
2836  	__le64 rsvd48;
2837  	__le64 rsvd49;
2838  
2839  	/* RDMA/ROCE REQ Error/Debugs (768 - 895) */
2840  	__le64 rdma_req_rx_pkt_seq_err;
2841  	__le64 rdma_req_rx_rnr_retry_err;
2842  	__le64 rdma_req_rx_remote_access_err;
2843  	__le64 rdma_req_rx_remote_inv_req_err;
2844  	__le64 rdma_req_rx_remote_oper_err;
2845  	__le64 rdma_req_rx_implied_nak_seq_err;
2846  	__le64 rdma_req_rx_cqe_err;
2847  	__le64 rdma_req_rx_cqe_flush_err;
2848  
2849  	__le64 rdma_req_rx_dup_responses;
2850  	__le64 rdma_req_rx_invalid_packets;
2851  	__le64 rdma_req_tx_local_access_err;
2852  	__le64 rdma_req_tx_local_oper_err;
2853  	__le64 rdma_req_tx_memory_mgmt_err;
2854  	__le64 rsvd52;
2855  	__le64 rsvd53;
2856  	__le64 rsvd54;
2857  
2858  	/* RDMA/ROCE RESP Error/Debugs (896 - 1023) */
2859  	__le64 rdma_resp_rx_dup_requests;
2860  	__le64 rdma_resp_rx_out_of_buffer;
2861  	__le64 rdma_resp_rx_out_of_seq_pkts;
2862  	__le64 rdma_resp_rx_cqe_err;
2863  	__le64 rdma_resp_rx_cqe_flush_err;
2864  	__le64 rdma_resp_rx_local_len_err;
2865  	__le64 rdma_resp_rx_inv_request_err;
2866  	__le64 rdma_resp_rx_local_qp_oper_err;
2867  
2868  	__le64 rdma_resp_rx_out_of_atomic_resource;
2869  	__le64 rdma_resp_tx_pkt_seq_err;
2870  	__le64 rdma_resp_tx_remote_inv_req_err;
2871  	__le64 rdma_resp_tx_remote_access_err;
2872  	__le64 rdma_resp_tx_remote_oper_err;
2873  	__le64 rdma_resp_tx_rnr_retry_err;
2874  	__le64 rsvd57;
2875  	__le64 rsvd58;
2876  };
2877  
2878  /**
2879   * struct ionic_lif_info - LIF info structure
2880   * @config:	LIF configuration structure
2881   * @status:	LIF status structure
2882   * @stats:	LIF statistics structure
2883   */
2884  struct ionic_lif_info {
2885  	union ionic_lif_config config;
2886  	struct ionic_lif_status status;
2887  	struct ionic_lif_stats stats;
2888  };
2889  
2890  union ionic_dev_cmd {
2891  	u32 words[16];
2892  	struct ionic_admin_cmd cmd;
2893  	struct ionic_nop_cmd nop;
2894  
2895  	struct ionic_dev_identify_cmd identify;
2896  	struct ionic_dev_init_cmd init;
2897  	struct ionic_dev_reset_cmd reset;
2898  	struct ionic_dev_getattr_cmd getattr;
2899  	struct ionic_dev_setattr_cmd setattr;
2900  
2901  	struct ionic_port_identify_cmd port_identify;
2902  	struct ionic_port_init_cmd port_init;
2903  	struct ionic_port_reset_cmd port_reset;
2904  	struct ionic_port_getattr_cmd port_getattr;
2905  	struct ionic_port_setattr_cmd port_setattr;
2906  
2907  	struct ionic_vf_setattr_cmd vf_setattr;
2908  	struct ionic_vf_getattr_cmd vf_getattr;
2909  	struct ionic_vf_ctrl_cmd vf_ctrl;
2910  
2911  	struct ionic_lif_identify_cmd lif_identify;
2912  	struct ionic_lif_init_cmd lif_init;
2913  	struct ionic_lif_reset_cmd lif_reset;
2914  
2915  	struct ionic_qos_identify_cmd qos_identify;
2916  	struct ionic_qos_init_cmd qos_init;
2917  	struct ionic_qos_reset_cmd qos_reset;
2918  	struct ionic_qos_clear_stats_cmd qos_clear_stats;
2919  
2920  	struct ionic_q_identify_cmd q_identify;
2921  	struct ionic_q_init_cmd q_init;
2922  	struct ionic_q_control_cmd q_control;
2923  
2924  	struct ionic_fw_download_cmd fw_download;
2925  	struct ionic_fw_control_cmd fw_control;
2926  };
2927  
2928  union ionic_dev_cmd_comp {
2929  	u32 words[4];
2930  	u8 status;
2931  	struct ionic_admin_comp comp;
2932  	struct ionic_nop_comp nop;
2933  
2934  	struct ionic_dev_identify_comp identify;
2935  	struct ionic_dev_init_comp init;
2936  	struct ionic_dev_reset_comp reset;
2937  	struct ionic_dev_getattr_comp getattr;
2938  	struct ionic_dev_setattr_comp setattr;
2939  
2940  	struct ionic_port_identify_comp port_identify;
2941  	struct ionic_port_init_comp port_init;
2942  	struct ionic_port_reset_comp port_reset;
2943  	struct ionic_port_getattr_comp port_getattr;
2944  	struct ionic_port_setattr_comp port_setattr;
2945  
2946  	struct ionic_vf_setattr_comp vf_setattr;
2947  	struct ionic_vf_getattr_comp vf_getattr;
2948  	struct ionic_vf_ctrl_comp vf_ctrl;
2949  
2950  	struct ionic_lif_identify_comp lif_identify;
2951  	struct ionic_lif_init_comp lif_init;
2952  	ionic_lif_reset_comp lif_reset;
2953  
2954  	struct ionic_qos_identify_comp qos_identify;
2955  	ionic_qos_init_comp qos_init;
2956  	ionic_qos_reset_comp qos_reset;
2957  
2958  	struct ionic_q_identify_comp q_identify;
2959  	struct ionic_q_init_comp q_init;
2960  
2961  	ionic_fw_download_comp fw_download;
2962  	struct ionic_fw_control_comp fw_control;
2963  };
2964  
2965  /**
2966   * struct ionic_hwstamp_regs - Hardware current timestamp registers
2967   * @tick_low:        Low 32 bits of hardware timestamp
2968   * @tick_high:       High 32 bits of hardware timestamp
2969   */
2970  struct ionic_hwstamp_regs {
2971  	u32    tick_low;
2972  	u32    tick_high;
2973  };
2974  
2975  /**
2976   * union ionic_dev_info_regs - Device info register format (read-only)
2977   * @signature:       Signature value of 0x44455649 ('DEVI')
2978   * @version:         Current version of info
2979   * @asic_type:       Asic type
2980   * @asic_rev:        Asic revision
2981   * @fw_status:       Firmware status
2982   *			bit 0   - 1 = fw running
2983   *			bit 4-7 - 4 bit generation number, changes on fw restart
2984   * @fw_heartbeat:    Firmware heartbeat counter
2985   * @serial_num:      Serial number
2986   * @fw_version:      Firmware version
2987   * @hwstamp_regs:    Hardware current timestamp registers
2988   */
2989  union ionic_dev_info_regs {
2990  #define IONIC_DEVINFO_FWVERS_BUFLEN 32
2991  #define IONIC_DEVINFO_SERIAL_BUFLEN 32
2992  	struct {
2993  		u32    signature;
2994  		u8     version;
2995  		u8     asic_type;
2996  		u8     asic_rev;
2997  #define IONIC_FW_STS_F_RUNNING		0x01
2998  #define IONIC_FW_STS_F_GENERATION	0xF0
2999  		u8     fw_status;
3000  		u32    fw_heartbeat;
3001  		char   fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
3002  		char   serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];
3003  		u8     rsvd_pad1024[948];
3004  		struct ionic_hwstamp_regs hwstamp;
3005  	};
3006  	u32 words[512];
3007  };
3008  
3009  /**
3010   * union ionic_dev_cmd_regs - Device command register format (read-write)
3011   * @doorbell:        Device Cmd Doorbell, write-only
3012   *                   Write a 1 to signal device to process cmd,
3013   *                   poll done for completion.
3014   * @done:            Done indicator, bit 0 == 1 when command is complete
3015   * @cmd:             Opcode-specific command bytes
3016   * @comp:            Opcode-specific response bytes
3017   * @data:            Opcode-specific side-data
3018   */
3019  union ionic_dev_cmd_regs {
3020  	struct {
3021  		u32                   doorbell;
3022  		u32                   done;
3023  		union ionic_dev_cmd         cmd;
3024  		union ionic_dev_cmd_comp    comp;
3025  		u8                    rsvd[48];
3026  		u32                   data[478];
3027  	} __packed;
3028  	u32 words[512];
3029  };
3030  
3031  /**
3032   * union ionic_dev_regs - Device register format for bar 0 page 0
3033   * @info:            Device info registers
3034   * @devcmd:          Device command registers
3035   */
3036  union ionic_dev_regs {
3037  	struct {
3038  		union ionic_dev_info_regs info;
3039  		union ionic_dev_cmd_regs  devcmd;
3040  	} __packed;
3041  	__le32 words[1024];
3042  };
3043  
3044  union ionic_adminq_cmd {
3045  	struct ionic_admin_cmd cmd;
3046  	struct ionic_nop_cmd nop;
3047  	struct ionic_q_identify_cmd q_identify;
3048  	struct ionic_q_init_cmd q_init;
3049  	struct ionic_q_control_cmd q_control;
3050  	struct ionic_lif_setattr_cmd lif_setattr;
3051  	struct ionic_lif_getattr_cmd lif_getattr;
3052  	struct ionic_lif_setphc_cmd lif_setphc;
3053  	struct ionic_rx_mode_set_cmd rx_mode_set;
3054  	struct ionic_rx_filter_add_cmd rx_filter_add;
3055  	struct ionic_rx_filter_del_cmd rx_filter_del;
3056  	struct ionic_rdma_reset_cmd rdma_reset;
3057  	struct ionic_rdma_queue_cmd rdma_queue;
3058  	struct ionic_fw_download_cmd fw_download;
3059  	struct ionic_fw_control_cmd fw_control;
3060  };
3061  
3062  union ionic_adminq_comp {
3063  	struct ionic_admin_comp comp;
3064  	struct ionic_nop_comp nop;
3065  	struct ionic_q_identify_comp q_identify;
3066  	struct ionic_q_init_comp q_init;
3067  	struct ionic_lif_setattr_comp lif_setattr;
3068  	struct ionic_lif_getattr_comp lif_getattr;
3069  	struct ionic_admin_comp lif_setphc;
3070  	struct ionic_rx_filter_add_comp rx_filter_add;
3071  	struct ionic_fw_control_comp fw_control;
3072  };
3073  
3074  #define IONIC_BARS_MAX			6
3075  #define IONIC_PCI_BAR_DBELL		1
3076  #define IONIC_PCI_BAR_CMB		2
3077  
3078  #define IONIC_BAR0_SIZE				0x8000
3079  #define IONIC_BAR2_SIZE				0x800000
3080  
3081  #define IONIC_BAR0_DEV_INFO_REGS_OFFSET		0x0000
3082  #define IONIC_BAR0_DEV_CMD_REGS_OFFSET		0x0800
3083  #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET	0x0c00
3084  #define IONIC_BAR0_INTR_STATUS_OFFSET		0x1000
3085  #define IONIC_BAR0_INTR_CTRL_OFFSET		0x2000
3086  #define IONIC_DEV_CMD_DONE			0x00000001
3087  
3088  #define IONIC_ASIC_TYPE_CAPRI			0
3089  
3090  /**
3091   * struct ionic_doorbell - Doorbell register layout
3092   * @p_index: Producer index
3093   * @ring:    Selects the specific ring of the queue to update
3094   *           Type-specific meaning:
3095   *              ring=0: Default producer/consumer queue
3096   *              ring=1: (CQ, EQ) Re-Arm queue.  RDMA CQs
3097   *              send events to EQs when armed.  EQs send
3098   *              interrupts when armed.
3099   * @qid_lo:  Queue destination for the producer index and flags (low bits)
3100   * @qid_hi:  Queue destination for the producer index and flags (high bits)
3101   */
3102  struct ionic_doorbell {
3103  	__le16 p_index;
3104  	u8     ring;
3105  	u8     qid_lo;
3106  	__le16 qid_hi;
3107  	u16    rsvd2;
3108  };
3109  
3110  struct ionic_intr_status {
3111  	u32 status[2];
3112  };
3113  
3114  struct ionic_notifyq_cmd {
3115  	__le32 data;	/* Not used but needed for qcq structure */
3116  };
3117  
3118  union ionic_notifyq_comp {
3119  	struct ionic_notifyq_event event;
3120  	struct ionic_link_change_event link_change;
3121  	struct ionic_reset_event reset;
3122  	struct ionic_heartbeat_event heartbeat;
3123  	struct ionic_log_event log;
3124  };
3125  
3126  /* Deprecate */
3127  struct ionic_identity {
3128  	union ionic_drv_identity drv;
3129  	union ionic_dev_identity dev;
3130  	union ionic_lif_identity lif;
3131  	union ionic_port_identity port;
3132  	union ionic_qos_identity qos;
3133  	union ionic_q_identity txq;
3134  };
3135  
3136  #endif /* _IONIC_IF_H_ */
3137