1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/timekeeping.h> 8 #include "coredump.h" 9 #include "mt7996.h" 10 #include "../dma.h" 11 #include "mac.h" 12 #include "mcu.h" 13 14 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 15 16 static const struct mt7996_dfs_radar_spec etsi_radar_specs = { 17 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 18 .radar_pattern = { 19 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 20 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 21 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 22 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 23 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 24 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 25 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 26 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 27 }, 28 }; 29 30 static const struct mt7996_dfs_radar_spec fcc_radar_specs = { 31 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 32 .radar_pattern = { 33 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 34 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 35 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 36 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 37 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 38 }, 39 }; 40 41 static const struct mt7996_dfs_radar_spec jp_radar_specs = { 42 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 43 .radar_pattern = { 44 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 45 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 46 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 47 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 48 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 49 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 50 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 51 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 52 }, 53 }; 54 mt7996_rx_get_wcid(struct mt7996_dev * dev,u16 idx,bool unicast)55 static struct mt76_wcid *mt7996_rx_get_wcid(struct mt7996_dev *dev, 56 u16 idx, bool unicast) 57 { 58 struct mt7996_sta *sta; 59 struct mt76_wcid *wcid; 60 61 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 62 return NULL; 63 64 wcid = rcu_dereference(dev->mt76.wcid[idx]); 65 if (unicast || !wcid) 66 return wcid; 67 68 if (!wcid->sta) 69 return NULL; 70 71 sta = container_of(wcid, struct mt7996_sta, wcid); 72 if (!sta->vif) 73 return NULL; 74 75 return &sta->vif->sta.wcid; 76 } 77 mt7996_mac_wtbl_update(struct mt7996_dev * dev,int idx,u32 mask)78 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask) 79 { 80 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 81 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 82 83 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 84 0, 5000); 85 } 86 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev * dev,u16 wcid,u8 dw)87 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw) 88 { 89 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 90 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 91 92 return MT_WTBL_LMAC_OFFS(wcid, dw); 93 } 94 mt7996_mac_sta_poll(struct mt7996_dev * dev)95 static void mt7996_mac_sta_poll(struct mt7996_dev *dev) 96 { 97 static const u8 ac_to_tid[] = { 98 [IEEE80211_AC_BE] = 0, 99 [IEEE80211_AC_BK] = 1, 100 [IEEE80211_AC_VI] = 4, 101 [IEEE80211_AC_VO] = 6 102 }; 103 struct ieee80211_sta *sta; 104 struct mt7996_sta *msta; 105 struct rate_info *rate; 106 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 107 LIST_HEAD(sta_poll_list); 108 int i; 109 110 spin_lock_bh(&dev->mt76.sta_poll_lock); 111 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list); 112 spin_unlock_bh(&dev->mt76.sta_poll_lock); 113 114 rcu_read_lock(); 115 116 while (true) { 117 bool clear = false; 118 u32 addr, val; 119 u16 idx; 120 s8 rssi[4]; 121 u8 bw; 122 123 spin_lock_bh(&dev->mt76.sta_poll_lock); 124 if (list_empty(&sta_poll_list)) { 125 spin_unlock_bh(&dev->mt76.sta_poll_lock); 126 break; 127 } 128 msta = list_first_entry(&sta_poll_list, 129 struct mt7996_sta, wcid.poll_list); 130 list_del_init(&msta->wcid.poll_list); 131 spin_unlock_bh(&dev->mt76.sta_poll_lock); 132 133 idx = msta->wcid.idx; 134 135 /* refresh peer's airtime reporting */ 136 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 20); 137 138 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 139 u32 tx_last = msta->airtime_ac[i]; 140 u32 rx_last = msta->airtime_ac[i + 4]; 141 142 msta->airtime_ac[i] = mt76_rr(dev, addr); 143 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 144 145 tx_time[i] = msta->airtime_ac[i] - tx_last; 146 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 147 148 if ((tx_last | rx_last) & BIT(30)) 149 clear = true; 150 151 addr += 8; 152 } 153 154 if (clear) { 155 mt7996_mac_wtbl_update(dev, idx, 156 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 157 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 158 } 159 160 if (!msta->wcid.sta) 161 continue; 162 163 sta = container_of((void *)msta, struct ieee80211_sta, 164 drv_priv); 165 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 166 u8 q = mt76_connac_lmac_mapping(i); 167 u32 tx_cur = tx_time[q]; 168 u32 rx_cur = rx_time[q]; 169 u8 tid = ac_to_tid[i]; 170 171 if (!tx_cur && !rx_cur) 172 continue; 173 174 ieee80211_sta_register_airtime(sta, tid, tx_cur, rx_cur); 175 } 176 177 /* We don't support reading GI info from txs packets. 178 * For accurate tx status reporting and AQL improvement, 179 * we need to make sure that flags match so polling GI 180 * from per-sta counters directly. 181 */ 182 rate = &msta->wcid.rate; 183 184 switch (rate->bw) { 185 case RATE_INFO_BW_320: 186 bw = IEEE80211_STA_RX_BW_320; 187 break; 188 case RATE_INFO_BW_160: 189 bw = IEEE80211_STA_RX_BW_160; 190 break; 191 case RATE_INFO_BW_80: 192 bw = IEEE80211_STA_RX_BW_80; 193 break; 194 case RATE_INFO_BW_40: 195 bw = IEEE80211_STA_RX_BW_40; 196 break; 197 default: 198 bw = IEEE80211_STA_RX_BW_20; 199 break; 200 } 201 202 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 6); 203 val = mt76_rr(dev, addr); 204 if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) { 205 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 5); 206 val = mt76_rr(dev, addr); 207 rate->eht_gi = FIELD_GET(GENMASK(25, 24), val); 208 } else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 209 u8 offs = 24 + 2 * bw; 210 211 rate->he_gi = (val & (0x3 << offs)) >> offs; 212 } else if (rate->flags & 213 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 214 if (val & BIT(12 + bw)) 215 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 216 else 217 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 218 } 219 220 /* get signal strength of resp frames (CTS/BA/ACK) */ 221 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 34); 222 val = mt76_rr(dev, addr); 223 224 rssi[0] = to_rssi(GENMASK(7, 0), val); 225 rssi[1] = to_rssi(GENMASK(15, 8), val); 226 rssi[2] = to_rssi(GENMASK(23, 16), val); 227 rssi[3] = to_rssi(GENMASK(31, 14), val); 228 229 msta->ack_signal = 230 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi); 231 232 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal); 233 } 234 235 rcu_read_unlock(); 236 } 237 mt7996_mac_enable_rtscts(struct mt7996_dev * dev,struct ieee80211_vif * vif,bool enable)238 void mt7996_mac_enable_rtscts(struct mt7996_dev *dev, 239 struct ieee80211_vif *vif, bool enable) 240 { 241 struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 242 u32 addr; 243 244 addr = mt7996_mac_wtbl_lmac_addr(dev, mvif->sta.wcid.idx, 5); 245 if (enable) 246 mt76_set(dev, addr, BIT(5)); 247 else 248 mt76_clear(dev, addr, BIT(5)); 249 } 250 mt7996_mac_set_fixed_rate_table(struct mt7996_dev * dev,u8 tbl_idx,u16 rate_idx)251 void mt7996_mac_set_fixed_rate_table(struct mt7996_dev *dev, 252 u8 tbl_idx, u16 rate_idx) 253 { 254 u32 ctrl = MT_WTBL_ITCR_WR | MT_WTBL_ITCR_EXEC | tbl_idx; 255 256 mt76_wr(dev, MT_WTBL_ITDR0, rate_idx); 257 /* use wtbl spe idx */ 258 mt76_wr(dev, MT_WTBL_ITDR1, MT_WTBL_SPE_IDX_SEL); 259 mt76_wr(dev, MT_WTBL_ITCR, ctrl); 260 } 261 262 /* The HW does not translate the mac header to 802.3 for mesh point */ mt7996_reverse_frag0_hdr_trans(struct sk_buff * skb,u16 hdr_gap)263 static int mt7996_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 264 { 265 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 266 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 267 struct mt7996_sta *msta = (struct mt7996_sta *)status->wcid; 268 __le32 *rxd = (__le32 *)skb->data; 269 struct ieee80211_sta *sta; 270 struct ieee80211_vif *vif; 271 struct ieee80211_hdr hdr; 272 u16 frame_control; 273 274 if (le32_get_bits(rxd[3], MT_RXD3_NORMAL_ADDR_TYPE) != 275 MT_RXD3_NORMAL_U2M) 276 return -EINVAL; 277 278 if (!(le32_to_cpu(rxd[1]) & MT_RXD1_NORMAL_GROUP_4)) 279 return -EINVAL; 280 281 if (!msta || !msta->vif) 282 return -EINVAL; 283 284 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 285 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 286 287 /* store the info from RXD and ethhdr to avoid being overridden */ 288 frame_control = le32_get_bits(rxd[8], MT_RXD8_FRAME_CONTROL); 289 hdr.frame_control = cpu_to_le16(frame_control); 290 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[10], MT_RXD10_SEQ_CTRL)); 291 hdr.duration_id = 0; 292 293 ether_addr_copy(hdr.addr1, vif->addr); 294 ether_addr_copy(hdr.addr2, sta->addr); 295 switch (frame_control & (IEEE80211_FCTL_TODS | 296 IEEE80211_FCTL_FROMDS)) { 297 case 0: 298 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 299 break; 300 case IEEE80211_FCTL_FROMDS: 301 ether_addr_copy(hdr.addr3, eth_hdr->h_source); 302 break; 303 case IEEE80211_FCTL_TODS: 304 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 305 break; 306 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 307 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 308 ether_addr_copy(hdr.addr4, eth_hdr->h_source); 309 break; 310 default: 311 return -EINVAL; 312 } 313 314 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 315 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || 316 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) 317 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 318 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN) 319 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 320 else 321 skb_pull(skb, 2); 322 323 if (ieee80211_has_order(hdr.frame_control)) 324 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[11], 325 IEEE80211_HT_CTL_LEN); 326 if (ieee80211_is_data_qos(hdr.frame_control)) { 327 __le16 qos_ctrl; 328 329 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[10], MT_RXD10_QOS_CTL)); 330 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl, 331 IEEE80211_QOS_CTL_LEN); 332 } 333 334 if (ieee80211_has_a4(hdr.frame_control)) 335 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 336 else 337 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 338 339 return 0; 340 } 341 342 static int mt7996_mac_fill_rx_rate(struct mt7996_dev * dev,struct mt76_rx_status * status,struct ieee80211_supported_band * sband,__le32 * rxv,u8 * mode)343 mt7996_mac_fill_rx_rate(struct mt7996_dev *dev, 344 struct mt76_rx_status *status, 345 struct ieee80211_supported_band *sband, 346 __le32 *rxv, u8 *mode) 347 { 348 u32 v0, v2; 349 u8 stbc, gi, bw, dcm, nss; 350 int i, idx; 351 bool cck = false; 352 353 v0 = le32_to_cpu(rxv[0]); 354 v2 = le32_to_cpu(rxv[2]); 355 356 idx = FIELD_GET(MT_PRXV_TX_RATE, v0); 357 i = idx; 358 nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1; 359 360 stbc = FIELD_GET(MT_PRXV_HT_STBC, v2); 361 gi = FIELD_GET(MT_PRXV_HT_SHORT_GI, v2); 362 *mode = FIELD_GET(MT_PRXV_TX_MODE, v2); 363 dcm = FIELD_GET(MT_PRXV_DCM, v2); 364 bw = FIELD_GET(MT_PRXV_FRAME_MODE, v2); 365 366 switch (*mode) { 367 case MT_PHY_TYPE_CCK: 368 cck = true; 369 fallthrough; 370 case MT_PHY_TYPE_OFDM: 371 i = mt76_get_rate(&dev->mt76, sband, i, cck); 372 break; 373 case MT_PHY_TYPE_HT_GF: 374 case MT_PHY_TYPE_HT: 375 status->encoding = RX_ENC_HT; 376 if (gi) 377 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 378 if (i > 31) 379 return -EINVAL; 380 break; 381 case MT_PHY_TYPE_VHT: 382 status->nss = nss; 383 status->encoding = RX_ENC_VHT; 384 if (gi) 385 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 386 if (i > 11) 387 return -EINVAL; 388 break; 389 case MT_PHY_TYPE_HE_MU: 390 case MT_PHY_TYPE_HE_SU: 391 case MT_PHY_TYPE_HE_EXT_SU: 392 case MT_PHY_TYPE_HE_TB: 393 status->nss = nss; 394 status->encoding = RX_ENC_HE; 395 i &= GENMASK(3, 0); 396 397 if (gi <= NL80211_RATE_INFO_HE_GI_3_2) 398 status->he_gi = gi; 399 400 status->he_dcm = dcm; 401 break; 402 case MT_PHY_TYPE_EHT_SU: 403 case MT_PHY_TYPE_EHT_TRIG: 404 case MT_PHY_TYPE_EHT_MU: 405 status->nss = nss; 406 status->encoding = RX_ENC_EHT; 407 i &= GENMASK(3, 0); 408 409 if (gi <= NL80211_RATE_INFO_EHT_GI_3_2) 410 status->eht.gi = gi; 411 break; 412 default: 413 return -EINVAL; 414 } 415 status->rate_idx = i; 416 417 switch (bw) { 418 case IEEE80211_STA_RX_BW_20: 419 break; 420 case IEEE80211_STA_RX_BW_40: 421 if (*mode & MT_PHY_TYPE_HE_EXT_SU && 422 (idx & MT_PRXV_TX_ER_SU_106T)) { 423 status->bw = RATE_INFO_BW_HE_RU; 424 status->he_ru = 425 NL80211_RATE_INFO_HE_RU_ALLOC_106; 426 } else { 427 status->bw = RATE_INFO_BW_40; 428 } 429 break; 430 case IEEE80211_STA_RX_BW_80: 431 status->bw = RATE_INFO_BW_80; 432 break; 433 case IEEE80211_STA_RX_BW_160: 434 status->bw = RATE_INFO_BW_160; 435 break; 436 /* rxv reports bw 320-1 and 320-2 separately */ 437 case IEEE80211_STA_RX_BW_320: 438 case IEEE80211_STA_RX_BW_320 + 1: 439 status->bw = RATE_INFO_BW_320; 440 break; 441 default: 442 return -EINVAL; 443 } 444 445 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 446 if (*mode < MT_PHY_TYPE_HE_SU && gi) 447 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 448 449 return 0; 450 } 451 452 static int mt7996_mac_fill_rx(struct mt7996_dev * dev,struct sk_buff * skb)453 mt7996_mac_fill_rx(struct mt7996_dev *dev, struct sk_buff *skb) 454 { 455 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 456 struct mt76_phy *mphy = &dev->mt76.phy; 457 struct mt7996_phy *phy = &dev->phy; 458 struct ieee80211_supported_band *sband; 459 __le32 *rxd = (__le32 *)skb->data; 460 __le32 *rxv = NULL; 461 u32 rxd0 = le32_to_cpu(rxd[0]); 462 u32 rxd1 = le32_to_cpu(rxd[1]); 463 u32 rxd2 = le32_to_cpu(rxd[2]); 464 u32 rxd3 = le32_to_cpu(rxd[3]); 465 u32 rxd4 = le32_to_cpu(rxd[4]); 466 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 467 u32 csum_status = *(u32 *)skb->cb; 468 u32 mesh_mask = MT_RXD0_MESH | MT_RXD0_MHCP; 469 bool is_mesh = (rxd0 & mesh_mask) == mesh_mask; 470 bool unicast, insert_ccmp_hdr = false; 471 u8 remove_pad, amsdu_info, band_idx; 472 u8 mode = 0, qos_ctl = 0; 473 bool hdr_trans; 474 u16 hdr_gap; 475 u16 seq_ctrl = 0; 476 __le16 fc = 0; 477 int idx; 478 479 memset(status, 0, sizeof(*status)); 480 481 band_idx = FIELD_GET(MT_RXD1_NORMAL_BAND_IDX, rxd1); 482 mphy = dev->mt76.phys[band_idx]; 483 phy = mphy->priv; 484 status->phy_idx = mphy->band_idx; 485 486 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 487 return -EINVAL; 488 489 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 490 return -EINVAL; 491 492 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 493 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 494 return -EINVAL; 495 496 /* ICV error or CCMP/BIP/WPI MIC error */ 497 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 498 status->flag |= RX_FLAG_ONLY_MONITOR; 499 500 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 501 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 502 status->wcid = mt7996_rx_get_wcid(dev, idx, unicast); 503 504 if (status->wcid) { 505 struct mt7996_sta *msta; 506 507 msta = container_of(status->wcid, struct mt7996_sta, wcid); 508 spin_lock_bh(&dev->mt76.sta_poll_lock); 509 if (list_empty(&msta->wcid.poll_list)) 510 list_add_tail(&msta->wcid.poll_list, 511 &dev->mt76.sta_poll_list); 512 spin_unlock_bh(&dev->mt76.sta_poll_lock); 513 } 514 515 status->freq = mphy->chandef.chan->center_freq; 516 status->band = mphy->chandef.chan->band; 517 if (status->band == NL80211_BAND_5GHZ) 518 sband = &mphy->sband_5g.sband; 519 else if (status->band == NL80211_BAND_6GHZ) 520 sband = &mphy->sband_6g.sband; 521 else 522 sband = &mphy->sband_2g.sband; 523 524 if (!sband->channels) 525 return -EINVAL; 526 527 if ((rxd0 & csum_mask) == csum_mask && 528 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 529 skb->ip_summed = CHECKSUM_UNNECESSARY; 530 531 if (rxd1 & MT_RXD3_NORMAL_FCS_ERR) 532 status->flag |= RX_FLAG_FAILED_FCS_CRC; 533 534 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 535 status->flag |= RX_FLAG_MMIC_ERROR; 536 537 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 538 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 539 status->flag |= RX_FLAG_DECRYPTED; 540 status->flag |= RX_FLAG_IV_STRIPPED; 541 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 542 } 543 544 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 545 546 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 547 return -EINVAL; 548 549 rxd += 8; 550 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 551 u32 v0 = le32_to_cpu(rxd[0]); 552 u32 v2 = le32_to_cpu(rxd[2]); 553 554 fc = cpu_to_le16(FIELD_GET(MT_RXD8_FRAME_CONTROL, v0)); 555 qos_ctl = FIELD_GET(MT_RXD10_QOS_CTL, v2); 556 seq_ctrl = FIELD_GET(MT_RXD10_SEQ_CTRL, v2); 557 558 rxd += 4; 559 if ((u8 *)rxd - skb->data >= skb->len) 560 return -EINVAL; 561 } 562 563 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 564 u8 *data = (u8 *)rxd; 565 566 if (status->flag & RX_FLAG_DECRYPTED) { 567 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { 568 case MT_CIPHER_AES_CCMP: 569 case MT_CIPHER_CCMP_CCX: 570 case MT_CIPHER_CCMP_256: 571 insert_ccmp_hdr = 572 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 573 fallthrough; 574 case MT_CIPHER_TKIP: 575 case MT_CIPHER_TKIP_NO_MIC: 576 case MT_CIPHER_GCMP: 577 case MT_CIPHER_GCMP_256: 578 status->iv[0] = data[5]; 579 status->iv[1] = data[4]; 580 status->iv[2] = data[3]; 581 status->iv[3] = data[2]; 582 status->iv[4] = data[1]; 583 status->iv[5] = data[0]; 584 break; 585 default: 586 break; 587 } 588 } 589 rxd += 4; 590 if ((u8 *)rxd - skb->data >= skb->len) 591 return -EINVAL; 592 } 593 594 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 595 status->timestamp = le32_to_cpu(rxd[0]); 596 status->flag |= RX_FLAG_MACTIME_START; 597 598 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 599 status->flag |= RX_FLAG_AMPDU_DETAILS; 600 601 /* all subframes of an A-MPDU have the same timestamp */ 602 if (phy->rx_ampdu_ts != status->timestamp) { 603 if (!++phy->ampdu_ref) 604 phy->ampdu_ref++; 605 } 606 phy->rx_ampdu_ts = status->timestamp; 607 608 status->ampdu_ref = phy->ampdu_ref; 609 } 610 611 rxd += 4; 612 if ((u8 *)rxd - skb->data >= skb->len) 613 return -EINVAL; 614 } 615 616 /* RXD Group 3 - P-RXV */ 617 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 618 u32 v3; 619 int ret; 620 621 rxv = rxd; 622 rxd += 4; 623 if ((u8 *)rxd - skb->data >= skb->len) 624 return -EINVAL; 625 626 v3 = le32_to_cpu(rxv[3]); 627 628 status->chains = mphy->antenna_mask; 629 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v3); 630 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v3); 631 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v3); 632 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v3); 633 634 /* RXD Group 5 - C-RXV */ 635 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 636 rxd += 24; 637 if ((u8 *)rxd - skb->data >= skb->len) 638 return -EINVAL; 639 } 640 641 ret = mt7996_mac_fill_rx_rate(dev, status, sband, rxv, &mode); 642 if (ret < 0) 643 return ret; 644 } 645 646 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 647 status->amsdu = !!amsdu_info; 648 if (status->amsdu) { 649 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 650 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 651 } 652 653 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 654 if (hdr_trans && ieee80211_has_morefrags(fc)) { 655 if (mt7996_reverse_frag0_hdr_trans(skb, hdr_gap)) 656 return -EINVAL; 657 hdr_trans = false; 658 } else { 659 int pad_start = 0; 660 661 skb_pull(skb, hdr_gap); 662 if (!hdr_trans && status->amsdu && !(ieee80211_has_a4(fc) && is_mesh)) { 663 pad_start = ieee80211_get_hdrlen_from_skb(skb); 664 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 665 /* When header translation failure is indicated, 666 * the hardware will insert an extra 2-byte field 667 * containing the data length after the protocol 668 * type field. This happens either when the LLC-SNAP 669 * pattern did not match, or if a VLAN header was 670 * detected. 671 */ 672 pad_start = 12; 673 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 674 pad_start += 4; 675 else 676 pad_start = 0; 677 } 678 679 if (pad_start) { 680 memmove(skb->data + 2, skb->data, pad_start); 681 skb_pull(skb, 2); 682 } 683 } 684 685 if (!hdr_trans) { 686 struct ieee80211_hdr *hdr; 687 688 if (insert_ccmp_hdr) { 689 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 690 691 mt76_insert_ccmp_hdr(skb, key_id); 692 } 693 694 hdr = mt76_skb_get_hdr(skb); 695 fc = hdr->frame_control; 696 if (ieee80211_is_data_qos(fc)) { 697 u8 *qos = ieee80211_get_qos_ctl(hdr); 698 699 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 700 qos_ctl = *qos; 701 702 /* Mesh DA/SA/Length will be stripped after hardware 703 * de-amsdu, so here needs to clear amsdu present bit 704 * to mark it as a normal mesh frame. 705 */ 706 if (ieee80211_has_a4(fc) && is_mesh && status->amsdu) 707 *qos &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; 708 } 709 } else { 710 status->flag |= RX_FLAG_8023; 711 } 712 713 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 714 mt76_connac3_mac_decode_he_radiotap(skb, rxv, mode); 715 716 if (!status->wcid || !ieee80211_is_data_qos(fc)) 717 return 0; 718 719 status->aggr = unicast && 720 !ieee80211_is_qos_nullfunc(fc); 721 status->qos_ctl = qos_ctl; 722 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 723 724 return 0; 725 } 726 727 static void mt7996_mac_write_txwi_8023(struct mt7996_dev * dev,__le32 * txwi,struct sk_buff * skb,struct mt76_wcid * wcid)728 mt7996_mac_write_txwi_8023(struct mt7996_dev *dev, __le32 *txwi, 729 struct sk_buff *skb, struct mt76_wcid *wcid) 730 { 731 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 732 u8 fc_type, fc_stype; 733 u16 ethertype; 734 bool wmm = false; 735 u32 val; 736 737 if (wcid->sta) { 738 struct ieee80211_sta *sta; 739 740 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv); 741 wmm = sta->wme; 742 } 743 744 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | 745 FIELD_PREP(MT_TXD1_TID, tid); 746 747 ethertype = get_unaligned_be16(&skb->data[12]); 748 if (ethertype >= ETH_P_802_3_MIN) 749 val |= MT_TXD1_ETH_802_3; 750 751 txwi[1] |= cpu_to_le32(val); 752 753 fc_type = IEEE80211_FTYPE_DATA >> 2; 754 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; 755 756 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 757 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 758 759 txwi[2] |= cpu_to_le32(val); 760 761 if (wcid->amsdu) 762 txwi[3] |= cpu_to_le32(MT_TXD3_HW_AMSDU); 763 } 764 765 static void mt7996_mac_write_txwi_80211(struct mt7996_dev * dev,__le32 * txwi,struct sk_buff * skb,struct ieee80211_key_conf * key)766 mt7996_mac_write_txwi_80211(struct mt7996_dev *dev, __le32 *txwi, 767 struct sk_buff *skb, struct ieee80211_key_conf *key) 768 { 769 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 770 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 771 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 772 bool multicast = is_multicast_ether_addr(hdr->addr1); 773 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 774 __le16 fc = hdr->frame_control; 775 u8 fc_type, fc_stype; 776 u32 val; 777 778 if (ieee80211_is_action(fc) && 779 mgmt->u.action.category == WLAN_CATEGORY_BACK && 780 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) 781 tid = MT_TX_ADDBA; 782 else if (ieee80211_is_mgmt(hdr->frame_control)) 783 tid = MT_TX_NORMAL; 784 785 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 786 FIELD_PREP(MT_TXD1_HDR_INFO, 787 ieee80211_get_hdrlen_from_skb(skb) / 2) | 788 FIELD_PREP(MT_TXD1_TID, tid); 789 790 if (!ieee80211_is_data(fc) || multicast || 791 info->flags & IEEE80211_TX_CTL_USE_MINRATE) 792 val |= MT_TXD1_FIXED_RATE; 793 794 if (key && multicast && ieee80211_is_robust_mgmt_frame(skb) && 795 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 796 val |= MT_TXD1_BIP; 797 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); 798 } 799 800 txwi[1] |= cpu_to_le32(val); 801 802 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 803 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 804 805 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 806 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 807 808 txwi[2] |= cpu_to_le32(val); 809 810 txwi[3] |= cpu_to_le32(FIELD_PREP(MT_TXD3_BCM, multicast)); 811 if (ieee80211_is_beacon(fc)) { 812 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); 813 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); 814 } 815 816 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 817 u16 seqno = le16_to_cpu(hdr->seq_ctrl); 818 819 if (ieee80211_is_back_req(hdr->frame_control)) { 820 struct ieee80211_bar *bar; 821 822 bar = (struct ieee80211_bar *)skb->data; 823 seqno = le16_to_cpu(bar->start_seq_num); 824 } 825 826 val = MT_TXD3_SN_VALID | 827 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 828 txwi[3] |= cpu_to_le32(val); 829 txwi[3] &= ~cpu_to_le32(MT_TXD3_HW_AMSDU); 830 } 831 } 832 mt7996_mac_write_txwi(struct mt7996_dev * dev,__le32 * txwi,struct sk_buff * skb,struct mt76_wcid * wcid,struct ieee80211_key_conf * key,int pid,enum mt76_txq_id qid,u32 changed)833 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 834 struct sk_buff *skb, struct mt76_wcid *wcid, 835 struct ieee80211_key_conf *key, int pid, 836 enum mt76_txq_id qid, u32 changed) 837 { 838 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 839 struct ieee80211_vif *vif = info->control.vif; 840 u8 band_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 841 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 842 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 843 struct mt76_vif *mvif; 844 u16 tx_count = 15; 845 u32 val; 846 bool inband_disc = !!(changed & (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP | 847 BSS_CHANGED_FILS_DISCOVERY)); 848 bool beacon = !!(changed & (BSS_CHANGED_BEACON | 849 BSS_CHANGED_BEACON_ENABLED)) && (!inband_disc); 850 851 mvif = vif ? (struct mt76_vif *)vif->drv_priv : NULL; 852 if (mvif) { 853 omac_idx = mvif->omac_idx; 854 wmm_idx = mvif->wmm_idx; 855 band_idx = mvif->band_idx; 856 } 857 858 if (inband_disc) { 859 p_fmt = MT_TX_TYPE_FW; 860 q_idx = MT_LMAC_ALTX0; 861 } else if (beacon) { 862 p_fmt = MT_TX_TYPE_FW; 863 q_idx = MT_LMAC_BCN0; 864 } else if (qid >= MT_TXQ_PSD) { 865 p_fmt = MT_TX_TYPE_CT; 866 q_idx = MT_LMAC_ALTX0; 867 } else { 868 p_fmt = MT_TX_TYPE_CT; 869 q_idx = wmm_idx * MT7996_MAX_WMM_SETS + 870 mt76_connac_lmac_mapping(skb_get_queue_mapping(skb)); 871 } 872 873 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 874 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | 875 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 876 txwi[0] = cpu_to_le32(val); 877 878 val = FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 879 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 880 881 if (band_idx) 882 val |= FIELD_PREP(MT_TXD1_TGID, band_idx); 883 884 txwi[1] = cpu_to_le32(val); 885 txwi[2] = 0; 886 887 val = MT_TXD3_SW_POWER_MGMT | 888 FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 889 if (key) 890 val |= MT_TXD3_PROTECT_FRAME; 891 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 892 val |= MT_TXD3_NO_ACK; 893 894 txwi[3] = cpu_to_le32(val); 895 txwi[4] = 0; 896 897 val = FIELD_PREP(MT_TXD5_PID, pid); 898 if (pid >= MT_PACKET_ID_FIRST) 899 val |= MT_TXD5_TX_STATUS_HOST; 900 txwi[5] = cpu_to_le32(val); 901 902 val = MT_TXD6_DIS_MAT | MT_TXD6_DAS | 903 FIELD_PREP(MT_TXD6_MSDU_CNT, 1); 904 txwi[6] = cpu_to_le32(val); 905 txwi[7] = 0; 906 907 if (is_8023) 908 mt7996_mac_write_txwi_8023(dev, txwi, skb, wcid); 909 else 910 mt7996_mac_write_txwi_80211(dev, txwi, skb, key); 911 912 if (txwi[1] & cpu_to_le32(MT_TXD1_FIXED_RATE)) { 913 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 914 bool mcast = ieee80211_is_data(hdr->frame_control) && 915 is_multicast_ether_addr(hdr->addr1); 916 u8 idx = MT7996_BASIC_RATES_TBL; 917 918 if (mvif) { 919 if (mcast && mvif->mcast_rates_idx) 920 idx = mvif->mcast_rates_idx; 921 else if (beacon && mvif->beacon_rates_idx) 922 idx = mvif->beacon_rates_idx; 923 else 924 idx = mvif->basic_rates_idx; 925 } 926 927 txwi[6] |= cpu_to_le32(FIELD_PREP(MT_TXD6_TX_RATE, idx)); 928 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 929 } 930 } 931 mt7996_tx_prepare_skb(struct mt76_dev * mdev,void * txwi_ptr,enum mt76_txq_id qid,struct mt76_wcid * wcid,struct ieee80211_sta * sta,struct mt76_tx_info * tx_info)932 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 933 enum mt76_txq_id qid, struct mt76_wcid *wcid, 934 struct ieee80211_sta *sta, 935 struct mt76_tx_info *tx_info) 936 { 937 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 938 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 939 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 940 struct ieee80211_key_conf *key = info->control.hw_key; 941 struct ieee80211_vif *vif = info->control.vif; 942 struct mt76_connac_txp_common *txp; 943 struct mt76_txwi_cache *t; 944 int id, i, pid, nbuf = tx_info->nbuf - 1; 945 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 946 u8 *txwi = (u8 *)txwi_ptr; 947 948 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 949 return -EINVAL; 950 951 if (!wcid) 952 wcid = &dev->mt76.global_wcid; 953 954 if (sta) { 955 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 956 957 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 958 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 959 msta->jiffies = jiffies; 960 } 961 } 962 963 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 964 t->skb = tx_info->skb; 965 966 id = mt76_token_consume(mdev, &t); 967 if (id < 0) 968 return id; 969 970 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 971 mt7996_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key, 972 pid, qid, 0); 973 974 txp = (struct mt76_connac_txp_common *)(txwi + MT_TXD_SIZE); 975 for (i = 0; i < nbuf; i++) { 976 txp->fw.buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 977 txp->fw.len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 978 } 979 txp->fw.nbuf = nbuf; 980 981 txp->fw.flags = 982 cpu_to_le16(MT_CT_INFO_FROM_HOST | MT_CT_INFO_APPLY_TXD); 983 984 if (!key) 985 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 986 987 if (!is_8023 && ieee80211_is_mgmt(hdr->frame_control)) 988 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 989 990 if (vif) { 991 struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 992 993 txp->fw.bss_idx = mvif->mt76.idx; 994 } 995 996 txp->fw.token = cpu_to_le16(id); 997 txp->fw.rept_wds_wcid = cpu_to_le16(sta ? wcid->idx : 0xfff); 998 999 tx_info->skb = NULL; 1000 1001 /* pass partial skb header to fw */ 1002 tx_info->buf[1].len = MT_CT_PARSE_LEN; 1003 tx_info->buf[1].skip_unmap = true; 1004 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 1005 1006 return 0; 1007 } 1008 1009 static void mt7996_tx_check_aggr(struct ieee80211_sta * sta,__le32 * txwi)1010 mt7996_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) 1011 { 1012 struct mt7996_sta *msta; 1013 u16 fc, tid; 1014 u32 val; 1015 1016 if (!sta || !(sta->deflink.ht_cap.ht_supported || sta->deflink.he_cap.has_he)) 1017 return; 1018 1019 tid = le32_get_bits(txwi[1], MT_TXD1_TID); 1020 if (tid >= 6) /* skip VO queue */ 1021 return; 1022 1023 val = le32_to_cpu(txwi[2]); 1024 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | 1025 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; 1026 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 1027 return; 1028 1029 msta = (struct mt7996_sta *)sta->drv_priv; 1030 if (!test_and_set_bit(tid, &msta->wcid.ampdu_state)) 1031 ieee80211_start_tx_ba_session(sta, tid, 0); 1032 } 1033 1034 static void mt7996_txwi_free(struct mt7996_dev * dev,struct mt76_txwi_cache * t,struct ieee80211_sta * sta,struct list_head * free_list)1035 mt7996_txwi_free(struct mt7996_dev *dev, struct mt76_txwi_cache *t, 1036 struct ieee80211_sta *sta, struct list_head *free_list) 1037 { 1038 struct mt76_dev *mdev = &dev->mt76; 1039 struct mt76_wcid *wcid; 1040 __le32 *txwi; 1041 u16 wcid_idx; 1042 1043 mt76_connac_txp_skb_unmap(mdev, t); 1044 if (!t->skb) 1045 goto out; 1046 1047 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 1048 if (sta) { 1049 wcid = (struct mt76_wcid *)sta->drv_priv; 1050 wcid_idx = wcid->idx; 1051 1052 if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1053 mt7996_tx_check_aggr(sta, txwi); 1054 } else { 1055 wcid_idx = le32_get_bits(txwi[9], MT_TXD9_WLAN_IDX); 1056 } 1057 1058 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); 1059 1060 out: 1061 t->skb = NULL; 1062 mt76_put_txwi(mdev, t); 1063 } 1064 1065 static void mt7996_mac_tx_free(struct mt7996_dev * dev,void * data,int len)1066 mt7996_mac_tx_free(struct mt7996_dev *dev, void *data, int len) 1067 { 1068 __le32 *tx_free = (__le32 *)data, *cur_info; 1069 struct mt76_dev *mdev = &dev->mt76; 1070 struct mt76_phy *phy2 = mdev->phys[MT_BAND1]; 1071 struct mt76_phy *phy3 = mdev->phys[MT_BAND2]; 1072 struct mt76_txwi_cache *txwi; 1073 struct ieee80211_sta *sta = NULL; 1074 LIST_HEAD(free_list); 1075 struct sk_buff *skb, *tmp; 1076 void *end = data + len; 1077 bool wake = false; 1078 u16 total, count = 0; 1079 1080 /* clean DMA queues and unmap buffers first */ 1081 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1082 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1083 if (phy2) { 1084 mt76_queue_tx_cleanup(dev, phy2->q_tx[MT_TXQ_PSD], false); 1085 mt76_queue_tx_cleanup(dev, phy2->q_tx[MT_TXQ_BE], false); 1086 } 1087 if (phy3) { 1088 mt76_queue_tx_cleanup(dev, phy3->q_tx[MT_TXQ_PSD], false); 1089 mt76_queue_tx_cleanup(dev, phy3->q_tx[MT_TXQ_BE], false); 1090 } 1091 1092 if (WARN_ON_ONCE(le32_get_bits(tx_free[1], MT_TXFREE1_VER) < 4)) 1093 return; 1094 1095 total = le32_get_bits(tx_free[0], MT_TXFREE0_MSDU_CNT); 1096 for (cur_info = &tx_free[2]; count < total; cur_info++) { 1097 u32 msdu, info; 1098 u8 i; 1099 1100 if (WARN_ON_ONCE((void *)cur_info >= end)) 1101 return; 1102 /* 1'b1: new wcid pair. 1103 * 1'b0: msdu_id with the same 'wcid pair' as above. 1104 */ 1105 info = le32_to_cpu(*cur_info); 1106 if (info & MT_TXFREE_INFO_PAIR) { 1107 struct mt7996_sta *msta; 1108 struct mt76_wcid *wcid; 1109 u16 idx; 1110 1111 idx = FIELD_GET(MT_TXFREE_INFO_WLAN_ID, info); 1112 wcid = rcu_dereference(dev->mt76.wcid[idx]); 1113 sta = wcid_to_sta(wcid); 1114 if (!sta) 1115 continue; 1116 1117 msta = container_of(wcid, struct mt7996_sta, wcid); 1118 spin_lock_bh(&mdev->sta_poll_lock); 1119 if (list_empty(&msta->wcid.poll_list)) 1120 list_add_tail(&msta->wcid.poll_list, 1121 &mdev->sta_poll_list); 1122 spin_unlock_bh(&mdev->sta_poll_lock); 1123 continue; 1124 } 1125 1126 if (info & MT_TXFREE_INFO_HEADER) 1127 continue; 1128 1129 for (i = 0; i < 2; i++) { 1130 msdu = (info >> (15 * i)) & MT_TXFREE_INFO_MSDU_ID; 1131 if (msdu == MT_TXFREE_INFO_MSDU_ID) 1132 continue; 1133 1134 count++; 1135 txwi = mt76_token_release(mdev, msdu, &wake); 1136 if (!txwi) 1137 continue; 1138 1139 mt7996_txwi_free(dev, txwi, sta, &free_list); 1140 } 1141 } 1142 1143 mt7996_mac_sta_poll(dev); 1144 1145 if (wake) 1146 mt76_set_tx_blocked(&dev->mt76, false); 1147 1148 mt76_worker_schedule(&dev->mt76.tx_worker); 1149 1150 list_for_each_entry_safe(skb, tmp, &free_list, list) { 1151 skb_list_del_init(skb); 1152 napi_consume_skb(skb, 1); 1153 } 1154 } 1155 1156 static bool mt7996_mac_add_txs_skb(struct mt7996_dev * dev,struct mt76_wcid * wcid,int pid,__le32 * txs_data)1157 mt7996_mac_add_txs_skb(struct mt7996_dev *dev, struct mt76_wcid *wcid, 1158 int pid, __le32 *txs_data) 1159 { 1160 struct mt76_sta_stats *stats = &wcid->stats; 1161 struct ieee80211_supported_band *sband; 1162 struct mt76_dev *mdev = &dev->mt76; 1163 struct mt76_phy *mphy; 1164 struct ieee80211_tx_info *info; 1165 struct sk_buff_head list; 1166 struct rate_info rate = {}; 1167 struct sk_buff *skb; 1168 bool cck = false; 1169 u32 txrate, txs, mode, stbc; 1170 1171 mt76_tx_status_lock(mdev, &list); 1172 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list); 1173 if (!skb) 1174 goto out_no_skb; 1175 1176 txs = le32_to_cpu(txs_data[0]); 1177 1178 info = IEEE80211_SKB_CB(skb); 1179 if (!(txs & MT_TXS0_ACK_ERROR_MASK)) 1180 info->flags |= IEEE80211_TX_STAT_ACK; 1181 1182 info->status.ampdu_len = 1; 1183 info->status.ampdu_ack_len = !!(info->flags & 1184 IEEE80211_TX_STAT_ACK); 1185 1186 info->status.rates[0].idx = -1; 1187 1188 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1189 1190 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate); 1191 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1; 1192 stbc = le32_get_bits(txs_data[3], MT_TXS3_RATE_STBC); 1193 1194 if (stbc && rate.nss > 1) 1195 rate.nss >>= 1; 1196 1197 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss)) 1198 stats->tx_nss[rate.nss - 1]++; 1199 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs)) 1200 stats->tx_mcs[rate.mcs]++; 1201 1202 mode = FIELD_GET(MT_TX_RATE_MODE, txrate); 1203 switch (mode) { 1204 case MT_PHY_TYPE_CCK: 1205 cck = true; 1206 fallthrough; 1207 case MT_PHY_TYPE_OFDM: 1208 mphy = mt76_dev_phy(mdev, wcid->phy_idx); 1209 1210 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1211 sband = &mphy->sband_5g.sband; 1212 else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ) 1213 sband = &mphy->sband_6g.sband; 1214 else 1215 sband = &mphy->sband_2g.sband; 1216 1217 rate.mcs = mt76_get_rate(mphy->dev, sband, rate.mcs, cck); 1218 rate.legacy = sband->bitrates[rate.mcs].bitrate; 1219 break; 1220 case MT_PHY_TYPE_HT: 1221 case MT_PHY_TYPE_HT_GF: 1222 if (rate.mcs > 31) 1223 goto out; 1224 1225 rate.flags = RATE_INFO_FLAGS_MCS; 1226 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1227 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1228 break; 1229 case MT_PHY_TYPE_VHT: 1230 if (rate.mcs > 9) 1231 goto out; 1232 1233 rate.flags = RATE_INFO_FLAGS_VHT_MCS; 1234 break; 1235 case MT_PHY_TYPE_HE_SU: 1236 case MT_PHY_TYPE_HE_EXT_SU: 1237 case MT_PHY_TYPE_HE_TB: 1238 case MT_PHY_TYPE_HE_MU: 1239 if (rate.mcs > 11) 1240 goto out; 1241 1242 rate.he_gi = wcid->rate.he_gi; 1243 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate); 1244 rate.flags = RATE_INFO_FLAGS_HE_MCS; 1245 break; 1246 case MT_PHY_TYPE_EHT_SU: 1247 case MT_PHY_TYPE_EHT_TRIG: 1248 case MT_PHY_TYPE_EHT_MU: 1249 if (rate.mcs > 13) 1250 goto out; 1251 1252 rate.eht_gi = wcid->rate.eht_gi; 1253 rate.flags = RATE_INFO_FLAGS_EHT_MCS; 1254 break; 1255 default: 1256 goto out; 1257 } 1258 1259 stats->tx_mode[mode]++; 1260 1261 switch (FIELD_GET(MT_TXS0_BW, txs)) { 1262 case IEEE80211_STA_RX_BW_320: 1263 rate.bw = RATE_INFO_BW_320; 1264 stats->tx_bw[4]++; 1265 break; 1266 case IEEE80211_STA_RX_BW_160: 1267 rate.bw = RATE_INFO_BW_160; 1268 stats->tx_bw[3]++; 1269 break; 1270 case IEEE80211_STA_RX_BW_80: 1271 rate.bw = RATE_INFO_BW_80; 1272 stats->tx_bw[2]++; 1273 break; 1274 case IEEE80211_STA_RX_BW_40: 1275 rate.bw = RATE_INFO_BW_40; 1276 stats->tx_bw[1]++; 1277 break; 1278 default: 1279 rate.bw = RATE_INFO_BW_20; 1280 stats->tx_bw[0]++; 1281 break; 1282 } 1283 wcid->rate = rate; 1284 1285 out: 1286 mt76_tx_status_skb_done(mdev, skb, &list); 1287 1288 out_no_skb: 1289 mt76_tx_status_unlock(mdev, &list); 1290 1291 return !!skb; 1292 } 1293 mt7996_mac_add_txs(struct mt7996_dev * dev,void * data)1294 static void mt7996_mac_add_txs(struct mt7996_dev *dev, void *data) 1295 { 1296 struct mt7996_sta *msta = NULL; 1297 struct mt76_wcid *wcid; 1298 __le32 *txs_data = data; 1299 u16 wcidx; 1300 u8 pid; 1301 1302 if (le32_get_bits(txs_data[0], MT_TXS0_TXS_FORMAT) > 1) 1303 return; 1304 1305 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1306 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 1307 1308 if (pid < MT_PACKET_ID_FIRST) 1309 return; 1310 1311 if (wcidx >= mt7996_wtbl_size(dev)) 1312 return; 1313 1314 rcu_read_lock(); 1315 1316 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1317 if (!wcid) 1318 goto out; 1319 1320 msta = container_of(wcid, struct mt7996_sta, wcid); 1321 1322 mt7996_mac_add_txs_skb(dev, wcid, pid, txs_data); 1323 1324 if (!wcid->sta) 1325 goto out; 1326 1327 spin_lock_bh(&dev->mt76.sta_poll_lock); 1328 if (list_empty(&msta->wcid.poll_list)) 1329 list_add_tail(&msta->wcid.poll_list, &dev->mt76.sta_poll_list); 1330 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1331 1332 out: 1333 rcu_read_unlock(); 1334 } 1335 mt7996_rx_check(struct mt76_dev * mdev,void * data,int len)1336 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len) 1337 { 1338 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1339 __le32 *rxd = (__le32 *)data; 1340 __le32 *end = (__le32 *)&rxd[len / 4]; 1341 enum rx_pkt_type type; 1342 1343 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1344 if (type != PKT_TYPE_NORMAL) { 1345 u32 sw_type = le32_get_bits(rxd[0], MT_RXD0_SW_PKT_TYPE_MASK); 1346 1347 if (unlikely((sw_type & MT_RXD0_SW_PKT_TYPE_MAP) == 1348 MT_RXD0_SW_PKT_TYPE_FRAME)) 1349 return true; 1350 } 1351 1352 switch (type) { 1353 case PKT_TYPE_TXRX_NOTIFY: 1354 mt7996_mac_tx_free(dev, data, len); 1355 return false; 1356 case PKT_TYPE_TXS: 1357 for (rxd += 4; rxd + 8 <= end; rxd += 8) 1358 mt7996_mac_add_txs(dev, rxd); 1359 return false; 1360 case PKT_TYPE_RX_FW_MONITOR: 1361 mt7996_debugfs_rx_fw_monitor(dev, data, len); 1362 return false; 1363 default: 1364 return true; 1365 } 1366 } 1367 mt7996_queue_rx_skb(struct mt76_dev * mdev,enum mt76_rxq_id q,struct sk_buff * skb,u32 * info)1368 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1369 struct sk_buff *skb, u32 *info) 1370 { 1371 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1372 __le32 *rxd = (__le32 *)skb->data; 1373 __le32 *end = (__le32 *)&skb->data[skb->len]; 1374 enum rx_pkt_type type; 1375 1376 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1377 if (type != PKT_TYPE_NORMAL) { 1378 u32 sw_type = le32_get_bits(rxd[0], MT_RXD0_SW_PKT_TYPE_MASK); 1379 1380 if (unlikely((sw_type & MT_RXD0_SW_PKT_TYPE_MAP) == 1381 MT_RXD0_SW_PKT_TYPE_FRAME)) 1382 type = PKT_TYPE_NORMAL; 1383 } 1384 1385 switch (type) { 1386 case PKT_TYPE_TXRX_NOTIFY: 1387 mt7996_mac_tx_free(dev, skb->data, skb->len); 1388 napi_consume_skb(skb, 1); 1389 break; 1390 case PKT_TYPE_RX_EVENT: 1391 mt7996_mcu_rx_event(dev, skb); 1392 break; 1393 case PKT_TYPE_TXS: 1394 for (rxd += 4; rxd + 8 <= end; rxd += 8) 1395 mt7996_mac_add_txs(dev, rxd); 1396 dev_kfree_skb(skb); 1397 break; 1398 case PKT_TYPE_RX_FW_MONITOR: 1399 mt7996_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1400 dev_kfree_skb(skb); 1401 break; 1402 case PKT_TYPE_NORMAL: 1403 if (!mt7996_mac_fill_rx(dev, skb)) { 1404 mt76_rx(&dev->mt76, q, skb); 1405 return; 1406 } 1407 fallthrough; 1408 default: 1409 dev_kfree_skb(skb); 1410 break; 1411 } 1412 } 1413 mt7996_mac_cca_stats_reset(struct mt7996_phy * phy)1414 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy) 1415 { 1416 struct mt7996_dev *dev = phy->dev; 1417 u32 reg = MT_WF_PHYRX_BAND_RX_CTRL1(phy->mt76->band_idx); 1418 1419 mt76_clear(dev, reg, MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN); 1420 mt76_set(dev, reg, BIT(11) | BIT(9)); 1421 } 1422 mt7996_mac_reset_counters(struct mt7996_phy * phy)1423 void mt7996_mac_reset_counters(struct mt7996_phy *phy) 1424 { 1425 struct mt7996_dev *dev = phy->dev; 1426 u8 band_idx = phy->mt76->band_idx; 1427 int i; 1428 1429 for (i = 0; i < 16; i++) 1430 mt76_rr(dev, MT_TX_AGG_CNT(band_idx, i)); 1431 1432 phy->mt76->survey_time = ktime_get_boottime(); 1433 1434 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1435 1436 /* reset airtime counters */ 1437 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(band_idx), 1438 MT_WF_RMAC_MIB_RXTIME_CLR); 1439 1440 mt7996_mcu_get_chan_mib_info(phy, true); 1441 } 1442 mt7996_mac_set_coverage_class(struct mt7996_phy * phy)1443 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy) 1444 { 1445 s16 coverage_class = phy->coverage_class; 1446 struct mt7996_dev *dev = phy->dev; 1447 struct mt7996_phy *phy2 = mt7996_phy2(dev); 1448 struct mt7996_phy *phy3 = mt7996_phy3(dev); 1449 u32 reg_offset; 1450 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1451 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1452 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1453 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1454 u8 band_idx = phy->mt76->band_idx; 1455 int offset; 1456 1457 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1458 return; 1459 1460 if (phy2) 1461 coverage_class = max_t(s16, dev->phy.coverage_class, 1462 phy2->coverage_class); 1463 1464 if (phy3) 1465 coverage_class = max_t(s16, coverage_class, 1466 phy3->coverage_class); 1467 1468 offset = 3 * coverage_class; 1469 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1470 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1471 1472 mt76_wr(dev, MT_TMAC_CDTR(band_idx), cck + reg_offset); 1473 mt76_wr(dev, MT_TMAC_ODTR(band_idx), ofdm + reg_offset); 1474 } 1475 mt7996_mac_enable_nf(struct mt7996_dev * dev,u8 band)1476 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band) 1477 { 1478 mt76_set(dev, MT_WF_PHYRX_CSD_BAND_RXTD12(band), 1479 MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY | 1480 MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR); 1481 1482 mt76_set(dev, MT_WF_PHYRX_BAND_RX_CTRL1(band), 1483 FIELD_PREP(MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN, 0x5)); 1484 } 1485 1486 static u8 mt7996_phy_get_nf(struct mt7996_phy * phy,u8 band_idx)1487 mt7996_phy_get_nf(struct mt7996_phy *phy, u8 band_idx) 1488 { 1489 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1490 struct mt7996_dev *dev = phy->dev; 1491 u32 val, sum = 0, n = 0; 1492 int ant, i; 1493 1494 for (ant = 0; ant < hweight8(phy->mt76->antenna_mask); ant++) { 1495 u32 reg = MT_WF_PHYRX_CSD_IRPI(band_idx, ant); 1496 1497 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1498 val = mt76_rr(dev, reg); 1499 sum += val * nf_power[i]; 1500 n += val; 1501 } 1502 } 1503 1504 return n ? sum / n : 0; 1505 } 1506 mt7996_update_channel(struct mt76_phy * mphy)1507 void mt7996_update_channel(struct mt76_phy *mphy) 1508 { 1509 struct mt7996_phy *phy = (struct mt7996_phy *)mphy->priv; 1510 struct mt76_channel_state *state = mphy->chan_state; 1511 int nf; 1512 1513 mt7996_mcu_get_chan_mib_info(phy, false); 1514 1515 nf = mt7996_phy_get_nf(phy, mphy->band_idx); 1516 if (!phy->noise) 1517 phy->noise = nf << 4; 1518 else if (nf) 1519 phy->noise += nf - (phy->noise >> 4); 1520 1521 state->noise = -(phy->noise >> 4); 1522 } 1523 1524 static bool mt7996_wait_reset_state(struct mt7996_dev * dev,u32 state)1525 mt7996_wait_reset_state(struct mt7996_dev *dev, u32 state) 1526 { 1527 bool ret; 1528 1529 ret = wait_event_timeout(dev->reset_wait, 1530 (READ_ONCE(dev->recovery.state) & state), 1531 MT7996_RESET_TIMEOUT); 1532 1533 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1534 return ret; 1535 } 1536 1537 static void mt7996_update_vif_beacon(void * priv,u8 * mac,struct ieee80211_vif * vif)1538 mt7996_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1539 { 1540 struct ieee80211_hw *hw = priv; 1541 1542 switch (vif->type) { 1543 case NL80211_IFTYPE_MESH_POINT: 1544 case NL80211_IFTYPE_ADHOC: 1545 case NL80211_IFTYPE_AP: 1546 mt7996_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon); 1547 break; 1548 default: 1549 break; 1550 } 1551 } 1552 1553 static void mt7996_update_beacons(struct mt7996_dev * dev)1554 mt7996_update_beacons(struct mt7996_dev *dev) 1555 { 1556 struct mt76_phy *phy2, *phy3; 1557 1558 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1559 IEEE80211_IFACE_ITER_RESUME_ALL, 1560 mt7996_update_vif_beacon, dev->mt76.hw); 1561 1562 phy2 = dev->mt76.phys[MT_BAND1]; 1563 if (!phy2) 1564 return; 1565 1566 ieee80211_iterate_active_interfaces(phy2->hw, 1567 IEEE80211_IFACE_ITER_RESUME_ALL, 1568 mt7996_update_vif_beacon, phy2->hw); 1569 1570 phy3 = dev->mt76.phys[MT_BAND2]; 1571 if (!phy3) 1572 return; 1573 1574 ieee80211_iterate_active_interfaces(phy3->hw, 1575 IEEE80211_IFACE_ITER_RESUME_ALL, 1576 mt7996_update_vif_beacon, phy3->hw); 1577 } 1578 mt7996_tx_token_put(struct mt7996_dev * dev)1579 void mt7996_tx_token_put(struct mt7996_dev *dev) 1580 { 1581 struct mt76_txwi_cache *txwi; 1582 int id; 1583 1584 spin_lock_bh(&dev->mt76.token_lock); 1585 idr_for_each_entry(&dev->mt76.token, txwi, id) { 1586 mt7996_txwi_free(dev, txwi, NULL, NULL); 1587 dev->mt76.token_count--; 1588 } 1589 spin_unlock_bh(&dev->mt76.token_lock); 1590 idr_destroy(&dev->mt76.token); 1591 } 1592 1593 static int mt7996_mac_restart(struct mt7996_dev * dev)1594 mt7996_mac_restart(struct mt7996_dev *dev) 1595 { 1596 struct mt7996_phy *phy2, *phy3; 1597 struct mt76_dev *mdev = &dev->mt76; 1598 int i, ret; 1599 1600 phy2 = mt7996_phy2(dev); 1601 phy3 = mt7996_phy3(dev); 1602 1603 if (dev->hif2) { 1604 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); 1605 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1606 } 1607 1608 if (dev_is_pci(mdev->dev)) { 1609 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 1610 if (dev->hif2) 1611 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 1612 } 1613 1614 set_bit(MT76_RESET, &dev->mphy.state); 1615 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1616 wake_up(&dev->mt76.mcu.wait); 1617 if (phy2) { 1618 set_bit(MT76_RESET, &phy2->mt76->state); 1619 set_bit(MT76_MCU_RESET, &phy2->mt76->state); 1620 } 1621 if (phy3) { 1622 set_bit(MT76_RESET, &phy3->mt76->state); 1623 set_bit(MT76_MCU_RESET, &phy3->mt76->state); 1624 } 1625 1626 /* lock/unlock all queues to ensure that no tx is pending */ 1627 mt76_txq_schedule_all(&dev->mphy); 1628 if (phy2) 1629 mt76_txq_schedule_all(phy2->mt76); 1630 if (phy3) 1631 mt76_txq_schedule_all(phy3->mt76); 1632 1633 /* disable all tx/rx napi */ 1634 mt76_worker_disable(&dev->mt76.tx_worker); 1635 mt76_for_each_q_rx(mdev, i) { 1636 if (mdev->q_rx[i].ndesc) 1637 napi_disable(&dev->mt76.napi[i]); 1638 } 1639 napi_disable(&dev->mt76.tx_napi); 1640 1641 /* token reinit */ 1642 mt7996_tx_token_put(dev); 1643 idr_init(&dev->mt76.token); 1644 1645 mt7996_dma_reset(dev, true); 1646 1647 local_bh_disable(); 1648 mt76_for_each_q_rx(mdev, i) { 1649 if (mdev->q_rx[i].ndesc) { 1650 napi_enable(&dev->mt76.napi[i]); 1651 napi_schedule(&dev->mt76.napi[i]); 1652 } 1653 } 1654 local_bh_enable(); 1655 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1656 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1657 1658 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); 1659 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1660 if (dev->hif2) { 1661 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); 1662 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1663 } 1664 if (dev_is_pci(mdev->dev)) { 1665 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 1666 if (dev->hif2) 1667 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff); 1668 } 1669 1670 /* load firmware */ 1671 ret = mt7996_mcu_init_firmware(dev); 1672 if (ret) 1673 goto out; 1674 1675 /* set the necessary init items */ 1676 ret = mt7996_mcu_set_eeprom(dev); 1677 if (ret) 1678 goto out; 1679 1680 mt7996_mac_init(dev); 1681 mt7996_init_txpower(dev, &dev->mphy.sband_2g.sband); 1682 mt7996_init_txpower(dev, &dev->mphy.sband_5g.sband); 1683 mt7996_init_txpower(dev, &dev->mphy.sband_6g.sband); 1684 ret = mt7996_txbf_init(dev); 1685 1686 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1687 ret = mt7996_run(dev->mphy.hw); 1688 if (ret) 1689 goto out; 1690 } 1691 1692 if (phy2 && test_bit(MT76_STATE_RUNNING, &phy2->mt76->state)) { 1693 ret = mt7996_run(phy2->mt76->hw); 1694 if (ret) 1695 goto out; 1696 } 1697 1698 if (phy3 && test_bit(MT76_STATE_RUNNING, &phy3->mt76->state)) { 1699 ret = mt7996_run(phy3->mt76->hw); 1700 if (ret) 1701 goto out; 1702 } 1703 1704 out: 1705 /* reset done */ 1706 clear_bit(MT76_RESET, &dev->mphy.state); 1707 if (phy2) 1708 clear_bit(MT76_RESET, &phy2->mt76->state); 1709 if (phy3) 1710 clear_bit(MT76_RESET, &phy3->mt76->state); 1711 1712 local_bh_disable(); 1713 napi_enable(&dev->mt76.tx_napi); 1714 napi_schedule(&dev->mt76.tx_napi); 1715 local_bh_enable(); 1716 1717 mt76_worker_enable(&dev->mt76.tx_worker); 1718 return ret; 1719 } 1720 1721 static void mt7996_mac_full_reset(struct mt7996_dev * dev)1722 mt7996_mac_full_reset(struct mt7996_dev *dev) 1723 { 1724 struct mt7996_phy *phy2, *phy3; 1725 int i; 1726 1727 phy2 = mt7996_phy2(dev); 1728 phy3 = mt7996_phy3(dev); 1729 dev->recovery.hw_full_reset = true; 1730 1731 wake_up(&dev->mt76.mcu.wait); 1732 ieee80211_stop_queues(mt76_hw(dev)); 1733 if (phy2) 1734 ieee80211_stop_queues(phy2->mt76->hw); 1735 if (phy3) 1736 ieee80211_stop_queues(phy3->mt76->hw); 1737 1738 cancel_delayed_work_sync(&dev->mphy.mac_work); 1739 if (phy2) 1740 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1741 if (phy3) 1742 cancel_delayed_work_sync(&phy3->mt76->mac_work); 1743 1744 mutex_lock(&dev->mt76.mutex); 1745 for (i = 0; i < 10; i++) { 1746 if (!mt7996_mac_restart(dev)) 1747 break; 1748 } 1749 mutex_unlock(&dev->mt76.mutex); 1750 1751 if (i == 10) 1752 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1753 1754 ieee80211_restart_hw(mt76_hw(dev)); 1755 if (phy2) 1756 ieee80211_restart_hw(phy2->mt76->hw); 1757 if (phy3) 1758 ieee80211_restart_hw(phy3->mt76->hw); 1759 1760 ieee80211_wake_queues(mt76_hw(dev)); 1761 if (phy2) 1762 ieee80211_wake_queues(phy2->mt76->hw); 1763 if (phy3) 1764 ieee80211_wake_queues(phy3->mt76->hw); 1765 1766 dev->recovery.hw_full_reset = false; 1767 ieee80211_queue_delayed_work(mt76_hw(dev), 1768 &dev->mphy.mac_work, 1769 MT7996_WATCHDOG_TIME); 1770 if (phy2) 1771 ieee80211_queue_delayed_work(phy2->mt76->hw, 1772 &phy2->mt76->mac_work, 1773 MT7996_WATCHDOG_TIME); 1774 if (phy3) 1775 ieee80211_queue_delayed_work(phy3->mt76->hw, 1776 &phy3->mt76->mac_work, 1777 MT7996_WATCHDOG_TIME); 1778 } 1779 mt7996_mac_reset_work(struct work_struct * work)1780 void mt7996_mac_reset_work(struct work_struct *work) 1781 { 1782 struct mt7996_phy *phy2, *phy3; 1783 struct mt7996_dev *dev; 1784 int i; 1785 1786 dev = container_of(work, struct mt7996_dev, reset_work); 1787 phy2 = mt7996_phy2(dev); 1788 phy3 = mt7996_phy3(dev); 1789 1790 /* chip full reset */ 1791 if (dev->recovery.restart) { 1792 /* disable WA/WM WDT */ 1793 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA, 1794 MT_MCU_CMD_WDT_MASK); 1795 1796 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT) 1797 dev->recovery.wa_reset_count++; 1798 else 1799 dev->recovery.wm_reset_count++; 1800 1801 mt7996_mac_full_reset(dev); 1802 1803 /* enable mcu irq */ 1804 mt7996_irq_enable(dev, MT_INT_MCU_CMD); 1805 mt7996_irq_disable(dev, 0); 1806 1807 /* enable WA/WM WDT */ 1808 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 1809 1810 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE; 1811 dev->recovery.restart = false; 1812 return; 1813 } 1814 1815 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) 1816 return; 1817 1818 dev_info(dev->mt76.dev,"\n%s L1 SER recovery start.", 1819 wiphy_name(dev->mt76.hw->wiphy)); 1820 ieee80211_stop_queues(mt76_hw(dev)); 1821 if (phy2) 1822 ieee80211_stop_queues(phy2->mt76->hw); 1823 if (phy3) 1824 ieee80211_stop_queues(phy3->mt76->hw); 1825 1826 set_bit(MT76_RESET, &dev->mphy.state); 1827 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1828 wake_up(&dev->mt76.mcu.wait); 1829 cancel_delayed_work_sync(&dev->mphy.mac_work); 1830 if (phy2) { 1831 set_bit(MT76_RESET, &phy2->mt76->state); 1832 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1833 } 1834 if (phy3) { 1835 set_bit(MT76_RESET, &phy3->mt76->state); 1836 cancel_delayed_work_sync(&phy3->mt76->mac_work); 1837 } 1838 mt76_worker_disable(&dev->mt76.tx_worker); 1839 mt76_for_each_q_rx(&dev->mt76, i) 1840 napi_disable(&dev->mt76.napi[i]); 1841 napi_disable(&dev->mt76.tx_napi); 1842 1843 mutex_lock(&dev->mt76.mutex); 1844 1845 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1846 1847 if (mt7996_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1848 mt7996_dma_reset(dev, false); 1849 1850 mt7996_tx_token_put(dev); 1851 idr_init(&dev->mt76.token); 1852 1853 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1854 mt7996_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1855 } 1856 1857 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1858 mt7996_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1859 1860 /* enable DMA Tx/Tx and interrupt */ 1861 mt7996_dma_start(dev, false); 1862 1863 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1864 clear_bit(MT76_RESET, &dev->mphy.state); 1865 if (phy2) 1866 clear_bit(MT76_RESET, &phy2->mt76->state); 1867 if (phy3) 1868 clear_bit(MT76_RESET, &phy3->mt76->state); 1869 1870 local_bh_disable(); 1871 mt76_for_each_q_rx(&dev->mt76, i) { 1872 napi_enable(&dev->mt76.napi[i]); 1873 napi_schedule(&dev->mt76.napi[i]); 1874 } 1875 local_bh_enable(); 1876 1877 tasklet_schedule(&dev->mt76.irq_tasklet); 1878 1879 mt76_worker_enable(&dev->mt76.tx_worker); 1880 1881 local_bh_disable(); 1882 napi_enable(&dev->mt76.tx_napi); 1883 napi_schedule(&dev->mt76.tx_napi); 1884 local_bh_enable(); 1885 1886 ieee80211_wake_queues(mt76_hw(dev)); 1887 if (phy2) 1888 ieee80211_wake_queues(phy2->mt76->hw); 1889 if (phy3) 1890 ieee80211_wake_queues(phy3->mt76->hw); 1891 1892 mutex_unlock(&dev->mt76.mutex); 1893 1894 mt7996_update_beacons(dev); 1895 1896 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1897 MT7996_WATCHDOG_TIME); 1898 if (phy2) 1899 ieee80211_queue_delayed_work(phy2->mt76->hw, 1900 &phy2->mt76->mac_work, 1901 MT7996_WATCHDOG_TIME); 1902 if (phy3) 1903 ieee80211_queue_delayed_work(phy3->mt76->hw, 1904 &phy3->mt76->mac_work, 1905 MT7996_WATCHDOG_TIME); 1906 dev_info(dev->mt76.dev,"\n%s L1 SER recovery completed.", 1907 wiphy_name(dev->mt76.hw->wiphy)); 1908 } 1909 1910 /* firmware coredump */ mt7996_mac_dump_work(struct work_struct * work)1911 void mt7996_mac_dump_work(struct work_struct *work) 1912 { 1913 const struct mt7996_mem_region *mem_region; 1914 struct mt7996_crash_data *crash_data; 1915 struct mt7996_dev *dev; 1916 struct mt7996_mem_hdr *hdr; 1917 size_t buf_len; 1918 int i; 1919 u32 num; 1920 u8 *buf; 1921 1922 dev = container_of(work, struct mt7996_dev, dump_work); 1923 1924 mutex_lock(&dev->dump_mutex); 1925 1926 crash_data = mt7996_coredump_new(dev); 1927 if (!crash_data) { 1928 mutex_unlock(&dev->dump_mutex); 1929 goto skip_coredump; 1930 } 1931 1932 mem_region = mt7996_coredump_get_mem_layout(dev, &num); 1933 if (!mem_region || !crash_data->memdump_buf_len) { 1934 mutex_unlock(&dev->dump_mutex); 1935 goto skip_memdump; 1936 } 1937 1938 buf = crash_data->memdump_buf; 1939 buf_len = crash_data->memdump_buf_len; 1940 1941 /* dumping memory content... */ 1942 memset(buf, 0, buf_len); 1943 for (i = 0; i < num; i++) { 1944 if (mem_region->len > buf_len) { 1945 dev_warn(dev->mt76.dev, "%s len %zu is too large\n", 1946 mem_region->name, mem_region->len); 1947 break; 1948 } 1949 1950 /* reserve space for the header */ 1951 hdr = (void *)buf; 1952 buf += sizeof(*hdr); 1953 buf_len -= sizeof(*hdr); 1954 1955 mt7996_memcpy_fromio(dev, buf, mem_region->start, 1956 mem_region->len); 1957 1958 hdr->start = mem_region->start; 1959 hdr->len = mem_region->len; 1960 1961 if (!mem_region->len) 1962 /* note: the header remains, just with zero length */ 1963 break; 1964 1965 buf += mem_region->len; 1966 buf_len -= mem_region->len; 1967 1968 mem_region++; 1969 } 1970 1971 mutex_unlock(&dev->dump_mutex); 1972 1973 skip_memdump: 1974 mt7996_coredump_submit(dev); 1975 skip_coredump: 1976 queue_work(dev->mt76.wq, &dev->reset_work); 1977 } 1978 mt7996_reset(struct mt7996_dev * dev)1979 void mt7996_reset(struct mt7996_dev *dev) 1980 { 1981 if (!dev->recovery.hw_init_done) 1982 return; 1983 1984 if (dev->recovery.hw_full_reset) 1985 return; 1986 1987 /* wm/wa exception: do full recovery */ 1988 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) { 1989 dev->recovery.restart = true; 1990 dev_info(dev->mt76.dev, 1991 "%s indicated firmware crash, attempting recovery\n", 1992 wiphy_name(dev->mt76.hw->wiphy)); 1993 1994 mt7996_irq_disable(dev, MT_INT_MCU_CMD); 1995 queue_work(dev->mt76.wq, &dev->dump_work); 1996 return; 1997 } 1998 1999 queue_work(dev->mt76.wq, &dev->reset_work); 2000 wake_up(&dev->reset_wait); 2001 } 2002 mt7996_mac_update_stats(struct mt7996_phy * phy)2003 void mt7996_mac_update_stats(struct mt7996_phy *phy) 2004 { 2005 struct mt76_mib_stats *mib = &phy->mib; 2006 struct mt7996_dev *dev = phy->dev; 2007 u8 band_idx = phy->mt76->band_idx; 2008 u32 cnt; 2009 int i; 2010 2011 cnt = mt76_rr(dev, MT_MIB_RSCR1(band_idx)); 2012 mib->fcs_err_cnt += cnt; 2013 2014 cnt = mt76_rr(dev, MT_MIB_RSCR33(band_idx)); 2015 mib->rx_fifo_full_cnt += cnt; 2016 2017 cnt = mt76_rr(dev, MT_MIB_RSCR31(band_idx)); 2018 mib->rx_mpdu_cnt += cnt; 2019 2020 cnt = mt76_rr(dev, MT_MIB_SDR6(band_idx)); 2021 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 2022 2023 cnt = mt76_rr(dev, MT_MIB_RVSR0(band_idx)); 2024 mib->rx_vector_mismatch_cnt += cnt; 2025 2026 cnt = mt76_rr(dev, MT_MIB_RSCR35(band_idx)); 2027 mib->rx_delimiter_fail_cnt += cnt; 2028 2029 cnt = mt76_rr(dev, MT_MIB_RSCR36(band_idx)); 2030 mib->rx_len_mismatch_cnt += cnt; 2031 2032 cnt = mt76_rr(dev, MT_MIB_TSCR0(band_idx)); 2033 mib->tx_ampdu_cnt += cnt; 2034 2035 cnt = mt76_rr(dev, MT_MIB_TSCR2(band_idx)); 2036 mib->tx_stop_q_empty_cnt += cnt; 2037 2038 cnt = mt76_rr(dev, MT_MIB_TSCR3(band_idx)); 2039 mib->tx_mpdu_attempts_cnt += cnt; 2040 2041 cnt = mt76_rr(dev, MT_MIB_TSCR4(band_idx)); 2042 mib->tx_mpdu_success_cnt += cnt; 2043 2044 cnt = mt76_rr(dev, MT_MIB_RSCR27(band_idx)); 2045 mib->rx_ampdu_cnt += cnt; 2046 2047 cnt = mt76_rr(dev, MT_MIB_RSCR28(band_idx)); 2048 mib->rx_ampdu_bytes_cnt += cnt; 2049 2050 cnt = mt76_rr(dev, MT_MIB_RSCR29(band_idx)); 2051 mib->rx_ampdu_valid_subframe_cnt += cnt; 2052 2053 cnt = mt76_rr(dev, MT_MIB_RSCR30(band_idx)); 2054 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 2055 2056 cnt = mt76_rr(dev, MT_MIB_SDR27(band_idx)); 2057 mib->tx_rwp_fail_cnt += FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT, cnt); 2058 2059 cnt = mt76_rr(dev, MT_MIB_SDR28(band_idx)); 2060 mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT, cnt); 2061 2062 cnt = mt76_rr(dev, MT_UMIB_RPDCR(band_idx)); 2063 mib->rx_pfdrop_cnt += cnt; 2064 2065 cnt = mt76_rr(dev, MT_MIB_RVSR1(band_idx)); 2066 mib->rx_vec_queue_overflow_drop_cnt += cnt; 2067 2068 cnt = mt76_rr(dev, MT_MIB_TSCR1(band_idx)); 2069 mib->rx_ba_cnt += cnt; 2070 2071 cnt = mt76_rr(dev, MT_MIB_BSCR0(band_idx)); 2072 mib->tx_bf_ebf_ppdu_cnt += cnt; 2073 2074 cnt = mt76_rr(dev, MT_MIB_BSCR1(band_idx)); 2075 mib->tx_bf_ibf_ppdu_cnt += cnt; 2076 2077 cnt = mt76_rr(dev, MT_MIB_BSCR2(band_idx)); 2078 mib->tx_mu_bf_cnt += cnt; 2079 2080 cnt = mt76_rr(dev, MT_MIB_TSCR5(band_idx)); 2081 mib->tx_mu_mpdu_cnt += cnt; 2082 2083 cnt = mt76_rr(dev, MT_MIB_TSCR6(band_idx)); 2084 mib->tx_mu_acked_mpdu_cnt += cnt; 2085 2086 cnt = mt76_rr(dev, MT_MIB_TSCR7(band_idx)); 2087 mib->tx_su_acked_mpdu_cnt += cnt; 2088 2089 cnt = mt76_rr(dev, MT_MIB_BSCR3(band_idx)); 2090 mib->tx_bf_rx_fb_ht_cnt += cnt; 2091 mib->tx_bf_rx_fb_all_cnt += cnt; 2092 2093 cnt = mt76_rr(dev, MT_MIB_BSCR4(band_idx)); 2094 mib->tx_bf_rx_fb_vht_cnt += cnt; 2095 mib->tx_bf_rx_fb_all_cnt += cnt; 2096 2097 cnt = mt76_rr(dev, MT_MIB_BSCR5(band_idx)); 2098 mib->tx_bf_rx_fb_he_cnt += cnt; 2099 mib->tx_bf_rx_fb_all_cnt += cnt; 2100 2101 cnt = mt76_rr(dev, MT_MIB_BSCR6(band_idx)); 2102 mib->tx_bf_rx_fb_eht_cnt += cnt; 2103 mib->tx_bf_rx_fb_all_cnt += cnt; 2104 2105 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CONT(band_idx)); 2106 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_RX_FB_BW, cnt); 2107 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_RX_FB_NC, cnt); 2108 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_RX_FB_NR, cnt); 2109 2110 cnt = mt76_rr(dev, MT_MIB_BSCR7(band_idx)); 2111 mib->tx_bf_fb_trig_cnt += cnt; 2112 2113 cnt = mt76_rr(dev, MT_MIB_BSCR17(band_idx)); 2114 mib->tx_bf_fb_cpl_cnt += cnt; 2115 2116 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 2117 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 2118 mib->tx_amsdu[i] += cnt; 2119 mib->tx_amsdu_cnt += cnt; 2120 } 2121 2122 /* rts count */ 2123 cnt = mt76_rr(dev, MT_MIB_BTSCR5(band_idx)); 2124 mib->rts_cnt += cnt; 2125 2126 /* rts retry count */ 2127 cnt = mt76_rr(dev, MT_MIB_BTSCR6(band_idx)); 2128 mib->rts_retries_cnt += cnt; 2129 2130 /* ba miss count */ 2131 cnt = mt76_rr(dev, MT_MIB_BTSCR0(band_idx)); 2132 mib->ba_miss_cnt += cnt; 2133 2134 /* ack fail count */ 2135 cnt = mt76_rr(dev, MT_MIB_BFTFCR(band_idx)); 2136 mib->ack_fail_cnt += cnt; 2137 2138 for (i = 0; i < 16; i++) { 2139 cnt = mt76_rr(dev, MT_TX_AGG_CNT(band_idx, i)); 2140 phy->mt76->aggr_stats[i] += cnt; 2141 } 2142 } 2143 mt7996_mac_sta_rc_work(struct work_struct * work)2144 void mt7996_mac_sta_rc_work(struct work_struct *work) 2145 { 2146 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, rc_work); 2147 struct ieee80211_sta *sta; 2148 struct ieee80211_vif *vif; 2149 struct mt7996_sta *msta; 2150 u32 changed; 2151 LIST_HEAD(list); 2152 2153 spin_lock_bh(&dev->mt76.sta_poll_lock); 2154 list_splice_init(&dev->sta_rc_list, &list); 2155 2156 while (!list_empty(&list)) { 2157 msta = list_first_entry(&list, struct mt7996_sta, rc_list); 2158 list_del_init(&msta->rc_list); 2159 changed = msta->changed; 2160 msta->changed = 0; 2161 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2162 2163 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 2164 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 2165 2166 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 2167 IEEE80211_RC_NSS_CHANGED | 2168 IEEE80211_RC_BW_CHANGED)) 2169 mt7996_mcu_add_rate_ctrl(dev, vif, sta, true); 2170 2171 /* TODO: smps change */ 2172 2173 spin_lock_bh(&dev->mt76.sta_poll_lock); 2174 } 2175 2176 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2177 } 2178 mt7996_mac_work(struct work_struct * work)2179 void mt7996_mac_work(struct work_struct *work) 2180 { 2181 struct mt7996_phy *phy; 2182 struct mt76_phy *mphy; 2183 2184 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2185 mac_work.work); 2186 phy = mphy->priv; 2187 2188 mutex_lock(&mphy->dev->mutex); 2189 2190 mt76_update_survey(mphy); 2191 if (++mphy->mac_work_count == 5) { 2192 mphy->mac_work_count = 0; 2193 2194 mt7996_mac_update_stats(phy); 2195 } 2196 2197 mutex_unlock(&mphy->dev->mutex); 2198 2199 mt76_tx_status_check(mphy->dev, false); 2200 2201 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2202 MT7996_WATCHDOG_TIME); 2203 } 2204 mt7996_dfs_stop_radar_detector(struct mt7996_phy * phy)2205 static void mt7996_dfs_stop_radar_detector(struct mt7996_phy *phy) 2206 { 2207 struct mt7996_dev *dev = phy->dev; 2208 2209 if (phy->rdd_state & BIT(0)) 2210 mt7996_mcu_rdd_cmd(dev, RDD_STOP, 0, 2211 MT_RX_SEL0, 0); 2212 if (phy->rdd_state & BIT(1)) 2213 mt7996_mcu_rdd_cmd(dev, RDD_STOP, 1, 2214 MT_RX_SEL0, 0); 2215 } 2216 mt7996_dfs_start_rdd(struct mt7996_dev * dev,int chain)2217 static int mt7996_dfs_start_rdd(struct mt7996_dev *dev, int chain) 2218 { 2219 int err, region; 2220 2221 switch (dev->mt76.region) { 2222 case NL80211_DFS_ETSI: 2223 region = 0; 2224 break; 2225 case NL80211_DFS_JP: 2226 region = 2; 2227 break; 2228 case NL80211_DFS_FCC: 2229 default: 2230 region = 1; 2231 break; 2232 } 2233 2234 err = mt7996_mcu_rdd_cmd(dev, RDD_START, chain, 2235 MT_RX_SEL0, region); 2236 if (err < 0) 2237 return err; 2238 2239 return mt7996_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, 2240 MT_RX_SEL0, 1); 2241 } 2242 mt7996_dfs_start_radar_detector(struct mt7996_phy * phy)2243 static int mt7996_dfs_start_radar_detector(struct mt7996_phy *phy) 2244 { 2245 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2246 struct mt7996_dev *dev = phy->dev; 2247 u8 band_idx = phy->mt76->band_idx; 2248 int err; 2249 2250 /* start CAC */ 2251 err = mt7996_mcu_rdd_cmd(dev, RDD_CAC_START, band_idx, 2252 MT_RX_SEL0, 0); 2253 if (err < 0) 2254 return err; 2255 2256 err = mt7996_dfs_start_rdd(dev, band_idx); 2257 if (err < 0) 2258 return err; 2259 2260 phy->rdd_state |= BIT(band_idx); 2261 2262 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2263 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2264 err = mt7996_dfs_start_rdd(dev, 1); 2265 if (err < 0) 2266 return err; 2267 2268 phy->rdd_state |= BIT(1); 2269 } 2270 2271 return 0; 2272 } 2273 2274 static int mt7996_dfs_init_radar_specs(struct mt7996_phy * phy)2275 mt7996_dfs_init_radar_specs(struct mt7996_phy *phy) 2276 { 2277 const struct mt7996_dfs_radar_spec *radar_specs; 2278 struct mt7996_dev *dev = phy->dev; 2279 int err, i; 2280 2281 switch (dev->mt76.region) { 2282 case NL80211_DFS_FCC: 2283 radar_specs = &fcc_radar_specs; 2284 err = mt7996_mcu_set_fcc5_lpn(dev, 8); 2285 if (err < 0) 2286 return err; 2287 break; 2288 case NL80211_DFS_ETSI: 2289 radar_specs = &etsi_radar_specs; 2290 break; 2291 case NL80211_DFS_JP: 2292 radar_specs = &jp_radar_specs; 2293 break; 2294 default: 2295 return -EINVAL; 2296 } 2297 2298 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2299 err = mt7996_mcu_set_radar_th(dev, i, 2300 &radar_specs->radar_pattern[i]); 2301 if (err < 0) 2302 return err; 2303 } 2304 2305 return mt7996_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2306 } 2307 mt7996_dfs_init_radar_detector(struct mt7996_phy * phy)2308 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy) 2309 { 2310 struct mt7996_dev *dev = phy->dev; 2311 enum mt76_dfs_state dfs_state, prev_state; 2312 int err; 2313 2314 prev_state = phy->mt76->dfs_state; 2315 dfs_state = mt76_phy_dfs_state(phy->mt76); 2316 2317 if (prev_state == dfs_state) 2318 return 0; 2319 2320 if (prev_state == MT_DFS_STATE_UNKNOWN) 2321 mt7996_dfs_stop_radar_detector(phy); 2322 2323 if (dfs_state == MT_DFS_STATE_DISABLED) 2324 goto stop; 2325 2326 if (prev_state <= MT_DFS_STATE_DISABLED) { 2327 err = mt7996_dfs_init_radar_specs(phy); 2328 if (err < 0) 2329 return err; 2330 2331 err = mt7996_dfs_start_radar_detector(phy); 2332 if (err < 0) 2333 return err; 2334 2335 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2336 } 2337 2338 if (dfs_state == MT_DFS_STATE_CAC) 2339 return 0; 2340 2341 err = mt7996_mcu_rdd_cmd(dev, RDD_CAC_END, 2342 phy->mt76->band_idx, MT_RX_SEL0, 0); 2343 if (err < 0) { 2344 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2345 return err; 2346 } 2347 2348 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2349 return 0; 2350 2351 stop: 2352 err = mt7996_mcu_rdd_cmd(dev, RDD_NORMAL_START, 2353 phy->mt76->band_idx, MT_RX_SEL0, 0); 2354 if (err < 0) 2355 return err; 2356 2357 mt7996_dfs_stop_radar_detector(phy); 2358 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2359 2360 return 0; 2361 } 2362 2363 static int mt7996_mac_twt_duration_align(int duration)2364 mt7996_mac_twt_duration_align(int duration) 2365 { 2366 return duration << 8; 2367 } 2368 2369 static u64 mt7996_mac_twt_sched_list_add(struct mt7996_dev * dev,struct mt7996_twt_flow * flow)2370 mt7996_mac_twt_sched_list_add(struct mt7996_dev *dev, 2371 struct mt7996_twt_flow *flow) 2372 { 2373 struct mt7996_twt_flow *iter, *iter_next; 2374 u32 duration = flow->duration << 8; 2375 u64 start_tsf; 2376 2377 iter = list_first_entry_or_null(&dev->twt_list, 2378 struct mt7996_twt_flow, list); 2379 if (!iter || !iter->sched || iter->start_tsf > duration) { 2380 /* add flow as first entry in the list */ 2381 list_add(&flow->list, &dev->twt_list); 2382 return 0; 2383 } 2384 2385 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2386 start_tsf = iter->start_tsf + 2387 mt7996_mac_twt_duration_align(iter->duration); 2388 if (list_is_last(&iter->list, &dev->twt_list)) 2389 break; 2390 2391 if (!iter_next->sched || 2392 iter_next->start_tsf > start_tsf + duration) { 2393 list_add(&flow->list, &iter->list); 2394 goto out; 2395 } 2396 } 2397 2398 /* add flow as last entry in the list */ 2399 list_add_tail(&flow->list, &dev->twt_list); 2400 out: 2401 return start_tsf; 2402 } 2403 mt7996_mac_check_twt_req(struct ieee80211_twt_setup * twt)2404 static int mt7996_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2405 { 2406 struct ieee80211_twt_params *twt_agrt; 2407 u64 interval, duration; 2408 u16 mantissa; 2409 u8 exp; 2410 2411 /* only individual agreement supported */ 2412 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2413 return -EOPNOTSUPP; 2414 2415 /* only 256us unit supported */ 2416 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2417 return -EOPNOTSUPP; 2418 2419 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2420 2421 /* explicit agreement not supported */ 2422 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2423 return -EOPNOTSUPP; 2424 2425 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2426 le16_to_cpu(twt_agrt->req_type)); 2427 mantissa = le16_to_cpu(twt_agrt->mantissa); 2428 duration = twt_agrt->min_twt_dur << 8; 2429 2430 interval = (u64)mantissa << exp; 2431 if (interval < duration) 2432 return -EOPNOTSUPP; 2433 2434 return 0; 2435 } 2436 2437 static bool mt7996_mac_twt_param_equal(struct mt7996_sta * msta,struct ieee80211_twt_params * twt_agrt)2438 mt7996_mac_twt_param_equal(struct mt7996_sta *msta, 2439 struct ieee80211_twt_params *twt_agrt) 2440 { 2441 u16 type = le16_to_cpu(twt_agrt->req_type); 2442 u8 exp; 2443 int i; 2444 2445 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type); 2446 for (i = 0; i < MT7996_MAX_STA_TWT_AGRT; i++) { 2447 struct mt7996_twt_flow *f; 2448 2449 if (!(msta->twt.flowid_mask & BIT(i))) 2450 continue; 2451 2452 f = &msta->twt.flow[i]; 2453 if (f->duration == twt_agrt->min_twt_dur && 2454 f->mantissa == twt_agrt->mantissa && 2455 f->exp == exp && 2456 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) && 2457 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) && 2458 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER)) 2459 return true; 2460 } 2461 2462 return false; 2463 } 2464 mt7996_mac_add_twt_setup(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct ieee80211_twt_setup * twt)2465 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 2466 struct ieee80211_sta *sta, 2467 struct ieee80211_twt_setup *twt) 2468 { 2469 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2470 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 2471 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2472 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2473 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2474 struct mt7996_dev *dev = mt7996_hw_dev(hw); 2475 struct mt7996_twt_flow *flow; 2476 u8 flowid, table_id, exp; 2477 2478 if (mt7996_mac_check_twt_req(twt)) 2479 goto out; 2480 2481 mutex_lock(&dev->mt76.mutex); 2482 2483 if (dev->twt.n_agrt == MT7996_MAX_TWT_AGRT) 2484 goto unlock; 2485 2486 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2487 goto unlock; 2488 2489 if (twt_agrt->min_twt_dur < MT7996_MIN_TWT_DUR) { 2490 setup_cmd = TWT_SETUP_CMD_DICTATE; 2491 twt_agrt->min_twt_dur = MT7996_MIN_TWT_DUR; 2492 goto unlock; 2493 } 2494 2495 if (mt7996_mac_twt_param_equal(msta, twt_agrt)) 2496 goto unlock; 2497 2498 flowid = ffs(~msta->twt.flowid_mask) - 1; 2499 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID); 2500 twt_agrt->req_type |= le16_encode_bits(flowid, 2501 IEEE80211_TWT_REQTYPE_FLOWID); 2502 2503 table_id = ffs(~dev->twt.table_mask) - 1; 2504 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2505 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2506 2507 flow = &msta->twt.flow[flowid]; 2508 memset(flow, 0, sizeof(*flow)); 2509 INIT_LIST_HEAD(&flow->list); 2510 flow->wcid = msta->wcid.idx; 2511 flow->table_id = table_id; 2512 flow->id = flowid; 2513 flow->duration = twt_agrt->min_twt_dur; 2514 flow->mantissa = twt_agrt->mantissa; 2515 flow->exp = exp; 2516 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2517 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2518 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2519 2520 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2521 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2522 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2523 u64 flow_tsf, curr_tsf; 2524 u32 rem; 2525 2526 flow->sched = true; 2527 flow->start_tsf = mt7996_mac_twt_sched_list_add(dev, flow); 2528 curr_tsf = __mt7996_get_tsf(hw, msta->vif); 2529 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2530 flow_tsf = curr_tsf + interval - rem; 2531 twt_agrt->twt = cpu_to_le64(flow_tsf); 2532 } else { 2533 list_add_tail(&flow->list, &dev->twt_list); 2534 } 2535 flow->tsf = le64_to_cpu(twt_agrt->twt); 2536 2537 if (mt7996_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2538 goto unlock; 2539 2540 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2541 dev->twt.table_mask |= BIT(table_id); 2542 msta->twt.flowid_mask |= BIT(flowid); 2543 dev->twt.n_agrt++; 2544 2545 unlock: 2546 mutex_unlock(&dev->mt76.mutex); 2547 out: 2548 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD); 2549 twt_agrt->req_type |= 2550 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD); 2551 twt->control = twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED; 2552 } 2553 mt7996_mac_twt_teardown_flow(struct mt7996_dev * dev,struct mt7996_sta * msta,u8 flowid)2554 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 2555 struct mt7996_sta *msta, 2556 u8 flowid) 2557 { 2558 struct mt7996_twt_flow *flow; 2559 2560 lockdep_assert_held(&dev->mt76.mutex); 2561 2562 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2563 return; 2564 2565 if (!(msta->twt.flowid_mask & BIT(flowid))) 2566 return; 2567 2568 flow = &msta->twt.flow[flowid]; 2569 if (mt7996_mcu_twt_agrt_update(dev, msta->vif, flow, 2570 MCU_TWT_AGRT_DELETE)) 2571 return; 2572 2573 list_del_init(&flow->list); 2574 msta->twt.flowid_mask &= ~BIT(flowid); 2575 dev->twt.table_mask &= ~BIT(flow->table_id); 2576 dev->twt.n_agrt--; 2577 } 2578