1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Standard PCI Hot Plug Driver 4 * 5 * Copyright (C) 1995,2001 Compaq Computer Corporation 6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 7 * Copyright (C) 2001 IBM Corp. 8 * Copyright (C) 2003-2004 Intel Corporation 9 * 10 * All rights reserved. 11 * 12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 13 * 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/types.h> 19 #include <linux/pci.h> 20 #include <linux/interrupt.h> 21 22 #include "shpchp.h" 23 24 /* Slot Available Register I field definition */ 25 #define SLOT_33MHZ 0x0000001f 26 #define SLOT_66MHZ_PCIX 0x00001f00 27 #define SLOT_100MHZ_PCIX 0x001f0000 28 #define SLOT_133MHZ_PCIX 0x1f000000 29 30 /* Slot Available Register II field definition */ 31 #define SLOT_66MHZ 0x0000001f 32 #define SLOT_66MHZ_PCIX_266 0x00000f00 33 #define SLOT_100MHZ_PCIX_266 0x0000f000 34 #define SLOT_133MHZ_PCIX_266 0x000f0000 35 #define SLOT_66MHZ_PCIX_533 0x00f00000 36 #define SLOT_100MHZ_PCIX_533 0x0f000000 37 #define SLOT_133MHZ_PCIX_533 0xf0000000 38 39 /* Slot Configuration */ 40 #define SLOT_NUM 0x0000001F 41 #define FIRST_DEV_NUM 0x00001F00 42 #define PSN 0x07FF0000 43 #define UPDOWN 0x20000000 44 #define MRLSENSOR 0x40000000 45 #define ATTN_BUTTON 0x80000000 46 47 /* 48 * Interrupt Locator Register definitions 49 */ 50 #define CMD_INTR_PENDING (1 << 0) 51 #define SLOT_INTR_PENDING(i) (1 << (i + 1)) 52 53 /* 54 * Controller SERR-INT Register 55 */ 56 #define GLOBAL_INTR_MASK (1 << 0) 57 #define GLOBAL_SERR_MASK (1 << 1) 58 #define COMMAND_INTR_MASK (1 << 2) 59 #define ARBITER_SERR_MASK (1 << 3) 60 #define COMMAND_DETECTED (1 << 16) 61 #define ARBITER_DETECTED (1 << 17) 62 #define SERR_INTR_RSVDZ_MASK 0xfffc0000 63 64 /* 65 * Logical Slot Register definitions 66 */ 67 #define SLOT_REG(i) (SLOT1 + (4 * i)) 68 69 #define SLOT_STATE_SHIFT (0) 70 #define SLOT_STATE_MASK (3 << 0) 71 #define SLOT_STATE_PWRONLY (1) 72 #define SLOT_STATE_ENABLED (2) 73 #define SLOT_STATE_DISABLED (3) 74 #define PWR_LED_STATE_SHIFT (2) 75 #define PWR_LED_STATE_MASK (3 << 2) 76 #define ATN_LED_STATE_SHIFT (4) 77 #define ATN_LED_STATE_MASK (3 << 4) 78 #define ATN_LED_STATE_ON (1) 79 #define ATN_LED_STATE_BLINK (2) 80 #define ATN_LED_STATE_OFF (3) 81 #define POWER_FAULT (1 << 6) 82 #define ATN_BUTTON (1 << 7) 83 #define MRL_SENSOR (1 << 8) 84 #define MHZ66_CAP (1 << 9) 85 #define PRSNT_SHIFT (10) 86 #define PRSNT_MASK (3 << 10) 87 #define PCIX_CAP_SHIFT (12) 88 #define PCIX_CAP_MASK_PI1 (3 << 12) 89 #define PCIX_CAP_MASK_PI2 (7 << 12) 90 #define PRSNT_CHANGE_DETECTED (1 << 16) 91 #define ISO_PFAULT_DETECTED (1 << 17) 92 #define BUTTON_PRESS_DETECTED (1 << 18) 93 #define MRL_CHANGE_DETECTED (1 << 19) 94 #define CON_PFAULT_DETECTED (1 << 20) 95 #define PRSNT_CHANGE_INTR_MASK (1 << 24) 96 #define ISO_PFAULT_INTR_MASK (1 << 25) 97 #define BUTTON_PRESS_INTR_MASK (1 << 26) 98 #define MRL_CHANGE_INTR_MASK (1 << 27) 99 #define CON_PFAULT_INTR_MASK (1 << 28) 100 #define MRL_CHANGE_SERR_MASK (1 << 29) 101 #define CON_PFAULT_SERR_MASK (1 << 30) 102 #define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21)) 103 104 /* 105 * SHPC Command Code definitions 106 * 107 * Slot Operation 00h - 3Fh 108 * Set Bus Segment Speed/Mode A 40h - 47h 109 * Power-Only All Slots 48h 110 * Enable All Slots 49h 111 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh 112 * Reserved Command Codes 60h - BFh 113 * Vendor Specific Commands C0h - FFh 114 */ 115 #define SET_SLOT_PWR 0x01 /* Slot Operation */ 116 #define SET_SLOT_ENABLE 0x02 117 #define SET_SLOT_DISABLE 0x03 118 #define SET_PWR_ON 0x04 119 #define SET_PWR_BLINK 0x08 120 #define SET_PWR_OFF 0x0c 121 #define SET_ATTN_ON 0x10 122 #define SET_ATTN_BLINK 0x20 123 #define SET_ATTN_OFF 0x30 124 #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ 125 #define SETA_PCI_66MHZ 0x41 126 #define SETA_PCIX_66MHZ 0x42 127 #define SETA_PCIX_100MHZ 0x43 128 #define SETA_PCIX_133MHZ 0x44 129 #define SETA_RESERVED1 0x45 130 #define SETA_RESERVED2 0x46 131 #define SETA_RESERVED3 0x47 132 #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ 133 #define SET_ENABLE_ALL 0x49 /* Enable All Slots */ 134 #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ 135 #define SETB_PCI_66MHZ 0x51 136 #define SETB_PCIX_66MHZ_PM 0x52 137 #define SETB_PCIX_100MHZ_PM 0x53 138 #define SETB_PCIX_133MHZ_PM 0x54 139 #define SETB_PCIX_66MHZ_EM 0x55 140 #define SETB_PCIX_100MHZ_EM 0x56 141 #define SETB_PCIX_133MHZ_EM 0x57 142 #define SETB_PCIX_66MHZ_266 0x58 143 #define SETB_PCIX_100MHZ_266 0x59 144 #define SETB_PCIX_133MHZ_266 0x5a 145 #define SETB_PCIX_66MHZ_533 0x5b 146 #define SETB_PCIX_100MHZ_533 0x5c 147 #define SETB_PCIX_133MHZ_533 0x5d 148 #define SETB_RESERVED1 0x5e 149 #define SETB_RESERVED2 0x5f 150 151 /* 152 * SHPC controller command error code 153 */ 154 #define SWITCH_OPEN 0x1 155 #define INVALID_CMD 0x2 156 #define INVALID_SPEED_MODE 0x4 157 158 /* 159 * For accessing SHPC Working Register Set via PCI Configuration Space 160 */ 161 #define DWORD_SELECT 0x2 162 #define DWORD_DATA 0x4 163 164 /* Field Offset in Logical Slot Register - byte boundary */ 165 #define SLOT_EVENT_LATCH 0x2 166 #define SLOT_SERR_INT_MASK 0x3 167 168 static irqreturn_t shpc_isr(int irq, void *dev_id); 169 static void start_int_poll_timer(struct controller *ctrl, int sec); 170 static int hpc_check_cmd_status(struct controller *ctrl); 171 shpc_readb(struct controller * ctrl,int reg)172 static inline u8 shpc_readb(struct controller *ctrl, int reg) 173 { 174 return readb(ctrl->creg + reg); 175 } 176 shpc_readw(struct controller * ctrl,int reg)177 static inline u16 shpc_readw(struct controller *ctrl, int reg) 178 { 179 return readw(ctrl->creg + reg); 180 } 181 shpc_writew(struct controller * ctrl,int reg,u16 val)182 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) 183 { 184 writew(val, ctrl->creg + reg); 185 } 186 shpc_readl(struct controller * ctrl,int reg)187 static inline u32 shpc_readl(struct controller *ctrl, int reg) 188 { 189 return readl(ctrl->creg + reg); 190 } 191 shpc_writel(struct controller * ctrl,int reg,u32 val)192 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) 193 { 194 writel(val, ctrl->creg + reg); 195 } 196 shpc_indirect_read(struct controller * ctrl,int index,u32 * value)197 static inline int shpc_indirect_read(struct controller *ctrl, int index, 198 u32 *value) 199 { 200 int rc; 201 u32 cap_offset = ctrl->cap_offset; 202 struct pci_dev *pdev = ctrl->pci_dev; 203 204 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); 205 if (rc) 206 return rc; 207 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); 208 } 209 210 /* 211 * This is the interrupt polling timeout function. 212 */ int_poll_timeout(struct timer_list * t)213 static void int_poll_timeout(struct timer_list *t) 214 { 215 struct controller *ctrl = from_timer(ctrl, t, poll_timer); 216 217 /* Poll for interrupt events. regs == NULL => polling */ 218 shpc_isr(0, ctrl); 219 220 if (!shpchp_poll_time) 221 shpchp_poll_time = 2; /* default polling interval is 2 sec */ 222 223 start_int_poll_timer(ctrl, shpchp_poll_time); 224 } 225 226 /* 227 * This function starts the interrupt polling timer. 228 */ start_int_poll_timer(struct controller * ctrl,int sec)229 static void start_int_poll_timer(struct controller *ctrl, int sec) 230 { 231 /* Clamp to sane value */ 232 if ((sec <= 0) || (sec > 60)) 233 sec = 2; 234 235 ctrl->poll_timer.expires = jiffies + sec * HZ; 236 add_timer(&ctrl->poll_timer); 237 } 238 is_ctrl_busy(struct controller * ctrl)239 static inline int is_ctrl_busy(struct controller *ctrl) 240 { 241 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS); 242 return cmd_status & 0x1; 243 } 244 245 /* 246 * Returns 1 if SHPC finishes executing a command within 1 sec, 247 * otherwise returns 0. 248 */ shpc_poll_ctrl_busy(struct controller * ctrl)249 static inline int shpc_poll_ctrl_busy(struct controller *ctrl) 250 { 251 int i; 252 253 if (!is_ctrl_busy(ctrl)) 254 return 1; 255 256 /* Check every 0.1 sec for a total of 1 sec */ 257 for (i = 0; i < 10; i++) { 258 msleep(100); 259 if (!is_ctrl_busy(ctrl)) 260 return 1; 261 } 262 263 return 0; 264 } 265 shpc_wait_cmd(struct controller * ctrl)266 static inline int shpc_wait_cmd(struct controller *ctrl) 267 { 268 int retval = 0; 269 unsigned long timeout = msecs_to_jiffies(1000); 270 int rc; 271 272 if (shpchp_poll_mode) 273 rc = shpc_poll_ctrl_busy(ctrl); 274 else 275 rc = wait_event_interruptible_timeout(ctrl->queue, 276 !is_ctrl_busy(ctrl), timeout); 277 if (!rc && is_ctrl_busy(ctrl)) { 278 retval = -EIO; 279 ctrl_err(ctrl, "Command not completed in 1000 msec\n"); 280 } else if (rc < 0) { 281 retval = -EINTR; 282 ctrl_info(ctrl, "Command was interrupted by a signal\n"); 283 } 284 285 return retval; 286 } 287 shpc_write_cmd(struct slot * slot,u8 t_slot,u8 cmd)288 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) 289 { 290 struct controller *ctrl = slot->ctrl; 291 u16 cmd_status; 292 int retval = 0; 293 u16 temp_word; 294 295 mutex_lock(&slot->ctrl->cmd_lock); 296 297 if (!shpc_poll_ctrl_busy(ctrl)) { 298 /* After 1 sec and the controller is still busy */ 299 ctrl_err(ctrl, "Controller is still busy after 1 sec\n"); 300 retval = -EBUSY; 301 goto out; 302 } 303 304 ++t_slot; 305 temp_word = (t_slot << 8) | (cmd & 0xFF); 306 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd); 307 308 /* To make sure the Controller Busy bit is 0 before we send out the 309 * command. 310 */ 311 shpc_writew(ctrl, CMD, temp_word); 312 313 /* 314 * Wait for command completion. 315 */ 316 retval = shpc_wait_cmd(slot->ctrl); 317 if (retval) 318 goto out; 319 320 cmd_status = hpc_check_cmd_status(slot->ctrl); 321 if (cmd_status) { 322 ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n", 323 cmd, cmd_status); 324 retval = -EIO; 325 } 326 out: 327 mutex_unlock(&slot->ctrl->cmd_lock); 328 return retval; 329 } 330 hpc_check_cmd_status(struct controller * ctrl)331 static int hpc_check_cmd_status(struct controller *ctrl) 332 { 333 int retval = 0; 334 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; 335 336 switch (cmd_status >> 1) { 337 case 0: 338 retval = 0; 339 break; 340 case 1: 341 retval = SWITCH_OPEN; 342 ctrl_err(ctrl, "Switch opened!\n"); 343 break; 344 case 2: 345 retval = INVALID_CMD; 346 ctrl_err(ctrl, "Invalid HPC command!\n"); 347 break; 348 case 4: 349 retval = INVALID_SPEED_MODE; 350 ctrl_err(ctrl, "Invalid bus speed/mode!\n"); 351 break; 352 default: 353 retval = cmd_status; 354 } 355 356 return retval; 357 } 358 359 hpc_get_attention_status(struct slot * slot,u8 * status)360 static int hpc_get_attention_status(struct slot *slot, u8 *status) 361 { 362 struct controller *ctrl = slot->ctrl; 363 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 364 u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; 365 366 switch (state) { 367 case ATN_LED_STATE_ON: 368 *status = 1; /* On */ 369 break; 370 case ATN_LED_STATE_BLINK: 371 *status = 2; /* Blink */ 372 break; 373 case ATN_LED_STATE_OFF: 374 *status = 0; /* Off */ 375 break; 376 default: 377 *status = 0xFF; /* Reserved */ 378 break; 379 } 380 381 return 0; 382 } 383 hpc_get_power_status(struct slot * slot,u8 * status)384 static int hpc_get_power_status(struct slot *slot, u8 *status) 385 { 386 struct controller *ctrl = slot->ctrl; 387 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 388 u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; 389 390 switch (state) { 391 case SLOT_STATE_PWRONLY: 392 *status = 2; /* Powered only */ 393 break; 394 case SLOT_STATE_ENABLED: 395 *status = 1; /* Enabled */ 396 break; 397 case SLOT_STATE_DISABLED: 398 *status = 0; /* Disabled */ 399 break; 400 default: 401 *status = 0xFF; /* Reserved */ 402 break; 403 } 404 405 return 0; 406 } 407 408 hpc_get_latch_status(struct slot * slot,u8 * status)409 static int hpc_get_latch_status(struct slot *slot, u8 *status) 410 { 411 struct controller *ctrl = slot->ctrl; 412 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 413 414 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ 415 416 return 0; 417 } 418 hpc_get_adapter_status(struct slot * slot,u8 * status)419 static int hpc_get_adapter_status(struct slot *slot, u8 *status) 420 { 421 struct controller *ctrl = slot->ctrl; 422 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 423 u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; 424 425 *status = (state != 0x3) ? 1 : 0; 426 427 return 0; 428 } 429 hpc_get_prog_int(struct slot * slot,u8 * prog_int)430 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) 431 { 432 struct controller *ctrl = slot->ctrl; 433 434 *prog_int = shpc_readb(ctrl, PROG_INTERFACE); 435 436 return 0; 437 } 438 hpc_get_adapter_speed(struct slot * slot,enum pci_bus_speed * value)439 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 440 { 441 int retval = 0; 442 struct controller *ctrl = slot->ctrl; 443 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 444 u8 m66_cap = !!(slot_reg & MHZ66_CAP); 445 u8 pi, pcix_cap; 446 447 retval = hpc_get_prog_int(slot, &pi); 448 if (retval) 449 return retval; 450 451 switch (pi) { 452 case 1: 453 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; 454 break; 455 case 2: 456 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; 457 break; 458 default: 459 return -ENODEV; 460 } 461 462 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", 463 __func__, slot_reg, pcix_cap, m66_cap); 464 465 switch (pcix_cap) { 466 case 0x0: 467 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; 468 break; 469 case 0x1: 470 *value = PCI_SPEED_66MHz_PCIX; 471 break; 472 case 0x3: 473 *value = PCI_SPEED_133MHz_PCIX; 474 break; 475 case 0x4: 476 *value = PCI_SPEED_133MHz_PCIX_266; 477 break; 478 case 0x5: 479 *value = PCI_SPEED_133MHz_PCIX_533; 480 break; 481 case 0x2: 482 default: 483 *value = PCI_SPEED_UNKNOWN; 484 retval = -ENODEV; 485 break; 486 } 487 488 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value); 489 return retval; 490 } 491 hpc_query_power_fault(struct slot * slot)492 static int hpc_query_power_fault(struct slot *slot) 493 { 494 struct controller *ctrl = slot->ctrl; 495 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 496 497 /* Note: Logic 0 => fault */ 498 return !(slot_reg & POWER_FAULT); 499 } 500 hpc_set_attention_status(struct slot * slot,u8 value)501 static int hpc_set_attention_status(struct slot *slot, u8 value) 502 { 503 u8 slot_cmd = 0; 504 505 switch (value) { 506 case 0: 507 slot_cmd = SET_ATTN_OFF; /* OFF */ 508 break; 509 case 1: 510 slot_cmd = SET_ATTN_ON; /* ON */ 511 break; 512 case 2: 513 slot_cmd = SET_ATTN_BLINK; /* BLINK */ 514 break; 515 default: 516 return -1; 517 } 518 519 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 520 } 521 522 hpc_set_green_led_on(struct slot * slot)523 static void hpc_set_green_led_on(struct slot *slot) 524 { 525 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); 526 } 527 hpc_set_green_led_off(struct slot * slot)528 static void hpc_set_green_led_off(struct slot *slot) 529 { 530 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); 531 } 532 hpc_set_green_led_blink(struct slot * slot)533 static void hpc_set_green_led_blink(struct slot *slot) 534 { 535 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); 536 } 537 hpc_release_ctlr(struct controller * ctrl)538 static void hpc_release_ctlr(struct controller *ctrl) 539 { 540 int i; 541 u32 slot_reg, serr_int; 542 543 /* 544 * Mask event interrupts and SERRs of all slots 545 */ 546 for (i = 0; i < ctrl->num_slots; i++) { 547 slot_reg = shpc_readl(ctrl, SLOT_REG(i)); 548 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 549 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 550 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 551 CON_PFAULT_SERR_MASK); 552 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 553 shpc_writel(ctrl, SLOT_REG(i), slot_reg); 554 } 555 556 cleanup_slots(ctrl); 557 558 /* 559 * Mask SERR and System Interrupt generation 560 */ 561 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 562 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 563 COMMAND_INTR_MASK | ARBITER_SERR_MASK); 564 serr_int &= ~SERR_INTR_RSVDZ_MASK; 565 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 566 567 if (shpchp_poll_mode) 568 del_timer(&ctrl->poll_timer); 569 else { 570 free_irq(ctrl->pci_dev->irq, ctrl); 571 pci_disable_msi(ctrl->pci_dev); 572 } 573 574 iounmap(ctrl->creg); 575 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 576 } 577 hpc_power_on_slot(struct slot * slot)578 static int hpc_power_on_slot(struct slot *slot) 579 { 580 int retval; 581 582 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); 583 if (retval) 584 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 585 586 return retval; 587 } 588 hpc_slot_enable(struct slot * slot)589 static int hpc_slot_enable(struct slot *slot) 590 { 591 int retval; 592 593 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ 594 retval = shpc_write_cmd(slot, slot->hp_slot, 595 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); 596 if (retval) 597 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 598 599 return retval; 600 } 601 hpc_slot_disable(struct slot * slot)602 static int hpc_slot_disable(struct slot *slot) 603 { 604 int retval; 605 606 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ 607 retval = shpc_write_cmd(slot, slot->hp_slot, 608 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); 609 if (retval) 610 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 611 612 return retval; 613 } 614 shpc_get_cur_bus_speed(struct controller * ctrl)615 static int shpc_get_cur_bus_speed(struct controller *ctrl) 616 { 617 int retval = 0; 618 struct pci_bus *bus = ctrl->pci_dev->subordinate; 619 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 620 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); 621 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 622 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); 623 624 if ((pi == 1) && (speed_mode > 4)) { 625 retval = -ENODEV; 626 goto out; 627 } 628 629 switch (speed_mode) { 630 case 0x0: 631 bus_speed = PCI_SPEED_33MHz; 632 break; 633 case 0x1: 634 bus_speed = PCI_SPEED_66MHz; 635 break; 636 case 0x2: 637 bus_speed = PCI_SPEED_66MHz_PCIX; 638 break; 639 case 0x3: 640 bus_speed = PCI_SPEED_100MHz_PCIX; 641 break; 642 case 0x4: 643 bus_speed = PCI_SPEED_133MHz_PCIX; 644 break; 645 case 0x5: 646 bus_speed = PCI_SPEED_66MHz_PCIX_ECC; 647 break; 648 case 0x6: 649 bus_speed = PCI_SPEED_100MHz_PCIX_ECC; 650 break; 651 case 0x7: 652 bus_speed = PCI_SPEED_133MHz_PCIX_ECC; 653 break; 654 case 0x8: 655 bus_speed = PCI_SPEED_66MHz_PCIX_266; 656 break; 657 case 0x9: 658 bus_speed = PCI_SPEED_100MHz_PCIX_266; 659 break; 660 case 0xa: 661 bus_speed = PCI_SPEED_133MHz_PCIX_266; 662 break; 663 case 0xb: 664 bus_speed = PCI_SPEED_66MHz_PCIX_533; 665 break; 666 case 0xc: 667 bus_speed = PCI_SPEED_100MHz_PCIX_533; 668 break; 669 case 0xd: 670 bus_speed = PCI_SPEED_133MHz_PCIX_533; 671 break; 672 default: 673 retval = -ENODEV; 674 break; 675 } 676 677 out: 678 bus->cur_bus_speed = bus_speed; 679 dbg("Current bus speed = %d\n", bus_speed); 680 return retval; 681 } 682 683 hpc_set_bus_speed_mode(struct slot * slot,enum pci_bus_speed value)684 static int hpc_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value) 685 { 686 int retval; 687 struct controller *ctrl = slot->ctrl; 688 u8 pi, cmd; 689 690 pi = shpc_readb(ctrl, PROG_INTERFACE); 691 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) 692 return -EINVAL; 693 694 switch (value) { 695 case PCI_SPEED_33MHz: 696 cmd = SETA_PCI_33MHZ; 697 break; 698 case PCI_SPEED_66MHz: 699 cmd = SETA_PCI_66MHZ; 700 break; 701 case PCI_SPEED_66MHz_PCIX: 702 cmd = SETA_PCIX_66MHZ; 703 break; 704 case PCI_SPEED_100MHz_PCIX: 705 cmd = SETA_PCIX_100MHZ; 706 break; 707 case PCI_SPEED_133MHz_PCIX: 708 cmd = SETA_PCIX_133MHZ; 709 break; 710 case PCI_SPEED_66MHz_PCIX_ECC: 711 cmd = SETB_PCIX_66MHZ_EM; 712 break; 713 case PCI_SPEED_100MHz_PCIX_ECC: 714 cmd = SETB_PCIX_100MHZ_EM; 715 break; 716 case PCI_SPEED_133MHz_PCIX_ECC: 717 cmd = SETB_PCIX_133MHZ_EM; 718 break; 719 case PCI_SPEED_66MHz_PCIX_266: 720 cmd = SETB_PCIX_66MHZ_266; 721 break; 722 case PCI_SPEED_100MHz_PCIX_266: 723 cmd = SETB_PCIX_100MHZ_266; 724 break; 725 case PCI_SPEED_133MHz_PCIX_266: 726 cmd = SETB_PCIX_133MHZ_266; 727 break; 728 case PCI_SPEED_66MHz_PCIX_533: 729 cmd = SETB_PCIX_66MHZ_533; 730 break; 731 case PCI_SPEED_100MHz_PCIX_533: 732 cmd = SETB_PCIX_100MHZ_533; 733 break; 734 case PCI_SPEED_133MHz_PCIX_533: 735 cmd = SETB_PCIX_133MHZ_533; 736 break; 737 default: 738 return -EINVAL; 739 } 740 741 retval = shpc_write_cmd(slot, 0, cmd); 742 if (retval) 743 ctrl_err(ctrl, "%s: Write command failed!\n", __func__); 744 else 745 shpc_get_cur_bus_speed(ctrl); 746 747 return retval; 748 } 749 shpc_isr(int irq,void * dev_id)750 static irqreturn_t shpc_isr(int irq, void *dev_id) 751 { 752 struct controller *ctrl = (struct controller *)dev_id; 753 u32 serr_int, slot_reg, intr_loc, intr_loc2; 754 int hp_slot; 755 756 /* Check to see if it was our interrupt */ 757 intr_loc = shpc_readl(ctrl, INTR_LOC); 758 if (!intr_loc) 759 return IRQ_NONE; 760 761 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc); 762 763 if (!shpchp_poll_mode) { 764 /* 765 * Mask Global Interrupt Mask - see implementation 766 * note on p. 139 of SHPC spec rev 1.0 767 */ 768 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 769 serr_int |= GLOBAL_INTR_MASK; 770 serr_int &= ~SERR_INTR_RSVDZ_MASK; 771 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 772 773 intr_loc2 = shpc_readl(ctrl, INTR_LOC); 774 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2); 775 } 776 777 if (intr_loc & CMD_INTR_PENDING) { 778 /* 779 * Command Complete Interrupt Pending 780 * RO only - clear by writing 1 to the Command Completion 781 * Detect bit in Controller SERR-INT register 782 */ 783 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 784 serr_int &= ~SERR_INTR_RSVDZ_MASK; 785 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 786 787 wake_up_interruptible(&ctrl->queue); 788 } 789 790 if (!(intr_loc & ~CMD_INTR_PENDING)) 791 goto out; 792 793 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 794 /* To find out which slot has interrupt pending */ 795 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) 796 continue; 797 798 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 799 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n", 800 hp_slot, slot_reg); 801 802 if (slot_reg & MRL_CHANGE_DETECTED) 803 shpchp_handle_switch_change(hp_slot, ctrl); 804 805 if (slot_reg & BUTTON_PRESS_DETECTED) 806 shpchp_handle_attention_button(hp_slot, ctrl); 807 808 if (slot_reg & PRSNT_CHANGE_DETECTED) 809 shpchp_handle_presence_change(hp_slot, ctrl); 810 811 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) 812 shpchp_handle_power_fault(hp_slot, ctrl); 813 814 /* Clear all slot events */ 815 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 816 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 817 } 818 out: 819 if (!shpchp_poll_mode) { 820 /* Unmask Global Interrupt Mask */ 821 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 822 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); 823 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 824 } 825 826 return IRQ_HANDLED; 827 } 828 shpc_get_max_bus_speed(struct controller * ctrl)829 static int shpc_get_max_bus_speed(struct controller *ctrl) 830 { 831 int retval = 0; 832 struct pci_bus *bus = ctrl->pci_dev->subordinate; 833 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 834 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 835 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); 836 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); 837 838 if (pi == 2) { 839 if (slot_avail2 & SLOT_133MHZ_PCIX_533) 840 bus_speed = PCI_SPEED_133MHz_PCIX_533; 841 else if (slot_avail2 & SLOT_100MHZ_PCIX_533) 842 bus_speed = PCI_SPEED_100MHz_PCIX_533; 843 else if (slot_avail2 & SLOT_66MHZ_PCIX_533) 844 bus_speed = PCI_SPEED_66MHz_PCIX_533; 845 else if (slot_avail2 & SLOT_133MHZ_PCIX_266) 846 bus_speed = PCI_SPEED_133MHz_PCIX_266; 847 else if (slot_avail2 & SLOT_100MHZ_PCIX_266) 848 bus_speed = PCI_SPEED_100MHz_PCIX_266; 849 else if (slot_avail2 & SLOT_66MHZ_PCIX_266) 850 bus_speed = PCI_SPEED_66MHz_PCIX_266; 851 } 852 853 if (bus_speed == PCI_SPEED_UNKNOWN) { 854 if (slot_avail1 & SLOT_133MHZ_PCIX) 855 bus_speed = PCI_SPEED_133MHz_PCIX; 856 else if (slot_avail1 & SLOT_100MHZ_PCIX) 857 bus_speed = PCI_SPEED_100MHz_PCIX; 858 else if (slot_avail1 & SLOT_66MHZ_PCIX) 859 bus_speed = PCI_SPEED_66MHz_PCIX; 860 else if (slot_avail2 & SLOT_66MHZ) 861 bus_speed = PCI_SPEED_66MHz; 862 else if (slot_avail1 & SLOT_33MHZ) 863 bus_speed = PCI_SPEED_33MHz; 864 else 865 retval = -ENODEV; 866 } 867 868 bus->max_bus_speed = bus_speed; 869 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed); 870 871 return retval; 872 } 873 874 static const struct hpc_ops shpchp_hpc_ops = { 875 .power_on_slot = hpc_power_on_slot, 876 .slot_enable = hpc_slot_enable, 877 .slot_disable = hpc_slot_disable, 878 .set_bus_speed_mode = hpc_set_bus_speed_mode, 879 .set_attention_status = hpc_set_attention_status, 880 .get_power_status = hpc_get_power_status, 881 .get_attention_status = hpc_get_attention_status, 882 .get_latch_status = hpc_get_latch_status, 883 .get_adapter_status = hpc_get_adapter_status, 884 885 .get_adapter_speed = hpc_get_adapter_speed, 886 .get_prog_int = hpc_get_prog_int, 887 888 .query_power_fault = hpc_query_power_fault, 889 .green_led_on = hpc_set_green_led_on, 890 .green_led_off = hpc_set_green_led_off, 891 .green_led_blink = hpc_set_green_led_blink, 892 893 .release_ctlr = hpc_release_ctlr, 894 }; 895 shpc_init(struct controller * ctrl,struct pci_dev * pdev)896 int shpc_init(struct controller *ctrl, struct pci_dev *pdev) 897 { 898 int rc = -1, num_slots = 0; 899 u8 hp_slot; 900 u32 shpc_base_offset; 901 u32 tempdword, slot_reg, slot_config; 902 u8 i; 903 904 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ 905 ctrl_dbg(ctrl, "Hotplug Controller:\n"); 906 907 if (pdev->vendor == PCI_VENDOR_ID_AMD && 908 pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) { 909 /* amd shpc driver doesn't use Base Offset; assume 0 */ 910 ctrl->mmio_base = pci_resource_start(pdev, 0); 911 ctrl->mmio_size = pci_resource_len(pdev, 0); 912 } else { 913 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); 914 if (!ctrl->cap_offset) { 915 ctrl_err(ctrl, "Cannot find PCI capability\n"); 916 goto abort; 917 } 918 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset); 919 920 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); 921 if (rc) { 922 ctrl_err(ctrl, "Cannot read base_offset\n"); 923 goto abort; 924 } 925 926 rc = shpc_indirect_read(ctrl, 3, &tempdword); 927 if (rc) { 928 ctrl_err(ctrl, "Cannot read slot config\n"); 929 goto abort; 930 } 931 num_slots = tempdword & SLOT_NUM; 932 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots); 933 934 for (i = 0; i < 9 + num_slots; i++) { 935 rc = shpc_indirect_read(ctrl, i, &tempdword); 936 if (rc) { 937 ctrl_err(ctrl, "Cannot read creg (index = %d)\n", 938 i); 939 goto abort; 940 } 941 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword); 942 } 943 944 ctrl->mmio_base = 945 pci_resource_start(pdev, 0) + shpc_base_offset; 946 ctrl->mmio_size = 0x24 + 0x4 * num_slots; 947 } 948 949 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", 950 pdev->vendor, pdev->device, pdev->subsystem_vendor, 951 pdev->subsystem_device); 952 953 rc = pci_enable_device(pdev); 954 if (rc) { 955 ctrl_err(ctrl, "pci_enable_device failed\n"); 956 goto abort; 957 } 958 959 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { 960 ctrl_err(ctrl, "Cannot reserve MMIO region\n"); 961 rc = -1; 962 goto abort; 963 } 964 965 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); 966 if (!ctrl->creg) { 967 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n", 968 ctrl->mmio_size, ctrl->mmio_base); 969 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 970 rc = -1; 971 goto abort; 972 } 973 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg); 974 975 mutex_init(&ctrl->crit_sect); 976 mutex_init(&ctrl->cmd_lock); 977 978 /* Setup wait queue */ 979 init_waitqueue_head(&ctrl->queue); 980 981 ctrl->hpc_ops = &shpchp_hpc_ops; 982 983 /* Return PCI Controller Info */ 984 slot_config = shpc_readl(ctrl, SLOT_CONFIG); 985 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; 986 ctrl->num_slots = slot_config & SLOT_NUM; 987 ctrl->first_slot = (slot_config & PSN) >> 16; 988 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1; 989 990 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ 991 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 992 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 993 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 994 COMMAND_INTR_MASK | ARBITER_SERR_MASK); 995 tempdword &= ~SERR_INTR_RSVDZ_MASK; 996 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 997 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 998 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 999 1000 /* Mask the MRL sensor SERR Mask of individual slot in 1001 * Slot SERR-INT Mask & clear all the existing event if any 1002 */ 1003 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1004 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1005 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", 1006 hp_slot, slot_reg); 1007 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1008 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1009 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 1010 CON_PFAULT_SERR_MASK); 1011 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 1012 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 1013 } 1014 1015 if (shpchp_poll_mode) { 1016 /* Install interrupt polling timer. Start with 10 sec delay */ 1017 timer_setup(&ctrl->poll_timer, int_poll_timeout, 0); 1018 start_int_poll_timer(ctrl, 10); 1019 } else { 1020 /* Installs the interrupt handler */ 1021 rc = pci_enable_msi(pdev); 1022 if (rc) { 1023 ctrl_info(ctrl, "Can't get msi for the hotplug controller\n"); 1024 ctrl_info(ctrl, "Use INTx for the hotplug controller\n"); 1025 } else { 1026 pci_set_master(pdev); 1027 } 1028 1029 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, 1030 MY_NAME, (void *)ctrl); 1031 ctrl_dbg(ctrl, "request_irq %d (returns %d)\n", 1032 ctrl->pci_dev->irq, rc); 1033 if (rc) { 1034 ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n", 1035 ctrl->pci_dev->irq); 1036 goto abort_iounmap; 1037 } 1038 } 1039 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq); 1040 1041 shpc_get_max_bus_speed(ctrl); 1042 shpc_get_cur_bus_speed(ctrl); 1043 1044 /* 1045 * Unmask all event interrupts of all slots 1046 */ 1047 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1048 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1049 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", 1050 hp_slot, slot_reg); 1051 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1052 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1053 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); 1054 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 1055 } 1056 if (!shpchp_poll_mode) { 1057 /* Unmask all general input interrupts and SERR */ 1058 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1059 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | 1060 SERR_INTR_RSVDZ_MASK); 1061 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1062 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1063 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 1064 } 1065 1066 return 0; 1067 1068 /* We end up here for the many possible ways to fail this API. */ 1069 abort_iounmap: 1070 iounmap(ctrl->creg); 1071 abort: 1072 return rc; 1073 } 1074