1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <dt-bindings/phy/phy.h>
9 #include <linux/clk.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of.h>
12 #include <linux/phy/phy.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/reset.h>
16 #include <linux/units.h>
17
18 #define BIT_WRITEABLE_SHIFT 16
19 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ)
20 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ)
21 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
22
23 /* COMBO PHY REG */
24 #define PHYREG6 0x14
25 #define PHYREG6_PLL_DIV_MASK GENMASK(7, 6)
26 #define PHYREG6_PLL_DIV_SHIFT 6
27 #define PHYREG6_PLL_DIV_2 1
28
29 #define PHYREG7 0x18
30 #define PHYREG7_TX_RTERM_MASK GENMASK(7, 4)
31 #define PHYREG7_TX_RTERM_SHIFT 4
32 #define PHYREG7_TX_RTERM_50OHM 8
33 #define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
34 #define PHYREG7_RX_RTERM_SHIFT 0
35 #define PHYREG7_RX_RTERM_44OHM 15
36
37 #define PHYREG8 0x1C
38 #define PHYREG8_SSC_EN BIT(4)
39
40 #define PHYREG11 0x28
41 #define PHYREG11_SU_TRIM_0_7 0xF0
42
43 #define PHYREG12 0x2C
44 #define PHYREG12_PLL_LPF_ADJ_VALUE 4
45
46 #define PHYREG13 0x30
47 #define PHYREG13_RESISTER_MASK GENMASK(5, 4)
48 #define PHYREG13_RESISTER_SHIFT 0x4
49 #define PHYREG13_RESISTER_HIGH_Z 3
50 #define PHYREG13_CKRCV_AMP0 BIT(7)
51
52 #define PHYREG14 0x34
53 #define PHYREG14_CKRCV_AMP1 BIT(0)
54
55 #define PHYREG15 0x38
56 #define PHYREG15_CTLE_EN BIT(0)
57 #define PHYREG15_SSC_CNT_MASK GENMASK(7, 6)
58 #define PHYREG15_SSC_CNT_SHIFT 6
59 #define PHYREG15_SSC_CNT_VALUE 1
60
61 #define PHYREG16 0x3C
62 #define PHYREG16_SSC_CNT_VALUE 0x5f
63
64 #define PHYREG18 0x44
65 #define PHYREG18_PLL_LOOP 0x32
66
67 #define PHYREG27 0x6C
68 #define PHYREG27_RX_TRIM_RK3588 0x4C
69
70 #define PHYREG32 0x7C
71 #define PHYREG32_SSC_MASK GENMASK(7, 4)
72 #define PHYREG32_SSC_DIR_SHIFT 4
73 #define PHYREG32_SSC_UPWARD 0
74 #define PHYREG32_SSC_DOWNWARD 1
75 #define PHYREG32_SSC_OFFSET_SHIFT 6
76 #define PHYREG32_SSC_OFFSET_500PPM 1
77
78 #define PHYREG33 0x80
79 #define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
80 #define PHYREG33_PLL_KVCO_SHIFT 2
81 #define PHYREG33_PLL_KVCO_VALUE 2
82
83 struct rockchip_combphy_priv;
84
85 struct combphy_reg {
86 u16 offset;
87 u16 bitend;
88 u16 bitstart;
89 u16 disable;
90 u16 enable;
91 };
92
93 struct rockchip_combphy_grfcfg {
94 struct combphy_reg pcie_mode_set;
95 struct combphy_reg usb_mode_set;
96 struct combphy_reg sgmii_mode_set;
97 struct combphy_reg qsgmii_mode_set;
98 struct combphy_reg pipe_rxterm_set;
99 struct combphy_reg pipe_txelec_set;
100 struct combphy_reg pipe_txcomp_set;
101 struct combphy_reg pipe_clk_25m;
102 struct combphy_reg pipe_clk_100m;
103 struct combphy_reg pipe_phymode_sel;
104 struct combphy_reg pipe_rate_sel;
105 struct combphy_reg pipe_rxterm_sel;
106 struct combphy_reg pipe_txelec_sel;
107 struct combphy_reg pipe_txcomp_sel;
108 struct combphy_reg pipe_clk_ext;
109 struct combphy_reg pipe_sel_usb;
110 struct combphy_reg pipe_sel_qsgmii;
111 struct combphy_reg pipe_phy_status;
112 struct combphy_reg con0_for_pcie;
113 struct combphy_reg con1_for_pcie;
114 struct combphy_reg con2_for_pcie;
115 struct combphy_reg con3_for_pcie;
116 struct combphy_reg con0_for_sata;
117 struct combphy_reg con1_for_sata;
118 struct combphy_reg con2_for_sata;
119 struct combphy_reg con3_for_sata;
120 struct combphy_reg pipe_con0_for_sata;
121 struct combphy_reg pipe_con1_for_sata;
122 struct combphy_reg pipe_xpcs_phy_ready;
123 struct combphy_reg pipe_pcie1l0_sel;
124 struct combphy_reg pipe_pcie1l1_sel;
125 };
126
127 struct rockchip_combphy_cfg {
128 unsigned int num_phys;
129 unsigned int phy_ids[3];
130 const struct rockchip_combphy_grfcfg *grfcfg;
131 int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
132 };
133
134 struct rockchip_combphy_priv {
135 u8 type;
136 int id;
137 void __iomem *mmio;
138 int num_clks;
139 struct clk_bulk_data *clks;
140 struct device *dev;
141 struct regmap *pipe_grf;
142 struct regmap *phy_grf;
143 struct phy *phy;
144 struct reset_control *phy_rst;
145 const struct rockchip_combphy_cfg *cfg;
146 bool enable_ssc;
147 bool ext_refclk;
148 struct clk *refclk;
149 };
150
rockchip_combphy_updatel(struct rockchip_combphy_priv * priv,int mask,int val,int reg)151 static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
152 int mask, int val, int reg)
153 {
154 unsigned int temp;
155
156 temp = readl(priv->mmio + reg);
157 temp = (temp & ~(mask)) | val;
158 writel(temp, priv->mmio + reg);
159 }
160
rockchip_combphy_param_write(struct regmap * base,const struct combphy_reg * reg,bool en)161 static int rockchip_combphy_param_write(struct regmap *base,
162 const struct combphy_reg *reg, bool en)
163 {
164 u32 val, mask, tmp;
165
166 tmp = en ? reg->enable : reg->disable;
167 mask = GENMASK(reg->bitend, reg->bitstart);
168 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
169
170 return regmap_write(base, reg->offset, val);
171 }
172
rockchip_combphy_is_ready(struct rockchip_combphy_priv * priv)173 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
174 {
175 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
176 u32 mask, val;
177
178 mask = GENMASK(cfg->pipe_phy_status.bitend,
179 cfg->pipe_phy_status.bitstart);
180
181 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
182 val = (val & mask) >> cfg->pipe_phy_status.bitstart;
183
184 return val;
185 }
186
rockchip_combphy_init(struct phy * phy)187 static int rockchip_combphy_init(struct phy *phy)
188 {
189 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
190 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
191 u32 val;
192 int ret;
193
194 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
195 if (ret) {
196 dev_err(priv->dev, "failed to enable clks\n");
197 return ret;
198 }
199
200 switch (priv->type) {
201 case PHY_TYPE_PCIE:
202 case PHY_TYPE_USB3:
203 case PHY_TYPE_SATA:
204 case PHY_TYPE_SGMII:
205 case PHY_TYPE_QSGMII:
206 if (priv->cfg->combphy_cfg)
207 ret = priv->cfg->combphy_cfg(priv);
208 break;
209 default:
210 dev_err(priv->dev, "incompatible PHY type\n");
211 ret = -EINVAL;
212 break;
213 }
214
215 if (ret) {
216 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
217 goto err_clk;
218 }
219
220 ret = reset_control_deassert(priv->phy_rst);
221 if (ret)
222 goto err_clk;
223
224 if (priv->type == PHY_TYPE_USB3) {
225 ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
226 priv, val,
227 val == cfg->pipe_phy_status.enable,
228 10, 1000);
229 if (ret)
230 dev_warn(priv->dev, "wait phy status ready timeout\n");
231 }
232
233 return 0;
234
235 err_clk:
236 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
237
238 return ret;
239 }
240
rockchip_combphy_exit(struct phy * phy)241 static int rockchip_combphy_exit(struct phy *phy)
242 {
243 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
244
245 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
246 reset_control_assert(priv->phy_rst);
247
248 return 0;
249 }
250
251 static const struct phy_ops rochchip_combphy_ops = {
252 .init = rockchip_combphy_init,
253 .exit = rockchip_combphy_exit,
254 .owner = THIS_MODULE,
255 };
256
rockchip_combphy_xlate(struct device * dev,struct of_phandle_args * args)257 static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
258 {
259 struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
260
261 if (args->args_count != 1) {
262 dev_err(dev, "invalid number of arguments\n");
263 return ERR_PTR(-EINVAL);
264 }
265
266 if (priv->type != PHY_NONE && priv->type != args->args[0])
267 dev_warn(dev, "phy type select %d overwriting type %d\n",
268 args->args[0], priv->type);
269
270 priv->type = args->args[0];
271
272 return priv->phy;
273 }
274
rockchip_combphy_parse_dt(struct device * dev,struct rockchip_combphy_priv * priv)275 static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
276 {
277 int i;
278
279 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
280 if (priv->num_clks < 1)
281 return -EINVAL;
282
283 priv->refclk = NULL;
284 for (i = 0; i < priv->num_clks; i++) {
285 if (!strncmp(priv->clks[i].id, "ref", 3)) {
286 priv->refclk = priv->clks[i].clk;
287 break;
288 }
289 }
290
291 if (!priv->refclk) {
292 dev_err(dev, "no refclk found\n");
293 return -EINVAL;
294 }
295
296 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
297 if (IS_ERR(priv->pipe_grf)) {
298 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
299 return PTR_ERR(priv->pipe_grf);
300 }
301
302 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
303 if (IS_ERR(priv->phy_grf)) {
304 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
305 return PTR_ERR(priv->phy_grf);
306 }
307
308 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
309
310 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
311
312 priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy");
313 /* fallback to old behaviour */
314 if (PTR_ERR(priv->phy_rst) == -ENOENT)
315 priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
316 if (IS_ERR(priv->phy_rst))
317 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
318
319 return 0;
320 }
321
rockchip_combphy_probe(struct platform_device * pdev)322 static int rockchip_combphy_probe(struct platform_device *pdev)
323 {
324 struct phy_provider *phy_provider;
325 struct device *dev = &pdev->dev;
326 struct rockchip_combphy_priv *priv;
327 const struct rockchip_combphy_cfg *phy_cfg;
328 struct resource *res;
329 int ret, id;
330
331 phy_cfg = of_device_get_match_data(dev);
332 if (!phy_cfg) {
333 dev_err(dev, "no OF match data provided\n");
334 return -EINVAL;
335 }
336
337 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
338 if (!priv)
339 return -ENOMEM;
340
341 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
342 if (IS_ERR(priv->mmio)) {
343 ret = PTR_ERR(priv->mmio);
344 return ret;
345 }
346
347 /* find the phy-id from the io address */
348 priv->id = -ENODEV;
349 for (id = 0; id < phy_cfg->num_phys; id++) {
350 if (res->start == phy_cfg->phy_ids[id]) {
351 priv->id = id;
352 break;
353 }
354 }
355
356 priv->dev = dev;
357 priv->type = PHY_NONE;
358 priv->cfg = phy_cfg;
359
360 ret = rockchip_combphy_parse_dt(dev, priv);
361 if (ret)
362 return ret;
363
364 ret = reset_control_assert(priv->phy_rst);
365 if (ret) {
366 dev_err(dev, "failed to reset phy\n");
367 return ret;
368 }
369
370 priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
371 if (IS_ERR(priv->phy)) {
372 dev_err(dev, "failed to create combphy\n");
373 return PTR_ERR(priv->phy);
374 }
375
376 dev_set_drvdata(dev, priv);
377 phy_set_drvdata(priv->phy, priv);
378
379 phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
380
381 return PTR_ERR_OR_ZERO(phy_provider);
382 }
383
rk3568_combphy_cfg(struct rockchip_combphy_priv * priv)384 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
385 {
386 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
387 unsigned long rate;
388 u32 val;
389
390 switch (priv->type) {
391 case PHY_TYPE_PCIE:
392 /* Set SSC downward spread spectrum. */
393 rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
394 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
395 PHYREG32);
396
397 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
398 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
399 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
400 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
401 break;
402
403 case PHY_TYPE_USB3:
404 /* Set SSC downward spread spectrum. */
405 rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
406 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
407 PHYREG32);
408
409 /* Enable adaptive CTLE for USB3.0 Rx. */
410 val = readl(priv->mmio + PHYREG15);
411 val |= PHYREG15_CTLE_EN;
412 writel(val, priv->mmio + PHYREG15);
413
414 /* Set PLL KVCO fine tuning signals. */
415 rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
416 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
417 PHYREG33);
418
419 /* Enable controlling random jitter. */
420 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
421
422 /* Set PLL input clock divider 1/2. */
423 rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
424 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
425 PHYREG6);
426
427 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
428 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
429
430 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
431 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
432 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
433 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
434 break;
435
436 case PHY_TYPE_SATA:
437 /* Enable adaptive CTLE for SATA Rx. */
438 val = readl(priv->mmio + PHYREG15);
439 val |= PHYREG15_CTLE_EN;
440 writel(val, priv->mmio + PHYREG15);
441 /*
442 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
443 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
444 */
445 val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
446 val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
447 writel(val, priv->mmio + PHYREG7);
448
449 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
450 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
451 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
452 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
453 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
454 break;
455
456 case PHY_TYPE_SGMII:
457 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
458 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
459 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
460 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
461 break;
462
463 case PHY_TYPE_QSGMII:
464 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
465 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
466 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
467 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
468 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
469 break;
470
471 default:
472 dev_err(priv->dev, "incompatible PHY type\n");
473 return -EINVAL;
474 }
475
476 rate = clk_get_rate(priv->refclk);
477
478 switch (rate) {
479 case REF_CLOCK_24MHz:
480 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
481 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
482 val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
483 rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
484 val, PHYREG15);
485
486 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
487 }
488 break;
489
490 case REF_CLOCK_25MHz:
491 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
492 break;
493
494 case REF_CLOCK_100MHz:
495 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
496 if (priv->type == PHY_TYPE_PCIE) {
497 /* PLL KVCO fine tuning. */
498 val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
499 rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
500 val, PHYREG33);
501
502 /* Enable controlling random jitter. */
503 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
504
505 val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
506 rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
507 val, PHYREG6);
508
509 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
510 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
511 } else if (priv->type == PHY_TYPE_SATA) {
512 /* downward spread spectrum +500ppm */
513 val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
514 val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
515 rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
516 }
517 break;
518
519 default:
520 dev_err(priv->dev, "unsupported rate: %lu\n", rate);
521 return -EINVAL;
522 }
523
524 if (priv->ext_refclk) {
525 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
526 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
527 val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
528 val |= PHYREG13_CKRCV_AMP0;
529 rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
530
531 val = readl(priv->mmio + PHYREG14);
532 val |= PHYREG14_CKRCV_AMP1;
533 writel(val, priv->mmio + PHYREG14);
534 }
535 }
536
537 if (priv->enable_ssc) {
538 val = readl(priv->mmio + PHYREG8);
539 val |= PHYREG8_SSC_EN;
540 writel(val, priv->mmio + PHYREG8);
541 }
542
543 return 0;
544 }
545
546 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
547 /* pipe-phy-grf */
548 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
549 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
550 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
551 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
552 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
553 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
554 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
555 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
556 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
557 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
558 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
559 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
560 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
561 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
562 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
563 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
564 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
565 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
566 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
567 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
568 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
569 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
570 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
571 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
572 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
573 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
574 /* pipe-grf */
575 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
576 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
577 };
578
579 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
580 .num_phys = 3,
581 .phy_ids = {
582 0xfe820000,
583 0xfe830000,
584 0xfe840000,
585 },
586 .grfcfg = &rk3568_combphy_grfcfgs,
587 .combphy_cfg = rk3568_combphy_cfg,
588 };
589
rk3588_combphy_cfg(struct rockchip_combphy_priv * priv)590 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
591 {
592 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
593 unsigned long rate;
594 u32 val;
595
596 switch (priv->type) {
597 case PHY_TYPE_PCIE:
598 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
599 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
600 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
601 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
602 switch (priv->id) {
603 case 1:
604 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
605 break;
606 case 2:
607 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
608 break;
609 }
610 break;
611 case PHY_TYPE_USB3:
612 /* Set SSC downward spread spectrum */
613 rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
614 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
615 PHYREG32);
616
617 /* Enable adaptive CTLE for USB3.0 Rx. */
618 val = readl(priv->mmio + PHYREG15);
619 val |= PHYREG15_CTLE_EN;
620 writel(val, priv->mmio + PHYREG15);
621
622 /* Set PLL KVCO fine tuning signals. */
623 rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
624 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
625 PHYREG33);
626
627 /* Enable controlling random jitter. */
628 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
629
630 /* Set PLL input clock divider 1/2. */
631 rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
632 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
633 PHYREG6);
634
635 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
636 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
637
638 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
639 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
640 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
641 break;
642 case PHY_TYPE_SATA:
643 /* Enable adaptive CTLE for SATA Rx. */
644 val = readl(priv->mmio + PHYREG15);
645 val |= PHYREG15_CTLE_EN;
646 writel(val, priv->mmio + PHYREG15);
647 /*
648 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
649 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
650 */
651 val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
652 val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
653 writel(val, priv->mmio + PHYREG7);
654
655 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
656 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
657 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
658 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
659 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
660 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
661 break;
662 case PHY_TYPE_SGMII:
663 case PHY_TYPE_QSGMII:
664 default:
665 dev_err(priv->dev, "incompatible PHY type\n");
666 return -EINVAL;
667 }
668
669 rate = clk_get_rate(priv->refclk);
670
671 switch (rate) {
672 case REF_CLOCK_24MHz:
673 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
674 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
675 val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
676 rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
677 val, PHYREG15);
678
679 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
680 }
681 break;
682
683 case REF_CLOCK_25MHz:
684 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
685 break;
686 case REF_CLOCK_100MHz:
687 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
688 if (priv->type == PHY_TYPE_PCIE) {
689 /* PLL KVCO fine tuning. */
690 val = 4 << PHYREG33_PLL_KVCO_SHIFT;
691 rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
692 val, PHYREG33);
693
694 /* Enable controlling random jitter. */
695 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
696
697 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
698 writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27);
699
700 /* Set up su_trim: */
701 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
702 } else if (priv->type == PHY_TYPE_SATA) {
703 /* downward spread spectrum +500ppm */
704 val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
705 val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
706 rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
707 }
708 break;
709 default:
710 dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
711 return -EINVAL;
712 }
713
714 if (priv->ext_refclk) {
715 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
716 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
717 val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
718 val |= PHYREG13_CKRCV_AMP0;
719 rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
720
721 val = readl(priv->mmio + PHYREG14);
722 val |= PHYREG14_CKRCV_AMP1;
723 writel(val, priv->mmio + PHYREG14);
724 }
725 }
726
727 if (priv->enable_ssc) {
728 val = readl(priv->mmio + PHYREG8);
729 val |= PHYREG8_SSC_EN;
730 writel(val, priv->mmio + PHYREG8);
731 }
732
733 return 0;
734 }
735
736 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
737 /* pipe-phy-grf */
738 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
739 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
740 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
741 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
742 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
743 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
744 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
745 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
746 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
747 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
748 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
749 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
750 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
751 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
752 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
753 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
754 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
755 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
756 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
757 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
758 /* pipe-grf */
759 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
760 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
761 .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 },
762 .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 },
763 };
764
765 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
766 .num_phys = 3,
767 .phy_ids = {
768 0xfee00000,
769 0xfee10000,
770 0xfee20000,
771 },
772 .grfcfg = &rk3588_combphy_grfcfgs,
773 .combphy_cfg = rk3588_combphy_cfg,
774 };
775
776 static const struct of_device_id rockchip_combphy_of_match[] = {
777 {
778 .compatible = "rockchip,rk3568-naneng-combphy",
779 .data = &rk3568_combphy_cfgs,
780 },
781 {
782 .compatible = "rockchip,rk3588-naneng-combphy",
783 .data = &rk3588_combphy_cfgs,
784 },
785 { },
786 };
787 MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
788
789 static struct platform_driver rockchip_combphy_driver = {
790 .probe = rockchip_combphy_probe,
791 .driver = {
792 .name = "rockchip-naneng-combphy",
793 .of_match_table = rockchip_combphy_of_match,
794 },
795 };
796 module_platform_driver(rockchip_combphy_driver);
797
798 MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
799 MODULE_LICENSE("GPL v2");
800