1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2016-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #ifndef QEMU_AVR_CPU_H 22 #define QEMU_AVR_CPU_H 23 24 #include "cpu-qom.h" 25 #include "exec/cpu-defs.h" 26 27 #ifdef CONFIG_USER_ONLY 28 #error "AVR 8-bit does not support user mode" 29 #endif 30 31 #define CPU_RESOLVING_TYPE TYPE_AVR_CPU 32 33 /* 34 * AVR has two memory spaces, data & code. 35 * e.g. both have 0 address 36 * ST/LD instructions access data space 37 * LPM/SPM and instruction fetching access code memory space 38 */ 39 #define MMU_CODE_IDX 0 40 #define MMU_DATA_IDX 1 41 42 #define EXCP_RESET 1 43 #define EXCP_INT(n) (EXCP_RESET + (n) + 1) 44 45 /* Number of CPU registers */ 46 #define NUMBER_OF_CPU_REGISTERS 32 47 /* Number of IO registers accessible by ld/st/in/out */ 48 #define NUMBER_OF_IO_REGISTERS 64 49 50 /* 51 * Offsets of AVR memory regions in host memory space. 52 * 53 * This is needed because the AVR has separate code and data address 54 * spaces that both have start from zero but have to go somewhere in 55 * host memory. 56 * 57 * It's also useful to know where some things are, like the IO registers. 58 */ 59 /* Flash program memory */ 60 #define OFFSET_CODE 0x00000000 61 /* CPU registers, IO registers, and SRAM */ 62 #define OFFSET_DATA 0x00800000 63 /* CPU registers specifically, these are mapped at the start of data */ 64 #define OFFSET_CPU_REGISTERS OFFSET_DATA 65 /* 66 * IO registers, including status register, stack pointer, and memory 67 * mapped peripherals, mapped just after CPU registers 68 */ 69 #define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS) 70 71 typedef enum AVRFeature { 72 AVR_FEATURE_SRAM, 73 74 AVR_FEATURE_1_BYTE_PC, 75 AVR_FEATURE_2_BYTE_PC, 76 AVR_FEATURE_3_BYTE_PC, 77 78 AVR_FEATURE_1_BYTE_SP, 79 AVR_FEATURE_2_BYTE_SP, 80 81 AVR_FEATURE_BREAK, 82 AVR_FEATURE_DES, 83 AVR_FEATURE_RMW, /* Read Modify Write - XCH LAC LAS LAT */ 84 85 AVR_FEATURE_EIJMP_EICALL, 86 AVR_FEATURE_IJMP_ICALL, 87 AVR_FEATURE_JMP_CALL, 88 89 AVR_FEATURE_ADIW_SBIW, 90 91 AVR_FEATURE_SPM, 92 AVR_FEATURE_SPMX, 93 94 AVR_FEATURE_ELPMX, 95 AVR_FEATURE_ELPM, 96 AVR_FEATURE_LPMX, 97 AVR_FEATURE_LPM, 98 99 AVR_FEATURE_MOVW, 100 AVR_FEATURE_MUL, 101 AVR_FEATURE_RAMPD, 102 AVR_FEATURE_RAMPX, 103 AVR_FEATURE_RAMPY, 104 AVR_FEATURE_RAMPZ, 105 } AVRFeature; 106 107 typedef struct CPUArchState { 108 uint32_t pc_w; /* 0x003fffff up to 22 bits */ 109 110 uint32_t sregC; /* 0x00000001 1 bit */ 111 uint32_t sregZ; /* 0x00000001 1 bit */ 112 uint32_t sregN; /* 0x00000001 1 bit */ 113 uint32_t sregV; /* 0x00000001 1 bit */ 114 uint32_t sregS; /* 0x00000001 1 bit */ 115 uint32_t sregH; /* 0x00000001 1 bit */ 116 uint32_t sregT; /* 0x00000001 1 bit */ 117 uint32_t sregI; /* 0x00000001 1 bit */ 118 119 uint32_t rampD; /* 0x00ff0000 8 bits */ 120 uint32_t rampX; /* 0x00ff0000 8 bits */ 121 uint32_t rampY; /* 0x00ff0000 8 bits */ 122 uint32_t rampZ; /* 0x00ff0000 8 bits */ 123 uint32_t eind; /* 0x00ff0000 8 bits */ 124 125 uint32_t r[NUMBER_OF_CPU_REGISTERS]; /* 8 bits each */ 126 uint32_t sp; /* 16 bits */ 127 128 uint32_t skip; /* if set skip instruction */ 129 130 uint64_t intsrc; /* interrupt sources */ 131 bool fullacc; /* CPU/MEM if true MEM only otherwise */ 132 133 uint64_t features; 134 } CPUAVRState; 135 136 /** 137 * AVRCPU: 138 * @env: #CPUAVRState 139 * 140 * A AVR CPU. 141 */ 142 struct ArchCPU { 143 CPUState parent_obj; 144 145 CPUAVRState env; 146 147 /* Initial value of stack pointer */ 148 uint32_t init_sp; 149 }; 150 151 /** 152 * AVRCPUClass: 153 * @parent_realize: The parent class' realize handler. 154 * @parent_phases: The parent class' reset phase handlers. 155 * 156 * A AVR CPU model. 157 */ 158 struct AVRCPUClass { 159 CPUClass parent_class; 160 161 DeviceRealize parent_realize; 162 ResettablePhases parent_phases; 163 }; 164 165 extern const struct VMStateDescription vms_avr_cpu; 166 167 void avr_cpu_do_interrupt(CPUState *cpu); 168 bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req); 169 hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 170 int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 171 int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 172 int avr_print_insn(bfd_vma addr, disassemble_info *info); 173 vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr); 174 avr_feature(CPUAVRState * env,AVRFeature feature)175 static inline int avr_feature(CPUAVRState *env, AVRFeature feature) 176 { 177 return (env->features & (1U << feature)) != 0; 178 } 179 set_avr_feature(CPUAVRState * env,int feature)180 static inline void set_avr_feature(CPUAVRState *env, int feature) 181 { 182 env->features |= (1U << feature); 183 } 184 185 void avr_cpu_tcg_init(void); 186 187 int cpu_avr_exec(CPUState *cpu); 188 189 enum { 190 TB_FLAGS_FULL_ACCESS = 1, 191 TB_FLAGS_SKIP = 2, 192 }; 193 cpu_get_tb_cpu_state(CPUAVRState * env,vaddr * pc,uint64_t * cs_base,uint32_t * pflags)194 static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, 195 uint64_t *cs_base, uint32_t *pflags) 196 { 197 uint32_t flags = 0; 198 199 *pc = env->pc_w * 2; 200 *cs_base = 0; 201 202 if (env->fullacc) { 203 flags |= TB_FLAGS_FULL_ACCESS; 204 } 205 if (env->skip) { 206 flags |= TB_FLAGS_SKIP; 207 } 208 209 *pflags = flags; 210 } 211 cpu_interrupts_enabled(CPUAVRState * env)212 static inline int cpu_interrupts_enabled(CPUAVRState *env) 213 { 214 return env->sregI != 0; 215 } 216 cpu_get_sreg(CPUAVRState * env)217 static inline uint8_t cpu_get_sreg(CPUAVRState *env) 218 { 219 return (env->sregC) << 0 220 | (env->sregZ) << 1 221 | (env->sregN) << 2 222 | (env->sregV) << 3 223 | (env->sregS) << 4 224 | (env->sregH) << 5 225 | (env->sregT) << 6 226 | (env->sregI) << 7; 227 } 228 cpu_set_sreg(CPUAVRState * env,uint8_t sreg)229 static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg) 230 { 231 env->sregC = (sreg >> 0) & 0x01; 232 env->sregZ = (sreg >> 1) & 0x01; 233 env->sregN = (sreg >> 2) & 0x01; 234 env->sregV = (sreg >> 3) & 0x01; 235 env->sregS = (sreg >> 4) & 0x01; 236 env->sregH = (sreg >> 5) & 0x01; 237 env->sregT = (sreg >> 6) & 0x01; 238 env->sregI = (sreg >> 7) & 0x01; 239 } 240 241 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 242 MMUAccessType access_type, int mmu_idx, 243 bool probe, uintptr_t retaddr); 244 245 #include "exec/cpu-all.h" 246 247 #endif /* QEMU_AVR_CPU_H */ 248