xref: /openbmc/u-boot/cmd/aspeed/nettest/mac.c (revision e12dfc2c7187d9ba6a722242cec57f059ebf37a8)
1  // SPDX-License-Identifier: GPL-2.0+
2  /*
3   * Copyright (C) ASPEED Technology Inc.
4   */
5  //#define MAC_DEBUG_REGRW_MAC
6  //#define MAC_DEBUG_REGRW_PHY
7  //#define MAC_DEBUG_REGRW_SCU
8  //#define MAC_DEBUG_REGRW_WDT
9  //#define MAC_DEBUG_REGRW_SDR
10  //#define MAC_DEBUG_REGRW_SMB
11  //#define MAC_DEBUG_REGRW_TIMER
12  //#define MAC_DEBUG_REGRW_GPIO
13  //#define MAC_DEBUG_MEMRW_Dat
14  //#define MAC_DEBUG_MEMRW_Des
15  
16  #define MAC_C
17  
18  #include "swfunc.h"
19  
20  #include "comminf.h"
21  #include <command.h>
22  #include <common.h>
23  #include <malloc.h>
24  #include "mem_io.h"
25  // -------------------------------------------------------------
26  const uint32_t ARP_org_data[16] = {
27      0xffffffff,
28      0x0000ffff, // SA:00-00-
29      0x12345678, // SA:78-56-34-12
30      0x01000608, // ARP(0x0806)
31      0x04060008,
32      0x00000100, // sender MAC Address: 00 00
33      0x12345678, // sender MAC Address: 12 34 56 78
34      0xeb00a8c0, // sender IP Address:  192.168.0.235 (C0.A8.0.EB)
35      0x00000000, // target MAC Address: 00 00 00 00
36      0xa8c00000, // target MAC Address: 00 00, target IP Address:192.168
37      0x00005c00, // target IP Address:  0.92 (C0.A8.0.5C)
38  		//	0x00000100, // target IP Address:  0.1 (C0.A8.0.1)
39  		//	0x0000de00, // target IP Address:  0.222 (C0.A8.0.DE)
40      0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc68e2bd5};
41  
42  //------------------------------------------------------------
43  // Read Memory
44  //------------------------------------------------------------
Read_Mem_Dat_NCSI_DD(uint32_t addr)45  uint32_t Read_Mem_Dat_NCSI_DD(uint32_t addr)
46  {
47  #ifdef MAC_DEBUG_MEMRW_Dat
48  	printf("[MEMRd-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( readl(addr) ) );
49  #endif
50  	return ( SWAP_4B_LEDN_MEM( readl(addr) ) );
51  }
52  
Read_Mem_Des_NCSI_DD(uint32_t addr)53  uint32_t Read_Mem_Des_NCSI_DD(uint32_t addr)
54  {
55  #ifdef MAC_DEBUG_MEMRW_Des
56  	printf("[MEMRd-Des] %08x = %08x\n", addr,
57  	       SWAP_4B_LEDN_MEM(readl(addr)));
58  #endif
59  	return (SWAP_4B_LEDN_MEM(readl(addr)));
60  }
61  
Read_Mem_Dat_DD(uint32_t addr)62  uint32_t Read_Mem_Dat_DD(uint32_t addr)
63  {
64  #ifdef MAC_DEBUG_MEMRW_Dat
65  	printf("[MEMRd-Dat] %08x = %08x\n", addr,
66  	       SWAP_4B_LEDN_MEM(readl(addr)));
67  #endif
68  	return (SWAP_4B_LEDN_MEM(readl(addr)));
69  }
70  
Read_Mem_Des_DD(uint32_t addr)71  uint32_t Read_Mem_Des_DD(uint32_t addr)
72  {
73  #ifdef MAC_DEBUG_MEMRW_Des
74  	printf("[MEMRd-Des] %08x = %08x\n", addr,
75  	       SWAP_4B_LEDN_MEM(readl(addr)));
76  #endif
77  	return (SWAP_4B_LEDN_MEM(readl(addr)));
78  }
79  
80  //------------------------------------------------------------
81  // Read Register
82  //------------------------------------------------------------
mac_reg_read(MAC_ENGINE * p_eng,uint32_t addr)83  uint32_t mac_reg_read(MAC_ENGINE *p_eng, uint32_t addr)
84  {
85  	return readl(p_eng->run.mac_base + addr);
86  }
87  
88  //------------------------------------------------------------
89  // Write Memory
90  //------------------------------------------------------------
Write_Mem_Dat_NCSI_DD(uint32_t addr,uint32_t data)91  void Write_Mem_Dat_NCSI_DD (uint32_t addr, uint32_t data) {
92  #ifdef MAC_DEBUG_MEMRW_Dat
93  	printf("[MEMWr-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) );
94  #endif
95  	writel(data, addr);
96  }
Write_Mem_Des_NCSI_DD(uint32_t addr,uint32_t data)97  void Write_Mem_Des_NCSI_DD (uint32_t addr, uint32_t data) {
98  #ifdef MAC_DEBUG_MEMRW_Des
99  	printf("[MEMWr-Des] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) );
100  #endif
101  	writel(data, addr);
102  }
Write_Mem_Dat_DD(uint32_t addr,uint32_t data)103  void Write_Mem_Dat_DD (uint32_t addr, uint32_t data) {
104  #ifdef MAC_DEBUG_MEMRW_Dat
105  	printf("[MEMWr-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) );
106  #endif
107  	writel(data, addr);
108  }
Write_Mem_Des_DD(uint32_t addr,uint32_t data)109  void Write_Mem_Des_DD (uint32_t addr, uint32_t data) {
110  #ifdef MAC_DEBUG_MEMRW_Des
111  	printf("[MEMWr-Des] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( data ) );
112  #endif
113  	writel(data, addr);
114  }
115  
116  //------------------------------------------------------------
117  // Write Register
118  //------------------------------------------------------------
mac_reg_write(MAC_ENGINE * p_eng,uint32_t addr,uint32_t data)119  void mac_reg_write(MAC_ENGINE *p_eng, uint32_t addr, uint32_t data)
120  {
121  	writel(data, p_eng->run.mac_base + addr);
122  }
123  
124  
125  //------------------------------------------------------------
126  // Others
127  //------------------------------------------------------------
debug_pause(void)128  void debug_pause (void) {
129  #ifdef DbgPrn_Enable_Debug_pause
130  	GET_CAHR();
131  #endif
132  }
133  
134  //------------------------------------------------------------
dump_mac_ROreg(MAC_ENGINE * p_eng)135  void dump_mac_ROreg(MAC_ENGINE *p_eng)
136  {
137  	int i = 0xa0;
138  
139  	printf("\nMAC%d base 0x%08x", p_eng->run.mac_idx, p_eng->run.mac_base);
140  	printf("\n%02x:", i);
141  	for (i = 0xa0; i <= 0xc8; i += 4) {
142  		printf("%08x ", mac_reg_read(p_eng, i));
143  		if ((i & 0xf) == 0xc)
144  			printf("\n%02x:", i + 4);
145  	}
146  	printf("\n");
147  }
148  
149  //------------------------------------------------------------
150  // IO delay
151  //------------------------------------------------------------
get_mac_1g_delay_1(uint32_t addr,int32_t * p_rx_d,int32_t * p_tx_d)152  static void get_mac_1g_delay_1(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d)
153  {
154  	int tx_d, rx_d;
155  	mac_delay_1g_t reg;
156  
157  	reg.w = readl(addr);
158  	tx_d = reg.b.tx_delay_1;
159  	rx_d = reg.b.rx_delay_1;
160  #ifdef CONFIG_ASPEED_AST2600
161  	if (reg.b.rx_clk_inv_1 == 1) {
162  		rx_d = (-1) * rx_d;
163  	}
164  #endif
165  	*p_tx_d = tx_d;
166  	*p_rx_d = rx_d;
167  	debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w,
168  	       rx_d, tx_d);
169  }
170  
get_mac_1g_delay_2(uint32_t addr,int32_t * p_rx_d,int32_t * p_tx_d)171  static void get_mac_1g_delay_2(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d)
172  {
173  	int tx_d, rx_d;
174  	mac_delay_1g_t reg;
175  
176  	reg.w = readl(addr);
177  	tx_d = reg.b.tx_delay_2;
178  	rx_d = reg.b.rx_delay_2;
179  #ifdef CONFIG_ASPEED_AST2600
180  	if (reg.b.rx_clk_inv_2 == 1) {
181  		rx_d = (-1) * rx_d;
182  	}
183  #endif
184  	*p_tx_d = tx_d;
185  	*p_rx_d = rx_d;
186  	debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w,
187  	       rx_d, tx_d);
188  }
189  
get_mac_100_10_delay_1(uint32_t addr,int32_t * p_rx_d,int32_t * p_tx_d)190  static void get_mac_100_10_delay_1(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d)
191  {
192  	int tx_d, rx_d;
193  	mac_delay_100_10_t reg;
194  
195  	reg.w = readl(addr);
196  	tx_d = reg.b.tx_delay_1;
197  	rx_d = reg.b.rx_delay_1;
198  #ifdef CONFIG_ASPEED_AST2600
199  	if (reg.b.rx_clk_inv_1 == 1) {
200  		rx_d = (-1) * rx_d;
201  	}
202  #endif
203  	*p_tx_d = tx_d;
204  	*p_rx_d = rx_d;
205  	debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w,
206  	       rx_d, tx_d);
207  }
208  
get_mac_100_10_delay_2(uint32_t addr,int32_t * p_rx_d,int32_t * p_tx_d)209  static void get_mac_100_10_delay_2(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d)
210  {
211  	int tx_d, rx_d;
212  	mac_delay_100_10_t reg;
213  
214  	reg.w = readl(addr);
215  	tx_d = reg.b.tx_delay_2;
216  	rx_d = reg.b.rx_delay_2;
217  #ifdef CONFIG_ASPEED_AST2600
218  	if (reg.b.rx_clk_inv_2 == 1) {
219  		rx_d = (-1) * rx_d;
220  	}
221  #endif
222  	*p_tx_d = tx_d;
223  	*p_rx_d = rx_d;
224  	debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w,
225  	       rx_d, tx_d);
226  }
227  
get_mac_rmii_delay_1(uint32_t addr,int32_t * p_rx_d,int32_t * p_tx_d)228  static void get_mac_rmii_delay_1(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d)
229  {
230  	mac_delay_1g_t reg;
231  
232  	reg.w = readl(addr);
233  	*p_rx_d = reg.b.rx_delay_1;
234  	*p_tx_d = reg.b.rmii_tx_data_at_falling_1;
235  
236  	debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w,
237  	       *p_rx_d, *p_tx_d);
238  }
get_mac_rmii_delay_2(uint32_t addr,int32_t * p_rx_d,int32_t * p_tx_d)239  static void get_mac_rmii_delay_2(uint32_t addr, int32_t *p_rx_d, int32_t *p_tx_d)
240  {
241  	mac_delay_1g_t reg;
242  
243  	reg.w = readl(addr);
244  	*p_rx_d = reg.b.rx_delay_2;
245  	*p_tx_d = reg.b.rmii_tx_data_at_falling_2;
246  
247  	debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w,
248  	       *p_rx_d, *p_tx_d);
249  }
250  
251  static
get_mac1_1g_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)252  void get_mac1_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
253  {
254  	get_mac_1g_delay_1(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d);
255  }
256  static
get_mac1_100m_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)257  void get_mac1_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
258  {
259  	get_mac_100_10_delay_1(p_eng->io.mac12_100m_delay.addr, p_rx_d, p_tx_d);
260  }
261  static
get_mac1_10m_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)262  void get_mac1_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
263  {
264  	get_mac_100_10_delay_1(p_eng->io.mac12_10m_delay.addr, p_rx_d, p_tx_d);
265  }
266  static
get_mac2_1g_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)267  void get_mac2_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
268  {
269  	get_mac_1g_delay_2(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d);
270  }
271  static
get_mac2_100m_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)272  void get_mac2_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
273  {
274  	get_mac_100_10_delay_2(p_eng->io.mac12_100m_delay.addr, p_rx_d, p_tx_d);
275  }
276  static
get_mac2_10m_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)277  void get_mac2_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
278  {
279  	get_mac_100_10_delay_2(p_eng->io.mac12_10m_delay.addr, p_rx_d, p_tx_d);
280  }
281  static
get_mac3_1g_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)282  void get_mac3_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
283  {
284  	get_mac_1g_delay_1(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d);
285  }
286  static
get_mac3_100m_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)287  void get_mac3_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
288  {
289  	get_mac_100_10_delay_1(p_eng->io.mac34_100m_delay.addr, p_rx_d, p_tx_d);
290  }
291  static
get_mac3_10m_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)292  void get_mac3_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
293  {
294  	get_mac_100_10_delay_1(p_eng->io.mac34_10m_delay.addr, p_rx_d, p_tx_d);
295  }
296  static
get_mac4_1g_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)297  void get_mac4_1g_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
298  {
299  	get_mac_1g_delay_2(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d);
300  }
301  static
get_mac4_100m_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)302  void get_mac4_100m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
303  {
304  	get_mac_100_10_delay_2(p_eng->io.mac34_100m_delay.addr, p_rx_d, p_tx_d);
305  }
306  static
get_mac4_10m_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)307  void get_mac4_10m_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
308  {
309  	get_mac_100_10_delay_2(p_eng->io.mac34_10m_delay.addr, p_rx_d, p_tx_d);
310  }
311  static
get_mac1_rmii_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)312  void get_mac1_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
313  {
314  	get_mac_rmii_delay_1(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d);
315  }
316  static
get_mac2_rmii_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)317  void get_mac2_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
318  {
319  	get_mac_rmii_delay_2(p_eng->io.mac12_1g_delay.addr, p_rx_d, p_tx_d);
320  }
321  static
get_mac3_rmii_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)322  void get_mac3_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
323  {
324  	get_mac_rmii_delay_1(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d);
325  }
326  static
get_mac4_rmii_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)327  void get_mac4_rmii_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
328  {
329  	get_mac_rmii_delay_2(p_eng->io.mac34_1g_delay.addr, p_rx_d, p_tx_d);
330  }
331  #if !defined(CONFIG_ASPEED_AST2600)
332  static
get_dummy_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)333  void get_dummy_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
334  {
335  	debug("%s\n", __func__);
336  }
337  #endif
338  
339  /**
340   * @brief function pointer table to get current delay setting
341   *
342   * get_delay_func_tbl[rmii/rgmii][mac_idx][speed_idx 1g/100m/10m]
343  */
344  typedef void (*pfn_get_delay) (MAC_ENGINE *, int32_t *, int32_t *);
345  pfn_get_delay get_delay_func_tbl[2][4][3] = {
346  	{
347  		{get_mac1_rmii_delay, get_mac1_rmii_delay, get_mac1_rmii_delay},
348  		{get_mac2_rmii_delay, get_mac2_rmii_delay, get_mac2_rmii_delay},
349  #if defined(CONFIG_ASPEED_AST2600)
350  		{get_mac3_rmii_delay, get_mac3_rmii_delay, get_mac3_rmii_delay},
351  		{get_mac4_rmii_delay, get_mac4_rmii_delay, get_mac4_rmii_delay},
352  #else
353  		{get_dummy_delay, get_dummy_delay, get_dummy_delay},
354  		{get_dummy_delay, get_dummy_delay, get_dummy_delay},
355  #endif
356  	},
357  	{
358  		{get_mac1_1g_delay, get_mac1_100m_delay, get_mac1_10m_delay},
359  		{get_mac2_1g_delay, get_mac2_100m_delay, get_mac2_10m_delay},
360  #if defined(CONFIG_ASPEED_AST2600)
361  		{get_mac3_1g_delay, get_mac3_100m_delay, get_mac3_10m_delay},
362  		{get_mac4_1g_delay, get_mac4_100m_delay, get_mac4_10m_delay},
363  #else
364  		{get_dummy_delay, get_dummy_delay, get_dummy_delay},
365  		{get_dummy_delay, get_dummy_delay, get_dummy_delay},
366  #endif
367  	}
368  };
mac_get_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)369  void mac_get_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
370  {
371  #if 1
372  	uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii;
373  	uint32_t mac_idx = p_eng->run.mac_idx;
374  	uint32_t speed_idx = p_eng->run.speed_idx;
375  
376  	get_delay_func_tbl[rgmii][mac_idx][speed_idx] (p_eng, p_rx_d, p_tx_d);
377  #else
378  	/* for test */
379  	uint32_t rgmii;
380  	uint32_t mac_idx;
381  	uint32_t speed_idx;
382  	for (rgmii = 0; rgmii < 2; rgmii++)
383  		for (mac_idx = 0; mac_idx < 4; mac_idx++)
384  			for (speed_idx = 0; speed_idx < 3; speed_idx++)
385  				get_delay_func_tbl[rgmii][mac_idx][speed_idx](
386  				    p_eng, p_rx_d, p_tx_d);
387  #endif
388  }
389  
mac_get_max_available_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)390  void mac_get_max_available_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
391  {
392  	uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii;
393  	uint32_t mac_idx = p_eng->run.mac_idx;
394  	int32_t tx_max, rx_max;
395  
396  	if (rgmii) {
397  		if (mac_idx > 1) {
398  			tx_max = p_eng->io.mac34_1g_delay.tx_max;
399  			rx_max = p_eng->io.mac34_1g_delay.rx_max;
400  		} else {
401  			tx_max = p_eng->io.mac12_1g_delay.tx_max;
402  			rx_max = p_eng->io.mac12_1g_delay.rx_max;
403  		}
404  	} else {
405  		if (mac_idx > 1) {
406  			tx_max = p_eng->io.mac34_1g_delay.rmii_tx_max;
407  			rx_max = p_eng->io.mac34_1g_delay.rmii_rx_max;
408  		} else {
409  			tx_max = p_eng->io.mac12_1g_delay.rmii_tx_max;
410  			rx_max = p_eng->io.mac12_1g_delay.rmii_rx_max;
411  		}
412  	}
413  	*p_tx_d = tx_max;
414  	*p_rx_d = rx_max;
415  }
416  
mac_get_min_available_delay(MAC_ENGINE * p_eng,int32_t * p_rx_d,int32_t * p_tx_d)417  void mac_get_min_available_delay(MAC_ENGINE *p_eng, int32_t *p_rx_d, int32_t *p_tx_d)
418  {
419  	uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii;
420  	uint32_t mac_idx = p_eng->run.mac_idx;
421  	int32_t tx_min, rx_min;
422  
423  	if (rgmii) {
424  		if (mac_idx > 1) {
425  			tx_min = p_eng->io.mac34_1g_delay.tx_min;
426  			rx_min = p_eng->io.mac34_1g_delay.rx_min;
427  		} else {
428  			tx_min = p_eng->io.mac12_1g_delay.tx_min;
429  			rx_min = p_eng->io.mac12_1g_delay.rx_min;
430  		}
431  	} else {
432  		if (mac_idx > 1) {
433  			tx_min = p_eng->io.mac34_1g_delay.rmii_tx_min;
434  			rx_min = p_eng->io.mac34_1g_delay.rmii_rx_min;
435  		} else {
436  			tx_min = p_eng->io.mac12_1g_delay.rmii_tx_min;
437  			rx_min = p_eng->io.mac12_1g_delay.rmii_rx_min;
438  		}
439  	}
440  	*p_tx_d = tx_min;
441  	*p_rx_d = rx_min;
442  }
443  
set_mac_1g_delay_1(uint32_t addr,int32_t rx_d,int32_t tx_d)444  static void set_mac_1g_delay_1(uint32_t addr, int32_t rx_d, int32_t tx_d)
445  {
446  	mac_delay_1g_t reg;
447  
448  	reg.w = readl(addr);
449  #ifdef CONFIG_ASPEED_AST2600
450  	if (rx_d < 0) {
451  		reg.b.rx_clk_inv_1 = 1;
452  		rx_d = abs(rx_d);
453  	}
454  #endif
455  	reg.b.rx_delay_1 = rx_d;
456  	reg.b.tx_delay_1 = tx_d;
457  	writel(reg.w, addr);
458  
459  	debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w,
460  	       rx_d, tx_d);
461  }
462  
set_mac_1g_delay_2(uint32_t addr,int32_t rx_d,int32_t tx_d)463  static void set_mac_1g_delay_2(uint32_t addr, int32_t rx_d, int32_t tx_d)
464  {
465  	mac_delay_1g_t reg;
466  
467  	reg.w = readl(addr);
468  #ifdef CONFIG_ASPEED_AST2600
469  	if (rx_d < 0) {
470  		reg.b.rx_clk_inv_2 = 1;
471  		rx_d = abs(rx_d);
472  	}
473  #endif
474  	reg.b.rx_delay_2 = rx_d;
475  	reg.b.tx_delay_2 = tx_d;
476  	writel(reg.w, addr);
477  
478  	debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w,
479  	       rx_d, tx_d);
480  }
481  
set_mac_100_10_delay_1(uint32_t addr,int32_t rx_d,int32_t tx_d)482  static void set_mac_100_10_delay_1(uint32_t addr, int32_t rx_d, int32_t tx_d)
483  {
484  	mac_delay_100_10_t reg;
485  
486  	reg.w = readl(addr);
487  #ifdef CONFIG_ASPEED_AST2600
488  	if (rx_d < 0) {
489  		reg.b.rx_clk_inv_1 = 1;
490  		rx_d = abs(rx_d);
491  	}
492  #endif
493  	reg.b.rx_delay_1 = rx_d;
494  	reg.b.tx_delay_1 = tx_d;
495  	writel(reg.w, addr);
496  
497  	debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w,
498  	       rx_d, tx_d);
499  }
500  
set_mac_100_10_delay_2(uint32_t addr,int32_t rx_d,int32_t tx_d)501  static void set_mac_100_10_delay_2(uint32_t addr, int32_t rx_d, int32_t tx_d)
502  {
503  	mac_delay_100_10_t reg;
504  
505  	reg.w = readl(addr);
506  #ifdef CONFIG_ASPEED_AST2600
507  	if (rx_d < 0) {
508  		reg.b.rx_clk_inv_2 = 1;
509  		rx_d = abs(rx_d);
510  	}
511  #endif
512  	reg.b.rx_delay_2 = rx_d;
513  	reg.b.tx_delay_2 = tx_d;
514  	writel(reg.w, addr);
515  
516  	debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w,
517  	       rx_d, tx_d);
518  }
519  
set_mac_rmii_delay_1(uint32_t addr,int32_t rx_d,int32_t tx_d)520  static void set_mac_rmii_delay_1(uint32_t addr, int32_t rx_d, int32_t tx_d)
521  {
522  	mac_delay_1g_t reg;
523  
524  	reg.w = readl(addr);
525  	reg.b.rmii_tx_data_at_falling_1 = tx_d;
526  	reg.b.rx_delay_1 = rx_d;
527  	writel(reg.w, addr);
528  
529  	debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w,
530  	       rx_d, tx_d);
531  }
532  
set_mac_rmii_delay_2(uint32_t addr,int32_t rx_d,int32_t tx_d)533  static void set_mac_rmii_delay_2(uint32_t addr, int32_t rx_d, int32_t tx_d)
534  {
535  	mac_delay_1g_t reg;
536  
537  	reg.w = readl(addr);
538  	reg.b.rmii_tx_data_at_falling_2 = tx_d;
539  	reg.b.rx_delay_2 = rx_d;
540  	writel(reg.w, addr);
541  
542  	debug("%s:[%08x] %08x, rx_d=%d, tx_d=%d\n", __func__, addr, reg.w,
543  	       rx_d, tx_d);
544  }
545  
546  
set_mac1_1g_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)547  static void set_mac1_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
548  {
549  	set_mac_1g_delay_1(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d);
550  }
set_mac1_100m_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)551  static void set_mac1_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
552  {
553  	set_mac_100_10_delay_1(p_eng->io.mac12_100m_delay.addr, rx_d, tx_d);
554  }
set_mac1_10m_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)555  static void set_mac1_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
556  {
557  	set_mac_100_10_delay_1(p_eng->io.mac12_10m_delay.addr, rx_d, tx_d);
558  }
set_mac2_1g_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)559  static void set_mac2_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
560  {
561  	set_mac_1g_delay_2(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d);
562  }
set_mac2_100m_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)563  static void set_mac2_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
564  {
565  	set_mac_100_10_delay_2(p_eng->io.mac12_100m_delay.addr, rx_d, tx_d);
566  }
set_mac2_10m_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)567  static void set_mac2_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
568  {
569  	set_mac_100_10_delay_2(p_eng->io.mac12_10m_delay.addr, rx_d, tx_d);
570  }
set_mac3_1g_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)571  static void set_mac3_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
572  {
573  	set_mac_1g_delay_1(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d);
574  }
set_mac3_100m_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)575  static void set_mac3_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
576  {
577  	set_mac_100_10_delay_1(p_eng->io.mac34_100m_delay.addr, rx_d, tx_d);
578  }
set_mac3_10m_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)579  static void set_mac3_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
580  {
581  	set_mac_100_10_delay_1(p_eng->io.mac34_10m_delay.addr, rx_d, tx_d);
582  }
set_mac4_1g_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)583  static void set_mac4_1g_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
584  {
585  	set_mac_1g_delay_2(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d);
586  }
set_mac4_100m_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)587  static void set_mac4_100m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
588  {
589  	set_mac_100_10_delay_2(p_eng->io.mac34_100m_delay.addr, rx_d, tx_d);
590  }
set_mac4_10m_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)591  static void set_mac4_10m_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
592  {
593  	set_mac_100_10_delay_2(p_eng->io.mac34_10m_delay.addr, rx_d, tx_d);
594  }
set_mac1_rmii_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)595  static void set_mac1_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
596  {
597  	set_mac_rmii_delay_1(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d);
598  }
set_mac2_rmii_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)599  static void set_mac2_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
600  {
601  	set_mac_rmii_delay_2(p_eng->io.mac12_1g_delay.addr, rx_d, tx_d);
602  }
603  
set_mac3_rmii_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)604  static void set_mac3_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
605  {
606  	set_mac_rmii_delay_1(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d);
607  }
608  
set_mac4_rmii_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)609  static void set_mac4_rmii_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
610  {
611  	set_mac_rmii_delay_2(p_eng->io.mac34_1g_delay.addr, rx_d, tx_d);
612  }
613  
set_dummy_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)614  void set_dummy_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
615  {
616  	printf("%s: %d, %d\n", __func__, rx_d, tx_d);
617  }
618  
619  /**
620   * @brief function pointer table for delay setting
621   *
622   * set_delay_func_tbl[rmii/rgmii][mac_idx][speed_idx 1g/100m/10m]
623  */
624  typedef void (*pfn_set_delay) (MAC_ENGINE *, int32_t, int32_t);
625  pfn_set_delay set_delay_func_tbl[2][4][3] = {
626  	{
627  		{set_mac1_rmii_delay, set_mac1_rmii_delay, set_mac1_rmii_delay},
628  		{set_mac2_rmii_delay, set_mac2_rmii_delay, set_mac2_rmii_delay},
629  #if defined(CONFIG_ASPEED_AST2600)
630  		{set_mac3_rmii_delay, set_mac3_rmii_delay, set_mac3_rmii_delay},
631  		{set_mac4_rmii_delay, set_mac4_rmii_delay, set_mac4_rmii_delay},
632  #else
633  		{set_dummy_delay, set_dummy_delay, set_dummy_delay},
634  		{set_dummy_delay, set_dummy_delay, set_dummy_delay},
635  #endif
636  	},
637  	{
638  		{set_mac1_1g_delay, set_mac1_100m_delay, set_mac1_10m_delay},
639  		{set_mac2_1g_delay, set_mac2_100m_delay, set_mac2_10m_delay},
640  #if defined(CONFIG_ASPEED_AST2600)
641  		{set_mac3_1g_delay, set_mac3_100m_delay, set_mac3_10m_delay},
642  		{set_mac4_1g_delay, set_mac4_100m_delay, set_mac4_10m_delay},
643  #else
644  		{set_dummy_delay, set_dummy_delay, set_dummy_delay},
645  		{set_dummy_delay, set_dummy_delay, set_dummy_delay},
646  #endif
647  	}
648  };
649  
mac_set_delay(MAC_ENGINE * p_eng,int32_t rx_d,int32_t tx_d)650  void mac_set_delay(MAC_ENGINE *p_eng, int32_t rx_d, int32_t tx_d)
651  {
652  	uint32_t rgmii = (uint32_t)p_eng->run.is_rgmii;
653  	uint32_t mac_idx = p_eng->run.mac_idx;
654  	u32 speed_idx = p_eng->run.speed_idx;
655  
656  	set_delay_func_tbl[rgmii][mac_idx][speed_idx] (p_eng, rx_d, tx_d);
657  }
658  
mac_get_driving_strength(MAC_ENGINE * p_eng)659  uint32_t mac_get_driving_strength(MAC_ENGINE *p_eng)
660  {
661  #ifdef CONFIG_ASPEED_AST2600
662  	mac34_drv_t reg;
663  
664  	reg.w = readl(p_eng->io.mac34_drv_reg.addr);
665  	/* ast2600 : only MAC#3 & MAC#4 have driving strength setting */
666  	if (p_eng->run.mac_idx == 2) {
667  		return (reg.b.mac3_tx_drv);
668  	} else if (p_eng->run.mac_idx == 3) {
669  		return (reg.b.mac4_tx_drv);
670  	} else {
671  		return 0;
672  	}
673  #else
674  	mac12_drv_t reg;
675  
676  	reg.w = readl(p_eng->io.mac12_drv_reg.addr);
677  
678  	if (p_eng->run.mac_idx == 0) {
679  		return reg.b.mac1_rgmii_tx_drv;
680  	} else if (p_eng->run.mac_idx == 1) {
681  		return reg.b.mac2_rgmii_tx_drv;
682  	} else {
683  		return 0;
684  	}
685  #endif
686  }
mac_set_driving_strength(MAC_ENGINE * p_eng,uint32_t strength)687  void mac_set_driving_strength(MAC_ENGINE *p_eng, uint32_t strength)
688  {
689  #ifdef CONFIG_ASPEED_AST2600
690  	mac34_drv_t reg;
691  
692  	if (strength > p_eng->io.mac34_drv_reg.drv_max) {
693  		printf("invalid driving strength value\n");
694  		return;
695  	}
696  
697  	/**
698  	 * read->modify->write for driving strength control register
699  	 * ast2600 : only MAC#3 & MAC#4 have driving strength setting
700  	 */
701  	reg.w = readl(p_eng->io.mac34_drv_reg.addr);
702  
703  	/* ast2600 : only MAC#3 & MAC#4 have driving strength setting */
704  	if (p_eng->run.mac_idx == 2) {
705  		reg.b.mac3_tx_drv = strength;
706  	} else if (p_eng->run.mac_idx == 3) {
707  		reg.b.mac4_tx_drv = strength;
708  	}
709  
710  	writel(reg.w, p_eng->io.mac34_drv_reg.addr);
711  #else
712  	mac12_drv_t reg;
713  
714  	if (strength > p_eng->io.mac12_drv_reg.drv_max) {
715  		printf("invalid driving strength value\n");
716  		return;
717  	}
718  
719  	/* read->modify->write for driving strength control register */
720  	reg.w = readl(p_eng->io.mac12_drv_reg.addr);
721  	if (p_eng->run.is_rgmii) {
722  		if (p_eng->run.mac_idx == 0) {
723  			reg.b.mac1_rgmii_tx_drv =
724  			    strength;
725  		} else if (p_eng->run.mac_idx == 2) {
726  			reg.b.mac2_rgmii_tx_drv =
727  			    strength;
728  		}
729  	} else {
730  		if (p_eng->run.mac_idx == 0) {
731  			reg.b.mac1_rmii_tx_drv =
732  			    strength;
733  		} else if (p_eng->run.mac_idx == 1) {
734  			reg.b.mac2_rmii_tx_drv =
735  			    strength;
736  		}
737  	}
738  	writel(reg.w, p_eng->io.mac12_drv_reg.addr);
739  #endif
740  }
741  
mac_set_rmii_50m_output_enable(MAC_ENGINE * p_eng)742  void mac_set_rmii_50m_output_enable(MAC_ENGINE *p_eng)
743  {
744  	uint32_t addr;
745  	mac_delay_1g_t value;
746  
747  	if (p_eng->run.mac_idx > 1) {
748  		addr = p_eng->io.mac34_1g_delay.addr;
749  	} else {
750  		addr = p_eng->io.mac12_1g_delay.addr;
751  	}
752  
753  	value.w = readl(addr);
754  	if (p_eng->run.mac_idx & BIT(0)) {
755  		value.b.rmii_50m_oe_2 = 1;
756  	} else {
757  		value.b.rmii_50m_oe_1 = 1;
758  	}
759  	writel(value.w, addr);
760  }
761  
762  //------------------------------------------------------------
mac_set_scan_boundary(MAC_ENGINE * p_eng)763  int mac_set_scan_boundary(MAC_ENGINE *p_eng)
764  {
765  	int32_t rx_cur, tx_cur;
766  	int32_t rx_min, rx_max, tx_min, tx_max;
767  	int32_t rx_scaling, tx_scaling;
768  
769  	nt_log_func_name();
770  
771  	/* get current delay setting */
772  	mac_get_delay(p_eng, &rx_cur, &tx_cur);
773  
774  	/* get physical boundaries */
775  	mac_get_max_available_delay(p_eng, &rx_max, &tx_max);
776  	mac_get_min_available_delay(p_eng, &rx_min, &tx_min);
777  
778  	if ((p_eng->run.is_rgmii) && (p_eng->arg.ctrl.b.inv_rgmii_rxclk)) {
779  		rx_max = (rx_max > 0) ? 0 : rx_max;
780  	} else {
781  		rx_min = (rx_min < 0) ? 0 : rx_min;
782  	}
783  
784  	if (p_eng->run.TM_IOTiming) {
785  		if (p_eng->arg.ctrl.b.full_range) {
786  			tx_scaling = 0;
787  			rx_scaling = 0;
788  		} else {
789  			/* down-scaling to save test time */
790  			tx_scaling = TX_DELAY_SCALING;
791  			rx_scaling = RX_DELAY_SCALING;
792  		}
793  		p_eng->io.rx_delay_scan.step = 1;
794  		p_eng->io.tx_delay_scan.step = 1;
795  		p_eng->io.rx_delay_scan.begin = rx_min >> rx_scaling;
796  		p_eng->io.rx_delay_scan.end = rx_max >> rx_scaling;
797  		p_eng->io.tx_delay_scan.begin = tx_min >> tx_scaling;
798  		p_eng->io.tx_delay_scan.end = tx_max >> tx_scaling;
799  	} else if (p_eng->run.delay_margin) {
800  		p_eng->io.rx_delay_scan.step = 1;
801  		p_eng->io.tx_delay_scan.step = 1;
802  		p_eng->io.rx_delay_scan.begin = rx_cur - p_eng->run.delay_margin;
803  		p_eng->io.rx_delay_scan.end = rx_cur + p_eng->run.delay_margin;
804  		p_eng->io.tx_delay_scan.begin = tx_cur - p_eng->run.delay_margin;
805  		p_eng->io.tx_delay_scan.end = tx_cur + p_eng->run.delay_margin;
806  	} else {
807  		p_eng->io.rx_delay_scan.step = 1;
808  		p_eng->io.tx_delay_scan.step = 1;
809  		p_eng->io.rx_delay_scan.begin = 0;
810  		p_eng->io.rx_delay_scan.end = 0;
811  		p_eng->io.tx_delay_scan.begin = 0;
812  		p_eng->io.tx_delay_scan.end = 0;
813  	}
814  
815  	/* backup current setting as the original for plotting result */
816  	p_eng->io.rx_delay_scan.orig = rx_cur;
817  	p_eng->io.tx_delay_scan.orig = tx_cur;
818  
819  	/* check if setting is legal or not */
820  	if (p_eng->io.rx_delay_scan.begin < rx_min)
821  		p_eng->io.rx_delay_scan.begin = rx_min;
822  
823  	if (p_eng->io.tx_delay_scan.begin < tx_min)
824  		p_eng->io.tx_delay_scan.begin = tx_min;
825  
826  	if (p_eng->io.rx_delay_scan.end > rx_max)
827  		p_eng->io.rx_delay_scan.end = rx_max;
828  
829  	if (p_eng->io.tx_delay_scan.end > tx_max)
830  		p_eng->io.tx_delay_scan.end = tx_max;
831  
832  	if (p_eng->io.rx_delay_scan.begin > p_eng->io.rx_delay_scan.end)
833  		p_eng->io.rx_delay_scan.begin = p_eng->io.rx_delay_scan.end;
834  
835  	if (p_eng->io.tx_delay_scan.begin > p_eng->io.tx_delay_scan.end)
836  		p_eng->io.tx_delay_scan.begin = p_eng->io.tx_delay_scan.end;
837  
838  	if (p_eng->run.IO_MrgChk) {
839  		if ((p_eng->io.rx_delay_scan.orig <
840  		     p_eng->io.rx_delay_scan.begin) ||
841  		    (p_eng->io.rx_delay_scan.orig >
842  		     p_eng->io.rx_delay_scan.end)) {
843  			printf("Warning: current delay is not in the "
844  			       "scan-range\n");
845  			printf("RX delay scan range:%d ~ %d, curr:%d\n",
846  			       p_eng->io.rx_delay_scan.begin,
847  			       p_eng->io.rx_delay_scan.end,
848  			       p_eng->io.rx_delay_scan.orig);
849  			printf("TX delay scan range:%d ~ %d, curr:%d\n",
850  			       p_eng->io.tx_delay_scan.begin,
851  			       p_eng->io.tx_delay_scan.end,
852  			       p_eng->io.tx_delay_scan.orig);
853  		}
854  	}
855  
856  	return (0);
857  }
858  
859  //------------------------------------------------------------
860  // MAC
861  //------------------------------------------------------------
mac_set_addr(MAC_ENGINE * p_eng)862  void mac_set_addr(MAC_ENGINE *p_eng)
863  {
864  	nt_log_func_name();
865  
866  	uint32_t madr = p_eng->reg.mac_madr;
867  	uint32_t ladr = p_eng->reg.mac_ladr;
868  
869  	if (((madr == 0x0000) && (ladr == 0x00000000)) ||
870  	    ((madr == 0xffff) && (ladr == 0xffffffff))) {
871  		/* FIXME: shall use random gen */
872  		madr = 0x0000000a;
873  		ladr = 0xf7837dd4;
874  	}
875  
876  	p_eng->inf.SA[0] = (madr >> 8) & 0xff; // MSB
877  	p_eng->inf.SA[1] = (madr >> 0) & 0xff;
878  	p_eng->inf.SA[2] = (ladr >> 24) & 0xff;
879  	p_eng->inf.SA[3] = (ladr >> 16) & 0xff;
880  	p_eng->inf.SA[4] = (ladr >> 8) & 0xff;
881  	p_eng->inf.SA[5] = (ladr >> 0) & 0xff; // LSB
882  
883  	printf("mac address: ");
884  	for (int i = 0; i < 6; i++) {
885  		printf("%02x:", p_eng->inf.SA[i]);
886  	}
887  	printf("\n");
888  }
889  
mac_set_interal_loopback(MAC_ENGINE * p_eng)890  void mac_set_interal_loopback(MAC_ENGINE *p_eng)
891  {
892  	uint32_t reg = mac_reg_read(p_eng, 0x40);
893  	mac_reg_write(p_eng, 0x40, reg | BIT(30));
894  }
895  
896  //------------------------------------------------------------
init_mac(MAC_ENGINE * eng)897  void init_mac (MAC_ENGINE *eng)
898  {
899  	nt_log_func_name();
900  
901  	mac_cr_t maccr;
902  
903  #ifdef Enable_MAC_SWRst
904  	maccr.w = 0;
905  	maccr.b.sw_rst = 1;
906  	mac_reg_write(eng, 0x50, maccr.w);
907  
908  	do {
909  		DELAY(Delay_MACRst);
910  		maccr.w = mac_reg_read(eng, 0x50);
911  	} while(maccr.b.sw_rst);
912  #endif
913  
914  	mac_reg_write(eng, 0x20, eng->run.tdes_base - ASPEED_DRAM_BASE);
915  	mac_reg_write(eng, 0x24, eng->run.rdes_base - ASPEED_DRAM_BASE);
916  
917  	mac_reg_write(eng, 0x08, eng->reg.mac_madr);
918  	mac_reg_write(eng, 0x0c, eng->reg.mac_ladr);
919  
920  #ifdef MAC_030_def
921  	mac_reg_write( eng, 0x30, MAC_030_def );//Int Thr/Cnt
922  #endif
923  #ifdef MAC_034_def
924  	mac_reg_write( eng, 0x34, MAC_034_def );//Poll Cnt
925  #endif
926  #ifdef MAC_038_def
927  	mac_reg_write( eng, 0x38, MAC_038_def );
928  #endif
929  #ifdef MAC_048_def
930  	mac_reg_write( eng, 0x48, MAC_048_def );
931  #endif
932  #ifdef MAC_058_def
933  	mac_reg_write( eng, 0x58, MAC_058_def );
934  #endif
935  
936  	if ( eng->arg.run_mode == MODE_NCSI )
937  		mac_reg_write( eng, 0x4c, NCSI_RxDMA_PakSize );
938  	else
939  		mac_reg_write( eng, 0x4c, DMA_PakSize );
940  
941  	maccr.b.txdma_en = 1;
942  	maccr.b.rxdma_en = 1;
943  	maccr.b.txmac_en = 1;
944  	maccr.b.rxmac_en = 1;
945  	maccr.b.fulldup = 1;
946  	maccr.b.crc_apd = 1;
947  
948  	if (eng->run.speed_sel[0]) {
949  		maccr.b.gmac_mode = 1;
950  	} else if (eng->run.speed_sel[1]) {
951  		maccr.b.speed_100 = 1;
952  	}
953  
954  	if (eng->arg.run_mode == MODE_NCSI) {
955  		maccr.b.rx_broadpkt_en = 1;
956  		maccr.b.speed_100 = 1;
957  	}
958  	else {
959  		maccr.b.rx_alladr = 1;
960  #ifdef Enable_Runt
961  		maccr.b.rx_runt = 1;
962  #endif
963  	}
964  	mac_reg_write(eng, 0x50, maccr.w);
965  	DELAY(Delay_MACRst);
966  } // End void init_mac (MAC_ENGINE *eng)
967  
968  //------------------------------------------------------------
969  // Basic
970  //------------------------------------------------------------
FPri_RegValue(MAC_ENGINE * eng,uint8_t option)971  void FPri_RegValue (MAC_ENGINE *eng, uint8_t option)
972  {
973  	nt_log_func_name();
974  
975  	PRINTF( option, "[SRAM] Date:%08x\n", SRAM_RD( 0x88 ) );
976  	PRINTF( option, "[SRAM]  80:%08x %08x %08x %08x\n", SRAM_RD( 0x80 ), SRAM_RD( 0x84 ), SRAM_RD( 0x88 ), SRAM_RD( 0x8c ) );
977  
978  	PRINTF( option, "[SCU]  a0:%08x  a4:%08x  b8:%08x  bc:%08x\n", SCU_RD( 0x0a0 ), SCU_RD( 0x0a4 ), SCU_RD( 0x0b8 ), SCU_RD( 0x0bc ));
979  
980  	PRINTF( option, "[SCU] 13c:%08x 140:%08x 144:%08x 1dc:%08x\n", SCU_RD( 0x13c ), SCU_RD( 0x140 ), SCU_RD( 0x144 ), SCU_RD( 0x1dc ) );
981  	PRINTF( option, "[WDT]  0c:%08x  2c:%08x  4c:%08x\n", eng->reg.WDT_00c, eng->reg.WDT_02c, eng->reg.WDT_04c );
982  	PRINTF( option, "[MAC]  A0|%08x %08x %08x %08x\n", mac_reg_read( eng, 0xa0 ), mac_reg_read( eng, 0xa4 ), mac_reg_read( eng, 0xa8 ), mac_reg_read( eng, 0xac ) );
983  	PRINTF( option, "[MAC]  B0|%08x %08x %08x %08x\n", mac_reg_read( eng, 0xb0 ), mac_reg_read( eng, 0xb4 ), mac_reg_read( eng, 0xb8 ), mac_reg_read( eng, 0xbc ) );
984  	PRINTF( option, "[MAC]  C0|%08x %08x %08x\n",       mac_reg_read( eng, 0xc0 ), mac_reg_read( eng, 0xc4 ), mac_reg_read( eng, 0xc8 ) );
985  
986  } // End void FPri_RegValue (MAC_ENGINE *eng, uint8_t *fp)
987  
988  //------------------------------------------------------------
FPri_End(MAC_ENGINE * eng,uint8_t option)989  void FPri_End (MAC_ENGINE *eng, uint8_t option)
990  {
991  	nt_log_func_name();
992  	if ((0 == eng->run.is_rgmii) && (eng->phy.RMIICK_IOMode != 0) &&
993  	    eng->run.IO_MrgChk && eng->flg.all_fail) {
994  		if ( eng->arg.ctrl.b.rmii_phy_in == 0 ) {
995  			PRINTF( option, "\n\n\n\n\n\n[Info] The PHY's RMII reference clock pin is setting to the OUTPUT mode now.\n" );
996  			PRINTF( option, "       Maybe you can run the INPUT mode command \"mactest  %d %d %d %d %d %d %d\".\n\n\n\n", eng->arg.mac_idx, eng->arg.run_speed, (eng->arg.ctrl.w | 0x80), eng->arg.loop_max, eng->arg.test_mode, eng->arg.phy_addr, eng->arg.delay_scan_range );
997  		}
998  		else {
999  			PRINTF( option, "\n\n\n\n\n\n[Info] The PHY's RMII reference clock pin is setting to the INPUT mode now.\n" );
1000  			PRINTF( option, "       Maybe you can run the OUTPUT mode command \"mactest  %d %d %d %d %d %d %d\".\n\n\n\n", eng->arg.mac_idx, eng->arg.run_speed, (eng->arg.ctrl.w & 0x7f), eng->arg.loop_max, eng->arg.test_mode, eng->arg.phy_addr, eng->arg.delay_scan_range );
1001  		}
1002  	}
1003  
1004  	if (!eng->run.TM_RxDataEn) {
1005  	} else if (eng->flg.error) {
1006  		PRINTF(option, "                    \n----> fail !!!\n");
1007  	}
1008  
1009  	//------------------------------
1010  	//[Warning] PHY Address
1011  	//------------------------------
1012  	if ( eng->arg.run_mode == MODE_DEDICATED ) {
1013  		if ( eng->arg.phy_addr != eng->phy.Adr )
1014  			PRINTF( option, "\n[Warning] PHY Address change from %d to %d !!!\n", eng->arg.phy_addr, eng->phy.Adr );
1015  	}
1016  
1017  	/* [Warning] IO Strength */
1018  	if (eng->io.init_done) {
1019  #ifdef CONFIG_ASPEED_AST2600
1020  		if ((eng->io.mac34_drv_reg.value.b.mac3_tx_drv != 0x3) ||
1021  		    (eng->io.mac34_drv_reg.value.b.mac4_tx_drv != 0x3)) {
1022  			PRINTF(option,
1023  			       "\n[Warning] [%08x] bit[3:0] 0x%02x is not the recommended value "
1024  			       "0xf.\n",
1025  			       eng->io.mac34_drv_reg.addr,
1026  			       eng->io.mac34_drv_reg.value.w & 0xf);
1027  		}
1028  #else
1029  		if (eng->io.mac12_drv_reg.value.w & GENMASK(11, 8)) {
1030  			PRINTF(option,
1031  			       "\n[Warning] [%08X] 0x%08x is not the recommended value "
1032  			       "0.\n",
1033  			       eng->io.mac12_drv_reg.addr,
1034  			       eng->io.mac12_drv_reg.value.w);
1035  		}
1036  #endif
1037  	}
1038  
1039  	//------------------------------
1040  	//[Warning] IO Timing
1041  	//------------------------------
1042  	if ( eng->arg.run_mode == MODE_NCSI ) {
1043  		PRINTF( option, "\n[Arg] %d %d %d %d %d %d %d {%d}\n", eng->arg.mac_idx, eng->arg.GPackageTolNum, eng->arg.GChannelTolNum, eng->arg.test_mode, eng->arg.delay_scan_range, eng->arg.ctrl.w, eng->arg.GARPNumCnt, TIME_OUT_NCSI );
1044  
1045  		switch ( eng->ncsi_cap.PCI_DID_VID ) {
1046  			case PCI_DID_VID_Intel_82574L             : { PRINTF( option, "[NC]%08x %08x: Intel 82574L       \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1047  			case PCI_DID_VID_Intel_82575_10d6         : { PRINTF( option, "[NC]%08x %08x: Intel 82575        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1048  			case PCI_DID_VID_Intel_82575_10a7         : { PRINTF( option, "[NC]%08x %08x: Intel 82575        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1049  			case PCI_DID_VID_Intel_82575_10a9         : { PRINTF( option, "[NC]%08x %08x: Intel 82575        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1050  			case PCI_DID_VID_Intel_82576_10c9         : { PRINTF( option, "[NC]%08x %08x: Intel 82576        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1051  			case PCI_DID_VID_Intel_82576_10e6         : { PRINTF( option, "[NC]%08x %08x: Intel 82576        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1052  			case PCI_DID_VID_Intel_82576_10e7         : { PRINTF( option, "[NC]%08x %08x: Intel 82576        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1053  			case PCI_DID_VID_Intel_82576_10e8         : { PRINTF( option, "[NC]%08x %08x: Intel 82576        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1054  			case PCI_DID_VID_Intel_82576_1518         : { PRINTF( option, "[NC]%08x %08x: Intel 82576        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1055  			case PCI_DID_VID_Intel_82576_1526         : { PRINTF( option, "[NC]%08x %08x: Intel 82576        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1056  			case PCI_DID_VID_Intel_82576_150a         : { PRINTF( option, "[NC]%08x %08x: Intel 82576        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1057  			case PCI_DID_VID_Intel_82576_150d         : { PRINTF( option, "[NC]%08x %08x: Intel 82576        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1058  			case PCI_DID_VID_Intel_82599_10fb         : { PRINTF( option, "[NC]%08x %08x: Intel 82599        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1059  			case PCI_DID_VID_Intel_82599_1557         : { PRINTF( option, "[NC]%08x %08x: Intel 82599        \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1060  			case PCI_DID_VID_Intel_I210_1533          : { PRINTF( option, "[NC]%08x %08x: Intel I210         \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1061  			case PCI_DID_VID_Intel_I210_1537          : { PRINTF( option, "[NC]%08x %08x: Intel I210         \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1062  			case PCI_DID_VID_Intel_I350_1521          : { PRINTF( option, "[NC]%08x %08x: Intel I350         \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1063  			case PCI_DID_VID_Intel_I350_1523          : { PRINTF( option, "[NC]%08x %08x: Intel I350         \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1064  			case PCI_DID_VID_Intel_X540               : { PRINTF( option, "[NC]%08x %08x: Intel X540         \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1065  			case PCI_DID_VID_Intel_X550               : { PRINTF( option, "[NC]%08x %08x: Intel X550         \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1066  			case PCI_DID_VID_Intel_Broadwell_DE       : { PRINTF( option, "[NC]%08x %08x: Intel Broadwell-DE \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1067  			case PCI_DID_VID_Intel_X722_37d0          : { PRINTF( option, "[NC]%08x %08x: Intel X722         \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1068  			case PCI_DID_VID_Broadcom_BCM5718         : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5718   \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1069  			case PCI_DID_VID_Broadcom_BCM5719         : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5719   \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1070  			case PCI_DID_VID_Broadcom_BCM5720         : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5720   \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1071  			case PCI_DID_VID_Broadcom_BCM5725         : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM5725   \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1072  			case PCI_DID_VID_Broadcom_BCM57810S       : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM57810S \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1073  			case PCI_DID_VID_Broadcom_Cumulus         : { PRINTF( option, "[NC]%08x %08x: Broadcom Cumulus   \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1074  			case PCI_DID_VID_Broadcom_BCM57302        : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM57302  \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1075  			case PCI_DID_VID_Broadcom_BCM957452       : { PRINTF( option, "[NC]%08x %08x: Broadcom BCM957452 \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1076  			case PCI_DID_VID_Mellanox_ConnectX_3_1003 : { PRINTF( option, "[NC]%08x %08x: Mellanox ConnectX-3\n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1077  			case PCI_DID_VID_Mellanox_ConnectX_3_1007 : { PRINTF( option, "[NC]%08x %08x: Mellanox ConnectX-3\n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1078  			case PCI_DID_VID_Mellanox_ConnectX_4      : { PRINTF( option, "[NC]%08x %08x: Mellanox ConnectX-4\n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1079  			default:
1080  			switch ( eng->ncsi_cap.manufacturer_id ) {
1081  				case ManufacturerID_Intel    : { PRINTF( option, "[NC]%08x %08x: Intel              \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1082  				case ManufacturerID_Broadcom : { PRINTF( option, "[NC]%08x %08x: Broadcom           \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1083  				case ManufacturerID_Mellanox : { PRINTF( option, "[NC]%08x %08x: Mellanox           \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1084  				case ManufacturerID_Mellanox1: { PRINTF( option, "[NC]%08x %08x: Mellanox           \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1085  				case ManufacturerID_Emulex   : { PRINTF( option, "[NC]%08x %08x: Emulex             \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1086  				default                      : { PRINTF( option, "[NC]%08x %08x                     \n", eng->ncsi_cap.manufacturer_id, eng->ncsi_cap.PCI_DID_VID ); break; }
1087  			} // End switch ( eng->ncsi_cap.manufacturer_id )
1088  		} // End switch ( eng->ncsi_cap.PCI_DID_VID )
1089  	}
1090  	else {
1091  		PRINTF(option, "[PHY] @addr %d: id = %04x_%04x (%s)\n",
1092  		       eng->phy.Adr, eng->phy.id1, eng->phy.id2,
1093  		       eng->phy.phy_name);
1094  	} // End if ( eng->arg.run_mode == MODE_NCSI )
1095  } // End void FPri_End (MAC_ENGINE *eng, uint8_t option)
1096  
1097  //------------------------------------------------------------
FPri_ErrFlag(MAC_ENGINE * eng,uint8_t option)1098  void FPri_ErrFlag (MAC_ENGINE *eng, uint8_t option)
1099  {
1100  	nt_log_func_name();
1101  	if ( eng->flg.print_en ) {
1102  		if ( eng->flg.warn ) {
1103  			if ( eng->flg.warn & Wrn_Flag_IOMarginOUF ) {
1104  				PRINTF(option, "[Warning] IO timing testing "
1105  					       "range out of boundary\n");
1106  
1107  				if (0 == eng->run.is_rgmii) {
1108  					PRINTF( option, "      (reg:%d,%d) %dx1(%d~%d,%d)\n", eng->io.Dly_in_reg_idx,
1109  											      eng->io.Dly_out_reg_idx,
1110  											      eng->run.delay_margin,
1111  											      eng->io.Dly_in_min,
1112  											      eng->io.Dly_in_max,
1113  											      eng->io.Dly_out_min );
1114  				}
1115  				else {
1116  					PRINTF( option, "      (reg:%d,%d) %dx%d(%d~%d,%d~%d)\n", eng->io.Dly_in_reg_idx,
1117  												  eng->io.Dly_out_reg_idx,
1118  												  eng->run.delay_margin,
1119  												  eng->run.delay_margin,
1120  												  eng->io.Dly_in_min,
1121  												  eng->io.Dly_in_max,
1122  												  eng->io.Dly_out_min,
1123  												  eng->io.Dly_out_max );
1124  				}
1125  			} // End if ( eng->flg.warn & Wrn_Flag_IOMarginOUF )
1126  			if ( eng->flg.warn & Wrn_Flag_RxErFloatting ) {
1127  				PRINTF( option, "[Warning] NCSI RXER pin may be floatting to the MAC !!!\n" );
1128  				PRINTF( option, "          Please contact with the ASPEED Inc. for more help.\n" );
1129  			} // End if ( eng->flg.warn & Wrn_Flag_RxErFloatting )
1130  		} // End if ( eng->flg.warn )
1131  
1132  		if ( eng->flg.error ) {
1133  			PRINTF( option, "\n\n" );
1134  //PRINTF( option, "error: %x\n\n", eng->flg.error );
1135  
1136  			if ( eng->flg.error & Err_Flag_PHY_Type                ) { PRINTF( option, "[Err] Unidentifiable PHY                                     \n" ); }
1137  			if ( eng->flg.error & Err_Flag_MALLOC_FrmSize          ) { PRINTF( option, "[Err] Malloc fail at frame size buffer                       \n" ); }
1138  			if ( eng->flg.error & Err_Flag_MALLOC_LastWP           ) { PRINTF( option, "[Err] Malloc fail at last WP buffer                          \n" ); }
1139  			if ( eng->flg.error & Err_Flag_Check_Buf_Data          ) { PRINTF( option, "[Err] Received data mismatch                                 \n" ); }
1140  			if ( eng->flg.error & Err_Flag_NCSI_Check_TxOwnTimeOut ) { PRINTF( option, "[Err] Time out of checking Tx owner bit in NCSI packet       \n" ); }
1141  			if ( eng->flg.error & Err_Flag_NCSI_Check_RxOwnTimeOut ) { PRINTF( option, "[Err] Time out of checking Rx owner bit in NCSI packet       \n" ); }
1142  			if ( eng->flg.error & Err_Flag_NCSI_Check_ARPOwnTimeOut) { PRINTF( option, "[Err] Time out of checking ARP owner bit in NCSI packet      \n" ); }
1143  			if ( eng->flg.error & Err_Flag_NCSI_No_PHY             ) { PRINTF( option, "[Err] Can not find NCSI PHY                                  \n" ); }
1144  			if ( eng->flg.error & Err_Flag_NCSI_Channel_Num        ) { PRINTF( option, "[Err] NCSI Channel Number Mismatch                           \n" ); }
1145  			if ( eng->flg.error & Err_Flag_NCSI_Package_Num        ) { PRINTF( option, "[Err] NCSI Package Number Mismatch                           \n" ); }
1146  			if ( eng->flg.error & Err_Flag_PHY_TimeOut_RW          ) { PRINTF( option, "[Err] Time out of read/write PHY register                    \n" ); }
1147  			if ( eng->flg.error & Err_Flag_PHY_TimeOut_Rst         ) { PRINTF( option, "[Err] Time out of reset PHY register                         \n" ); }
1148  			if ( eng->flg.error & Err_Flag_RXBUF_UNAVA             ) { PRINTF( option, "[Err] MAC00h[2]:Receiving buffer unavailable                 \n" ); }
1149  			if ( eng->flg.error & Err_Flag_RPKT_LOST               ) { PRINTF( option, "[Err] MAC00h[3]:Received packet lost due to RX FIFO full     \n" ); }
1150  			if ( eng->flg.error & Err_Flag_NPTXBUF_UNAVA           ) { PRINTF( option, "[Err] MAC00h[6]:Normal priority transmit buffer unavailable  \n" ); }
1151  			if ( eng->flg.error & Err_Flag_TPKT_LOST               ) { PRINTF( option, "[Err] MAC00h[7]:Packets transmitted to Ethernet lost         \n" ); }
1152  			if ( eng->flg.error & Err_Flag_DMABufNum               ) { PRINTF( option, "[Err] DMA Buffer is not enough                               \n" ); }
1153  			if ( eng->flg.error & Err_Flag_IOMargin                ) { PRINTF( option, "[Err] IO timing margin is not enough                         \n" ); }
1154  
1155  			if ( eng->flg.error & Err_Flag_MHCLK_Ratio             ) {
1156  				PRINTF( option, "[Err] Error setting of MAC AHB bus clock (SCU08[18:16])      \n" );
1157  				if ( eng->env.at_least_1g_valid )
1158  					{ PRINTF( option, "      SCU08[18:16] == 0x%01x is not the suggestion value 2.\n", eng->env.MHCLK_Ratio ); }
1159  				else
1160  					{ PRINTF( option, "      SCU08[18:16] == 0x%01x is not the suggestion value 4.\n", eng->env.MHCLK_Ratio ); }
1161  			} // End if ( eng->flg.error & Err_Flag_MHCLK_Ratio             )
1162  
1163  			if ( eng->flg.error & Err_Flag_IOMarginOUF ) {
1164  				PRINTF( option, "[Err] IO timing testing range out of boundary\n");
1165  				if (0 == eng->run.is_rgmii) {
1166  					PRINTF( option, "      (reg:%d,%d) %dx1(%d~%d,%d)\n", eng->io.Dly_in_reg_idx,
1167  											      eng->io.Dly_out_reg_idx,
1168  											      eng->run.delay_margin,
1169  											      eng->io.Dly_in_min,
1170  											      eng->io.Dly_in_max,
1171  											      eng->io.Dly_out_min );
1172  				}
1173  				else {
1174  					PRINTF( option, "      (reg:%d,%d) %dx%d(%d~%d,%d~%d)\n", eng->io.Dly_in_reg_idx,
1175  												  eng->io.Dly_out_reg_idx,
1176  												  eng->run.delay_margin,
1177  												  eng->run.delay_margin,
1178  												  eng->io.Dly_in_min,
1179  												  eng->io.Dly_in_max,
1180  												  eng->io.Dly_out_min,
1181  												  eng->io.Dly_out_max );
1182  				}
1183  			} // End if ( eng->flg.error & Err_Flag_IOMarginOUF )
1184  
1185  			if ( eng->flg.error & Err_Flag_Check_Des ) {
1186  				PRINTF( option, "[Err] Descriptor error\n");
1187  				if ( eng->flg.desc & Des_Flag_TxOwnTimeOut ) { PRINTF( option, "[Des] Time out of checking Tx owner bit\n" ); }
1188  				if ( eng->flg.desc & Des_Flag_RxOwnTimeOut ) { PRINTF( option, "[Des] Time out of checking Rx owner bit\n" ); }
1189  				if ( eng->flg.desc & Des_Flag_FrameLen     ) { PRINTF( option, "[Des] Frame length mismatch            \n" ); }
1190  				if ( eng->flg.desc & Des_Flag_RxErr        ) { PRINTF( option, "[Des] Input signal RxErr               \n" ); }
1191  				if ( eng->flg.desc & Des_Flag_CRC          ) { PRINTF( option, "[Des] CRC error of frame               \n" ); }
1192  				if ( eng->flg.desc & Des_Flag_FTL          ) { PRINTF( option, "[Des] Frame too long                   \n" ); }
1193  				if ( eng->flg.desc & Des_Flag_Runt         ) { PRINTF( option, "[Des] Runt packet                      \n" ); }
1194  				if ( eng->flg.desc & Des_Flag_OddNibble    ) { PRINTF( option, "[Des] Nibble bit happen                \n" ); }
1195  				if ( eng->flg.desc & Des_Flag_RxFIFOFull   ) { PRINTF( option, "[Des] Rx FIFO full                     \n" ); }
1196  			} // End if ( eng->flg.error & Err_Flag_Check_Des )
1197  
1198  			if ( eng->flg.error & Err_Flag_MACMode ) {
1199  				PRINTF( option, "[Err] MAC interface mode mismatch\n" );
1200  				for (int i = 0; i < 4; i++) {
1201  					if (eng->env.is_1g_valid[i]) {
1202  						PRINTF(option,
1203  						       "[MAC%d] is RGMII\n", i);
1204  					} else {
1205  						PRINTF(option,
1206  						       "[MAC%d] RMII\n", i);
1207  					}
1208  				}
1209  			} // End if ( eng->flg.error & Err_Flag_MACMode )
1210  
1211  			if ( eng->arg.run_mode == MODE_NCSI ) {
1212  				if ( eng->flg.error & ERR_FLAG_NCSI_LINKFAIL ) {
1213  					PRINTF( option, "[Err] NCSI packet retry number over flows when find channel\n" );
1214  
1215  					if ( eng->flg.ncsi & NCSI_Flag_Get_Version_ID                  ) { PRINTF( option, "[NCSI] Time out when Get Version ID                  \n" ); }
1216  					if ( eng->flg.ncsi & NCSI_Flag_Get_Capabilities                ) { PRINTF( option, "[NCSI] Time out when Get Capabilities                \n" ); }
1217  					if ( eng->flg.ncsi & NCSI_Flag_Select_Active_Package           ) { PRINTF( option, "[NCSI] Time out when Select Active Package           \n" ); }
1218  					if ( eng->flg.ncsi & NCSI_Flag_Enable_Set_MAC_Address          ) { PRINTF( option, "[NCSI] Time out when Enable Set MAC Address          \n" ); }
1219  					if ( eng->flg.ncsi & NCSI_Flag_Enable_Broadcast_Filter         ) { PRINTF( option, "[NCSI] Time out when Enable Broadcast Filter         \n" ); }
1220  					if ( eng->flg.ncsi & NCSI_Flag_Enable_Network_TX               ) { PRINTF( option, "[NCSI] Time out when Enable Network TX               \n" ); }
1221  					if ( eng->flg.ncsi & NCSI_Flag_Enable_Channel                  ) { PRINTF( option, "[NCSI] Time out when Enable Channel                  \n" ); }
1222  					if ( eng->flg.ncsi & NCSI_Flag_Disable_Network_TX              ) { PRINTF( option, "[NCSI] Time out when Disable Network TX              \n" ); }
1223  					if ( eng->flg.ncsi & NCSI_Flag_Disable_Channel                 ) { PRINTF( option, "[NCSI] Time out when Disable Channel                 \n" ); }
1224  					if ( eng->flg.ncsi & NCSI_Flag_Select_Package                  ) { PRINTF( option, "[NCSI] Time out when Select Package                  \n" ); }
1225  					if ( eng->flg.ncsi & NCSI_Flag_Deselect_Package                ) { PRINTF( option, "[NCSI] Time out when Deselect Package                \n" ); }
1226  					if ( eng->flg.ncsi & NCSI_Flag_Set_Link                        ) { PRINTF( option, "[NCSI] Time out when Set Link                        \n" ); }
1227  					if ( eng->flg.ncsi & NCSI_Flag_Get_Controller_Packet_Statistics) { PRINTF( option, "[NCSI] Time out when Get Controller Packet Statistics\n" ); }
1228  				}
1229  
1230  				if ( eng->flg.error & Err_Flag_NCSI_Channel_Num ) { PRINTF( option, "[NCSI] Channel number expected: %d, real: %d\n", eng->arg.GChannelTolNum, eng->dat.number_chl ); }
1231  				if ( eng->flg.error & Err_Flag_NCSI_Package_Num ) { PRINTF( option, "[NCSI] Peckage number expected: %d, real: %d\n", eng->arg.GPackageTolNum, eng->dat.number_pak ); }
1232  			} // End if ( eng->arg.run_mode == MODE_NCSI )
1233  		} // End if ( eng->flg.error )
1234  	} // End if ( eng->flg.print_en )
1235  } // End void FPri_ErrFlag (MAC_ENGINE *eng, uint8_t option)
1236  
1237  //------------------------------------------------------------
1238  
1239  //------------------------------------------------------------
FindErr(MAC_ENGINE * p_eng,int value)1240  int FindErr (MAC_ENGINE *p_eng, int value)
1241  {
1242  	p_eng->flg.error = p_eng->flg.error | value;
1243  
1244  	if (DBG_PRINT_ERR_FLAG)
1245  		printf("flags: error = %08x\n", p_eng->flg.error);
1246  
1247  	return (1);
1248  }
1249  
1250  //------------------------------------------------------------
FindErr_Des(MAC_ENGINE * p_eng,int value)1251  int FindErr_Des (MAC_ENGINE *p_eng, int value)
1252  {
1253  	p_eng->flg.error = p_eng->flg.error | Err_Flag_Check_Des;
1254  	p_eng->flg.desc = p_eng->flg.desc | value;
1255  	if (DBG_PRINT_ERR_FLAG)
1256  		printf("flags: error = %08x, desc = %08x\n", p_eng->flg.error, p_eng->flg.desc);
1257  
1258  	return (1);
1259  }
1260  
1261  //------------------------------------------------------------
1262  // Get and Check status of Interrupt
1263  //------------------------------------------------------------
check_int(MAC_ENGINE * eng,char * type)1264  int check_int (MAC_ENGINE *eng, char *type )
1265  {
1266  	nt_log_func_name();
1267  
1268  	uint32_t mac_00;
1269  
1270  	mac_00 = mac_reg_read(eng, 0x00);
1271  #ifdef CheckRxbufUNAVA
1272  	if (mac_00 & BIT(2)) {
1273  		PRINTF( FP_LOG, "[%sIntStatus] Receiving buffer unavailable               : %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt );
1274  		FindErr( eng, Err_Flag_RXBUF_UNAVA );
1275  	}
1276  #endif
1277  
1278  #ifdef CheckRPktLost
1279  	if (mac_00 & BIT(3)) {
1280  		PRINTF( FP_LOG, "[%sIntStatus] Received packet lost due to RX FIFO full   : %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt );
1281  		FindErr( eng, Err_Flag_RPKT_LOST );
1282  	}
1283  #endif
1284  
1285  #ifdef CheckNPTxbufUNAVA
1286  	if (mac_00 & BIT(6) ) {
1287  		PRINTF( FP_LOG, "[%sIntStatus] Normal priority transmit buffer unavailable: %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt );
1288  		FindErr( eng, Err_Flag_NPTXBUF_UNAVA );
1289  	}
1290  #endif
1291  
1292  #ifdef CheckTPktLost
1293  	if (mac_00 & BIT(7)) {
1294  		PRINTF( FP_LOG, "[%sIntStatus] Packets transmitted to Ethernet lost       : %08x [loop[%d]:%d]\n", type, mac_00, eng->run.loop_of_cnt, eng->run.loop_cnt );
1295  		FindErr( eng, Err_Flag_TPKT_LOST );
1296  	}
1297  #endif
1298  
1299  	if ( eng->flg.error )
1300  		return(1);
1301  	else
1302  		return(0);
1303  } // End int check_int (MAC_ENGINE *eng, char *type)
1304  
1305  
1306  //------------------------------------------------------------
1307  // Buffer
1308  //------------------------------------------------------------
setup_framesize(MAC_ENGINE * eng)1309  void setup_framesize (MAC_ENGINE *eng)
1310  {
1311  	int32_t       des_num;
1312  
1313  	nt_log_func_name();
1314  
1315  	//------------------------------
1316  	// Fill Frame Size out descriptor area
1317  	//------------------------------
1318  	if (0) {
1319  		for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) {
1320  			if ( RAND_SIZE_SIMPLE )
1321  				switch( rand() % 5 ) {
1322  					case 0 : eng->dat.FRAME_LEN[ des_num ] = 0x4e ; break;
1323  					case 1 : eng->dat.FRAME_LEN[ des_num ] = 0x4ba; break;
1324  					default: eng->dat.FRAME_LEN[ des_num ] = 0x5ea; break;
1325  				}
1326  			else
1327  //				eng->dat.FRAME_LEN[ des_num ] = ( rand() + RAND_SIZE_MIN ) % ( RAND_SIZE_MAX + 1 );
1328  				eng->dat.FRAME_LEN[ des_num ] = RAND_SIZE_MIN + ( rand() % ( RAND_SIZE_MAX - RAND_SIZE_MIN + 1 ) );
1329  
1330  			if ( DbgPrn_FRAME_LEN )
1331  				PRINTF( FP_LOG, "[setup_framesize] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", eng->dat.FRAME_LEN[ des_num ], des_num, eng->run.loop_of_cnt, eng->run.loop_cnt );
1332  		}
1333  	}
1334  	else {
1335  		for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) {
1336  #ifdef SelectSimpleLength
1337  			if ( des_num % FRAME_SELH_PERD )
1338  				eng->dat.FRAME_LEN[ des_num ] = FRAME_LENH;
1339  			else
1340  				eng->dat.FRAME_LEN[ des_num ] = FRAME_LENL;
1341  #else
1342  			if ( eng->run.tm_tx_only ) {
1343  				if ( eng->run.TM_IEEE )
1344  					eng->dat.FRAME_LEN[ des_num ] = 1514;
1345  				else
1346  					eng->dat.FRAME_LEN[ des_num ] = 60;
1347  			}
1348  			else {
1349    #ifdef SelectLengthInc
1350  				eng->dat.FRAME_LEN[ des_num ] = 1514 - ( des_num % 1455 );
1351    #else
1352  				if ( des_num % FRAME_SELH_PERD )
1353  					eng->dat.FRAME_LEN[ des_num ] = FRAME_LENH;
1354  				else
1355  					eng->dat.FRAME_LEN[ des_num ] = FRAME_LENL;
1356    #endif
1357  			} // End if ( eng->run.tm_tx_only )
1358  #endif
1359  			if ( DbgPrn_FRAME_LEN )
1360  				PRINTF( FP_LOG, "[setup_framesize] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", eng->dat.FRAME_LEN[ des_num ], des_num, eng->run.loop_of_cnt, eng->run.loop_cnt );
1361  
1362  		} // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++)
1363  	} // End if ( ENABLE_RAND_SIZE )
1364  
1365  	// Calculate average of frame size
1366  #ifdef Enable_ShowBW
1367  	eng->dat.Total_frame_len = 0;
1368  
1369  	for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ )
1370  		eng->dat.Total_frame_len += eng->dat.FRAME_LEN[ des_num ];
1371  #endif
1372  
1373  	//------------------------------
1374  	// Write Plane
1375  	//------------------------------
1376  	switch( ZeroCopy_OFFSET & 0x3 ) {
1377  		case 0: eng->dat.wp_fir = 0xffffffff; break;
1378  		case 1: eng->dat.wp_fir = 0xffffff00; break;
1379  		case 2: eng->dat.wp_fir = 0xffff0000; break;
1380  		case 3: eng->dat.wp_fir = 0xff000000; break;
1381  	}
1382  
1383  	for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ )
1384  		switch( ( ZeroCopy_OFFSET + eng->dat.FRAME_LEN[ des_num ] - 1 ) & 0x3 ) {
1385  			case 0: eng->dat.wp_lst[ des_num ] = 0x000000ff; break;
1386  			case 1: eng->dat.wp_lst[ des_num ] = 0x0000ffff; break;
1387  			case 2: eng->dat.wp_lst[ des_num ] = 0x00ffffff; break;
1388  			case 3: eng->dat.wp_lst[ des_num ] = 0xffffffff; break;
1389  		}
1390  } // End void setup_framesize (void)
1391  
1392  //------------------------------------------------------------
setup_arp(MAC_ENGINE * eng)1393  void setup_arp(MAC_ENGINE *eng)
1394  {
1395  
1396  	nt_log_func_name();
1397  
1398  	memcpy(eng->dat.ARP_data, ARP_org_data, sizeof(ARP_org_data));
1399  
1400  	eng->dat.ARP_data[1] &= ~GENMASK(31, 16);
1401  	eng->dat.ARP_data[1] |= (eng->inf.SA[1] << 24) | (eng->inf.SA[0] << 16);
1402  	eng->dat.ARP_data[2] = (eng->inf.SA[5] << 24) | (eng->inf.SA[4] << 16) |
1403  			       (eng->inf.SA[3] << 8) | (eng->inf.SA[2]);
1404  	eng->dat.ARP_data[5] &= ~GENMASK(31, 16);
1405  	eng->dat.ARP_data[5] |= (eng->inf.SA[1] << 24) | (eng->inf.SA[0] << 16);
1406  	eng->dat.ARP_data[6] = (eng->inf.SA[5] << 24) | (eng->inf.SA[4] << 16) |
1407  			       (eng->inf.SA[3] << 8) | (eng->inf.SA[2]);
1408  }
1409  
1410  //------------------------------------------------------------
setup_buf(MAC_ENGINE * eng)1411  void setup_buf (MAC_ENGINE *eng)
1412  {
1413  	int32_t des_num_max;
1414  	int32_t des_num;
1415  	int i;
1416  	uint32_t adr;
1417  	uint32_t adr_srt;
1418  	uint32_t adr_end;
1419  	uint32_t Current_framelen;
1420  	uint32_t gdata = 0;
1421  #ifdef SelectSimpleDA
1422  	int cnt;
1423  	uint32_t len;
1424  #endif
1425  
1426  	nt_log_func_name();
1427  
1428  	// It need be multiple of 4
1429  	eng->dat.DMA_Base_Setup = DMA_BASE & 0xfffffffc;
1430  	adr_srt = eng->dat.DMA_Base_Setup;
1431  
1432  	if (eng->run.tm_tx_only) {
1433  		if (eng->run.TM_IEEE) {
1434  			for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) {
1435  				if ( DbgPrn_BufAdr )
1436  					printf("[loop[%d]:%4d][des:%4d][setup_buf  ] %08x\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, adr_srt);
1437  				Write_Mem_Dat_DD(adr_srt, 0xffffffff);
1438  				Write_Mem_Dat_DD(adr_srt + 4,
1439  						 eng->dat.ARP_data[1]);
1440  				Write_Mem_Dat_DD(adr_srt + 8,
1441  						 eng->dat.ARP_data[2]);
1442  
1443  				for (adr = (adr_srt + 12);
1444  				     adr < (adr_srt + DMA_PakSize); adr += 4) {
1445  					switch (eng->arg.test_mode) {
1446  					case 4:
1447  						gdata = rand() | (rand() << 16);
1448  						break;
1449  					case 5:
1450  						gdata = eng->arg.user_def_val;
1451  						break;
1452  					}
1453  					Write_Mem_Dat_DD(adr, gdata);
1454  				}
1455  				adr_srt += DMA_PakSize;
1456  			}
1457  		} else {
1458  			printf("----->[ARP] 60 bytes\n");
1459  			for (i = 0; i < 16; i++)
1460  				printf("      [Tx%02d] %08x %08x\n", i, eng->dat.ARP_data[i], SWAP_4B( eng->dat.ARP_data[i] ) );
1461  
1462  			for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) {
1463  				if ( DbgPrn_BufAdr )
1464  					printf("[loop[%d]:%4d][des:%4d][setup_buf  ] %08x\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, adr_srt);
1465  
1466  				for (i = 0; i < 16; i++)
1467  					Write_Mem_Dat_DD( adr_srt + ( i << 2 ), eng->dat.ARP_data[i] );
1468  
1469  
1470  				adr_srt += DMA_PakSize;
1471  			} // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++)
1472  		} // End if ( eng->run.TM_IEEE )
1473  	} else {
1474  		if ( eng->arg.ctrl.b.single_packet )
1475  			des_num_max = 1;
1476  		else
1477  			des_num_max = eng->dat.Des_Num;
1478  
1479  		for (des_num = 0; des_num < des_num_max; des_num++) {
1480  			if (DbgPrn_BufAdr)
1481  				printf("[loop[%d]:%4d][des:%4d][setup_buf  ] %08x\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, adr_srt);
1482    #ifdef SelectSimpleData
1483      #ifdef SimpleData_Fix
1484  			switch( des_num % SimpleData_FixNum ) {
1485  				case  0 : gdata = SimpleData_FixVal00; break;
1486  				case  1 : gdata = SimpleData_FixVal01; break;
1487  				case  2 : gdata = SimpleData_FixVal02; break;
1488  				case  3 : gdata = SimpleData_FixVal03; break;
1489  				case  4 : gdata = SimpleData_FixVal04; break;
1490  				case  5 : gdata = SimpleData_FixVal05; break;
1491  				case  6 : gdata = SimpleData_FixVal06; break;
1492  				case  7 : gdata = SimpleData_FixVal07; break;
1493  				case  8 : gdata = SimpleData_FixVal08; break;
1494  				case  9 : gdata = SimpleData_FixVal09; break;
1495  				case 10 : gdata = SimpleData_FixVal10; break;
1496  				default : gdata = SimpleData_FixVal11; break;
1497  			}
1498      #else
1499  			gdata   = 0x11111111 * ((des_num + SEED_START) % 256);
1500      #endif
1501    #else
1502  			gdata   = DATA_SEED( des_num + SEED_START );
1503    #endif
1504  			Current_framelen = eng->dat.FRAME_LEN[ des_num ];
1505  
1506  			if ( DbgPrn_FRAME_LEN )
1507  				PRINTF( FP_LOG, "[setup_buf      ] Current_framelen:%08x[Des:%d][loop[%d]:%d]\n", Current_framelen, des_num, eng->run.loop_of_cnt, eng->run.loop_cnt );
1508  #ifdef SelectSimpleDA
1509  			cnt     = 0;
1510  			len     = ( ( ( Current_framelen - 14 ) & 0xff ) << 8) |
1511  			            ( ( Current_framelen - 14 ) >> 8 );
1512  #endif
1513  			adr_end = adr_srt + DMA_PakSize;
1514  			for ( adr = adr_srt; adr < adr_end; adr += 4 ) {
1515    #ifdef SelectSimpleDA
1516  				cnt++;
1517  				if      ( cnt == 1 ) Write_Mem_Dat_DD( adr, SelectSimpleDA_Dat0 );
1518  				else if ( cnt == 2 ) Write_Mem_Dat_DD( adr, SelectSimpleDA_Dat1 );
1519  				else if ( cnt == 3 ) Write_Mem_Dat_DD( adr, SelectSimpleDA_Dat2 );
1520  				else if ( cnt == 4 ) Write_Mem_Dat_DD( adr, len | (len << 16)   );
1521  				else
1522    #endif
1523  				                     Write_Mem_Dat_DD( adr, gdata );
1524    #ifdef SelectSimpleData
1525  				gdata = gdata ^ SimpleData_XORVal;
1526    #else
1527  				gdata += DATA_IncVal;
1528    #endif
1529  			}
1530  			adr_srt += DMA_PakSize;
1531  		} // End for (des_num = 0; des_num < eng->dat.Des_Num; des_num++)
1532  	} // End if ( eng->run.tm_tx_only )
1533  } // End void setup_buf (MAC_ENGINE *eng)
1534  
1535  //------------------------------------------------------------
1536  // Check data of one packet
1537  //------------------------------------------------------------
check_Data(MAC_ENGINE * eng,uint32_t datbase,int32_t number)1538  char check_Data (MAC_ENGINE *eng, uint32_t datbase, int32_t number)
1539  {
1540  	int32_t       number_dat;
1541  	int        index;
1542  	uint32_t      rdata;
1543  	uint32_t      wp_lst_cur;
1544  	uint32_t      adr_las;
1545  	uint32_t      adr;
1546  	uint32_t      adr_srt;
1547  	uint32_t      adr_end;
1548  #ifdef SelectSimpleDA
1549  	int        cnt;
1550  	uint32_t      len;
1551  	uint32_t      gdata_bak;
1552  #endif
1553  	uint32_t      gdata;
1554  
1555  	uint32_t      wp;
1556  
1557  	nt_log_func_name();
1558  
1559  	if (eng->arg.ctrl.b.single_packet)
1560  		number_dat = 0;
1561  	else
1562  		number_dat = number;
1563  
1564  	wp_lst_cur             = eng->dat.wp_lst[ number ];
1565  	eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[ number_dat ];
1566  
1567  	if ( DbgPrn_FRAME_LEN )
1568  		PRINTF( FP_LOG, "[check_Data     ] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", eng->dat.FRAME_LEN_Cur, number, eng->run.loop_of_cnt, eng->run.loop_cnt );
1569  
1570  	adr_srt = datbase;
1571  	adr_end = adr_srt + PktByteSize;
1572  
1573  #if defined(SelectSimpleData)
1574      #ifdef SimpleData_Fix
1575  	switch( number_dat % SimpleData_FixNum ) {
1576  		case  0 : gdata = SimpleData_FixVal00; break;
1577  		case  1 : gdata = SimpleData_FixVal01; break;
1578  		case  2 : gdata = SimpleData_FixVal02; break;
1579  		case  3 : gdata = SimpleData_FixVal03; break;
1580  		case  4 : gdata = SimpleData_FixVal04; break;
1581  		case  5 : gdata = SimpleData_FixVal05; break;
1582  		case  6 : gdata = SimpleData_FixVal06; break;
1583  		case  7 : gdata = SimpleData_FixVal07; break;
1584  		case  8 : gdata = SimpleData_FixVal08; break;
1585  		case  9 : gdata = SimpleData_FixVal09; break;
1586  		case 10 : gdata = SimpleData_FixVal10; break;
1587  		default : gdata = SimpleData_FixVal11; break;
1588  	}
1589      #else
1590  	gdata   = 0x11111111 * (( number_dat + SEED_START ) % 256 );
1591      #endif
1592  #else
1593  	gdata   = DATA_SEED( number_dat + SEED_START );
1594  #endif
1595  
1596  //printf("check_buf: %08x - %08x [%08x]\n", adr_srt, adr_end, datbase);
1597  	wp      = eng->dat.wp_fir;
1598  	adr_las = adr_end - 4;
1599  #ifdef SelectSimpleDA
1600  	cnt     = 0;
1601  	len     = ((( eng->dat.FRAME_LEN_Cur-14 ) & 0xff ) << 8 ) |
1602  	          ( ( eng->dat.FRAME_LEN_Cur-14 )          >> 8 );
1603  #endif
1604  
1605  	if ( DbgPrn_Bufdat )
1606  		PRINTF( FP_LOG, " Inf:%08x ~ %08x(%08x) %08x [Des:%d][loop[%d]:%d]\n", adr_srt, adr_end, adr_las, gdata, number, eng->run.loop_of_cnt, eng->run.loop_cnt );
1607  
1608  	for ( adr = adr_srt; adr < adr_end; adr+=4 ) {
1609  #ifdef SelectSimpleDA
1610  		cnt++;
1611  		if      ( cnt == 1 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat0; }
1612  		else if ( cnt == 2 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat1; }
1613  		else if ( cnt == 3 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat2; }
1614  		else if ( cnt == 4 ) { gdata_bak = gdata; gdata = len | (len << 16);   }
1615  #endif
1616  		rdata = Read_Mem_Dat_DD( adr );
1617  		if ( adr == adr_las )
1618  			wp = wp & wp_lst_cur;
1619  
1620  		if ( ( rdata & wp ) != ( gdata & wp ) ) {
1621  			PRINTF( FP_LOG, "\nError: Adr:%08x[%3d] (%08x) (%08x:%08x) [Des:%d][loop[%d]:%d]\n", adr, ( adr - adr_srt ) / 4, rdata, gdata, wp, number, eng->run.loop_of_cnt, eng->run.loop_cnt );
1622  			for ( index = 0; index < 6; index++ )
1623  				PRINTF( FP_LOG, "Rep  : Adr:%08x      (%08x) (%08x:%08x) [Des:%d][loop[%d]:%d]\n", adr, Read_Mem_Dat_DD( adr ), gdata, wp, number, eng->run.loop_of_cnt, eng->run.loop_cnt );
1624  
1625  			if (DbgPrn_DumpMACCnt)
1626  				dump_mac_ROreg(eng);
1627  
1628  			return( FindErr( eng, Err_Flag_Check_Buf_Data ) );
1629  		} // End if ( (rdata & wp) != (gdata & wp) )
1630  		if ( DbgPrn_BufdatDetail )
1631  			PRINTF( FP_LOG, " Adr:%08x[%3d] (%08x) (%08x:%08x) [Des:%d][loop[%d]:%d]\n", adr, ( adr - adr_srt ) / 4, rdata, gdata, wp, number, eng->run.loop_of_cnt, eng->run.loop_cnt );
1632  
1633  #ifdef SelectSimpleDA
1634  		if ( cnt <= 4 )
1635  			gdata = gdata_bak;
1636  #endif
1637  
1638  #if defined(SelectSimpleData)
1639  		gdata = gdata ^ SimpleData_XORVal;
1640  #else
1641  		gdata += DATA_IncVal;
1642  #endif
1643  
1644  		wp     = 0xffffffff;
1645  	}
1646  	return(0);
1647  } // End char check_Data (MAC_ENGINE *eng, uint32_t datbase, int32_t number)
1648  
1649  //------------------------------------------------------------
check_buf(MAC_ENGINE * eng,int loopcnt)1650  char check_buf (MAC_ENGINE *eng, int loopcnt)
1651  {
1652  	int32_t des_num;
1653  	uint32_t desadr;
1654  #ifdef CHECK_RX_DATA
1655  	uint32_t datbase;
1656  #endif
1657  	nt_log_func_name();
1658  
1659  	desadr = eng->run.rdes_base + (16 * eng->dat.Des_Num) - 4;
1660  	for (des_num = eng->dat.Des_Num - 1; des_num >= 0; des_num--) {
1661  #ifdef CHECK_RX_DATA
1662  		datbase = AT_BUF_MEMRW(Read_Mem_Des_DD(desadr) & 0xfffffffc);
1663  		if (check_Data(eng, datbase, des_num)) {
1664  			check_int(eng, "");
1665  			return (1);
1666  		}
1667  		if (check_int(eng, ""))
1668  			return 1;
1669  #endif
1670  		desadr -= 16;
1671  	}
1672  	if (check_int(eng, ""))
1673  		return (1);
1674  
1675  #if defined(Delay_CheckData_LoopNum) && defined(Delay_CheckData)
1676  	if ((loopcnt % Delay_CheckData_LoopNum) == 0)
1677  		DELAY(Delay_CheckData);
1678  #endif
1679  	return (0);
1680  } // End char check_buf (MAC_ENGINE *eng, int loopcnt)
1681  
1682  //------------------------------------------------------------
1683  // Descriptor
1684  //------------------------------------------------------------
setup_txdes(MAC_ENGINE * eng,uint32_t desadr,uint32_t bufbase)1685  void setup_txdes (MAC_ENGINE *eng, uint32_t desadr, uint32_t bufbase)
1686  {
1687  	uint32_t bufadr;
1688  	uint32_t bufadrgap;
1689  	uint32_t desval = 0;
1690  	int32_t des_num;
1691  
1692  	nt_log_func_name();
1693  
1694  	bufadr = bufbase;
1695  	if (eng->arg.ctrl.b.single_packet)
1696  		bufadrgap = 0;
1697  	else
1698  		bufadrgap = DMA_PakSize;
1699  
1700  	if (eng->run.TM_TxDataEn) {
1701  		for (des_num = 0; des_num < eng->dat.Des_Num; des_num++) {
1702  			eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[des_num];
1703  			desval = TDES_IniVal;
1704  			Write_Mem_Des_DD(desadr + 0x04, 0);
1705  			Write_Mem_Des_DD(desadr + 0x08, 0);
1706  			Write_Mem_Des_DD(desadr + 0x0C, bufadr);
1707  			Write_Mem_Des_DD(desadr, desval);
1708  
1709  			if (DbgPrn_FRAME_LEN)
1710  				PRINTF(
1711  				    FP_LOG,
1712  				    "[setup_txdes    ] "
1713  				    "FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n",
1714  				    eng->dat.FRAME_LEN_Cur, des_num,
1715  				    eng->run.loop_of_cnt, eng->run.loop_cnt);
1716  
1717  			if (DbgPrn_BufAdr)
1718  				printf("[loop[%d]:%4d][des:%4d][setup_txdes] "
1719  				       "%08x [%08x]\n",
1720  				       eng->run.loop_of_cnt, eng->run.loop_cnt,
1721  				       des_num, desadr, bufadr);
1722  
1723  			desadr += 16;
1724  			bufadr += bufadrgap;
1725  		}
1726  		barrier();
1727  		Write_Mem_Des_DD(desadr - 0x10, desval | EOR_IniVal);
1728  	} else {
1729  		Write_Mem_Des_DD(desadr, 0);
1730  	}
1731  }
1732  
1733  //------------------------------------------------------------
setup_rxdes(MAC_ENGINE * eng,uint32_t desadr,uint32_t bufbase)1734  void setup_rxdes (MAC_ENGINE *eng, uint32_t desadr, uint32_t bufbase)
1735  {
1736  	uint32_t      bufadr;
1737  	uint32_t      desval;
1738  	int32_t       des_num;
1739  
1740  	nt_log_func_name();
1741  
1742  	bufadr = bufbase;
1743  	desval = RDES_IniVal;
1744  	if ( eng->run.TM_RxDataEn ) {
1745  		for ( des_num = 0; des_num < eng->dat.Des_Num; des_num++ ) {
1746  			Write_Mem_Des_DD(desadr + 0x04, 0     );
1747  			Write_Mem_Des_DD(desadr + 0x08, 0     );
1748  			Write_Mem_Des_DD(desadr + 0x0C, bufadr);
1749  			Write_Mem_Des_DD(desadr + 0x00, desval);
1750  
1751  			if ( DbgPrn_BufAdr )
1752  				printf("[loop[%d]:%4d][des:%4d][setup_rxdes] %08x [%08x]\n", eng->run.loop_of_cnt, eng->run.loop_cnt, des_num, desadr, bufadr);
1753  
1754  			desadr += 16;
1755  			bufadr += DMA_PakSize;
1756  		}
1757  		barrier();
1758  		Write_Mem_Des_DD( desadr - 0x10, desval | EOR_IniVal );
1759  	}
1760  	else {
1761  		Write_Mem_Des_DD( desadr, 0x80000000 );
1762  	} // End if ( eng->run.TM_RxDataEn )
1763  } // End void setup_rxdes (uint32_t desadr, uint32_t bufbase)
1764  
1765  //------------------------------------------------------------
1766  // First setting TX and RX information
1767  //------------------------------------------------------------
setup_des(MAC_ENGINE * eng,uint32_t bufnum)1768  void setup_des (MAC_ENGINE *eng, uint32_t bufnum)
1769  {
1770  	if (DbgPrn_BufAdr) {
1771  		printf("setup_des: %d\n", bufnum);
1772  		debug_pause();
1773  	}
1774  
1775  	eng->dat.DMA_Base_Tx =
1776  	    ZeroCopy_OFFSET + eng->dat.DMA_Base_Setup;
1777  	eng->dat.DMA_Base_Rx = ZeroCopy_OFFSET + GET_DMA_BASE(eng, 0);
1778  
1779  	setup_txdes(eng, eng->run.tdes_base,
1780  		    AT_MEMRW_BUF(eng->dat.DMA_Base_Tx));
1781  	setup_rxdes(eng, eng->run.rdes_base,
1782  		    AT_MEMRW_BUF(eng->dat.DMA_Base_Rx));
1783  } // End void setup_des (uint32_t bufnum)
1784  
1785  //------------------------------------------------------------
1786  // Move buffer point of TX and RX descriptor to next DMA buffer
1787  //------------------------------------------------------------
setup_des_loop(MAC_ENGINE * eng,uint32_t bufnum)1788  void setup_des_loop (MAC_ENGINE *eng, uint32_t bufnum)
1789  {
1790  	int32_t des_num;
1791  	uint32_t H_rx_desadr;
1792  	uint32_t H_tx_desadr;
1793  	uint32_t H_tx_bufadr;
1794  	uint32_t H_rx_bufadr;
1795  
1796  	nt_log_func_name();
1797  
1798  	if (eng->run.TM_RxDataEn) {
1799  		H_rx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Rx);
1800  		H_rx_desadr = eng->run.rdes_base;
1801  		for (des_num = 0; des_num < eng->dat.Des_Num - 1; des_num++) {
1802  			Write_Mem_Des_DD(H_rx_desadr + 0x0C, H_rx_bufadr);
1803  			Write_Mem_Des_DD(H_rx_desadr, RDES_IniVal);
1804  			if (DbgPrn_BufAdr)
1805  				printf("[loop[%d]:%4d][des:%4d][setup_rxdes] "
1806  				       "%08x [%08x]\n",
1807  				       eng->run.loop_of_cnt, eng->run.loop_cnt,
1808  				       des_num, H_rx_desadr, H_rx_bufadr);
1809  
1810  			H_rx_bufadr += DMA_PakSize;
1811  			H_rx_desadr += 16;
1812  		}
1813  		Write_Mem_Des_DD(H_rx_desadr + 0x0C, H_rx_bufadr);
1814  		Write_Mem_Des_DD(H_rx_desadr, RDES_IniVal | EOR_IniVal);
1815  		if (DbgPrn_BufAdr)
1816  			printf("[loop[%d]:%4d][des:%4d][setup_rxdes] %08x "
1817  			       "[%08x]\n",
1818  			       eng->run.loop_of_cnt, eng->run.loop_cnt, des_num,
1819  			       H_rx_desadr, H_rx_bufadr);
1820  	}
1821  
1822  	if (eng->run.TM_TxDataEn) {
1823  		H_tx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Tx);
1824  		H_tx_desadr = eng->run.tdes_base;
1825  		for (des_num = 0; des_num < eng->dat.Des_Num - 1; des_num++) {
1826  			eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[des_num];
1827  			Write_Mem_Des_DD(H_tx_desadr + 0x0C, H_tx_bufadr);
1828  			Write_Mem_Des_DD(H_tx_desadr, TDES_IniVal);
1829  			if (DbgPrn_BufAdr)
1830  				printf("[loop[%d]:%4d][des:%4d][setup_txdes] "
1831  				       "%08x [%08x]\n",
1832  				       eng->run.loop_of_cnt, eng->run.loop_cnt,
1833  				       des_num, H_tx_desadr, H_tx_bufadr);
1834  
1835  			H_tx_bufadr += DMA_PakSize;
1836  			H_tx_desadr += 16;
1837  		}
1838  		eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[des_num];
1839  		Write_Mem_Des_DD(H_tx_desadr + 0x0C, H_tx_bufadr);
1840  		Write_Mem_Des_DD(H_tx_desadr, TDES_IniVal | EOR_IniVal);
1841  		if (DbgPrn_BufAdr)
1842  			printf("[loop[%d]:%4d][des:%4d][setup_txdes] %08x "
1843  			       "[%08x]\n",
1844  			       eng->run.loop_of_cnt, eng->run.loop_cnt, des_num,
1845  			       H_tx_desadr, H_tx_bufadr);
1846  	}
1847  } // End void setup_des_loop (uint32_t bufnum)
1848  
1849  //------------------------------------------------------------
check_des_header_Tx(MAC_ENGINE * eng,char * type,uint32_t adr,int32_t desnum)1850  char check_des_header_Tx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum)
1851  {
1852  	int timeout = 0;
1853  
1854  	eng->dat.TxDes0DW = Read_Mem_Des_DD(adr);
1855  
1856  	while (HWOwnTx(eng->dat.TxDes0DW)) {
1857  		// we will run again, if transfer has not been completed.
1858  		if ((eng->run.tm_tx_only || eng->run.TM_RxDataEn) &&
1859  		    (++timeout > eng->run.timeout_th)) {
1860  			PRINTF(FP_LOG,
1861  			       "[%sTxDesOwn] Address %08x = %08x "
1862  			       "[Des:%d][loop[%d]:%d]\n",
1863  			       type, adr, eng->dat.TxDes0DW, desnum,
1864  			       eng->run.loop_of_cnt, eng->run.loop_cnt);
1865  			return (FindErr_Des(eng, Des_Flag_TxOwnTimeOut));
1866  		}
1867  
1868  #ifdef Delay_ChkTxOwn
1869  		DELAY(Delay_ChkTxOwn);
1870  #endif
1871  		eng->dat.TxDes0DW = Read_Mem_Des_DD(adr);
1872  	}
1873  
1874  	return(0);
1875  } // End char check_des_header_Tx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum)
1876  
1877  //------------------------------------------------------------
check_des_header_Rx(MAC_ENGINE * eng,char * type,uint32_t adr,int32_t desnum)1878  char check_des_header_Rx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum)
1879  {
1880  #ifdef CheckRxOwn
1881  	int timeout = 0;
1882  
1883  	eng->dat.RxDes0DW = Read_Mem_Des_DD(adr);
1884  
1885  	while (HWOwnRx(eng->dat.RxDes0DW)) {
1886  		// we will run again, if transfer has not been completed.
1887  		if (eng->run.TM_TxDataEn && (++timeout > eng->run.timeout_th)) {
1888  #if 0
1889  			printf("[%sRxDesOwn] Address %08x = %08x "
1890  			       "[Des:%d][loop[%d]:%d]\n",
1891  			       type, adr, eng->dat.RxDes0DW, desnum,
1892  			       eng->run.loop_of_cnt, eng->run.loop_cnt);
1893  #endif
1894  			FindErr_Des(eng, Des_Flag_RxOwnTimeOut);
1895  			return (2);
1896  		}
1897  
1898    #ifdef Delay_ChkRxOwn
1899  		DELAY(Delay_ChkRxOwn);
1900    #endif
1901  		eng->dat.RxDes0DW = Read_Mem_Des_DD(adr);
1902  	};
1903  
1904    #ifdef CheckRxLen
1905  	if ( DbgPrn_FRAME_LEN )
1906  		PRINTF( FP_LOG, "[%sRxDes          ] FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]\n", type, ( eng->dat.FRAME_LEN_Cur + 4 ), desnum, eng->run.loop_of_cnt, eng->run.loop_cnt );
1907  
1908  	if ( ( eng->dat.RxDes0DW & 0x3fff ) != ( eng->dat.FRAME_LEN_Cur + 4 ) ) {
1909  		eng->dat.RxDes3DW = Read_Mem_Des_DD( adr + 12 );
1910  		PRINTF( FP_LOG, "[%sRxDes] Error Frame Length %08x:%08x %08x(%4d/%4d) [Des:%d][loop[%d]:%d]\n",   type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, ( eng->dat.RxDes0DW & 0x3fff ), ( eng->dat.FRAME_LEN_Cur + 4 ), desnum, eng->run.loop_of_cnt, eng->run.loop_cnt );
1911  		FindErr_Des( eng, Des_Flag_FrameLen );
1912  	}
1913    #endif // End CheckRxLen
1914  
1915  	if ( eng->dat.RxDes0DW & RXDES_EM_ALL ) {
1916  		eng->dat.RxDes3DW = Read_Mem_Des_DD( adr + 12 );
1917    #ifdef CheckRxErr
1918  		if ( eng->dat.RxDes0DW & RXDES_EM_RXERR ) {
1919  			PRINTF( FP_LOG, "[%sRxDes] Error RxErr        %08x:%08x %08x            [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt );
1920  			FindErr_Des( eng, Des_Flag_RxErr );
1921  		}
1922    #endif // End CheckRxErr
1923  
1924    #ifdef CheckCRC
1925  		if ( eng->dat.RxDes0DW & RXDES_EM_CRC ) {
1926  			PRINTF( FP_LOG, "[%sRxDes] Error CRC          %08x:%08x %08x            [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt );
1927  			FindErr_Des( eng, Des_Flag_CRC );
1928  		}
1929    #endif // End CheckCRC
1930  
1931    #ifdef CheckFTL
1932  		if ( eng->dat.RxDes0DW & RXDES_EM_FTL ) {
1933  			PRINTF( FP_LOG, "[%sRxDes] Error FTL          %08x:%08x %08x            [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt );
1934  			FindErr_Des( eng, Des_Flag_FTL );
1935  		}
1936    #endif // End CheckFTL
1937  
1938    #ifdef CheckRunt
1939  		if ( eng->dat.RxDes0DW & RXDES_EM_RUNT) {
1940  			PRINTF( FP_LOG, "[%sRxDes] Error Runt         %08x:%08x %08x            [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt );
1941  			FindErr_Des( eng, Des_Flag_Runt );
1942  		}
1943    #endif // End CheckRunt
1944  
1945    #ifdef CheckOddNibble
1946  		if ( eng->dat.RxDes0DW & RXDES_EM_ODD_NB ) {
1947  			PRINTF( FP_LOG, "[%sRxDes] Odd Nibble         %08x:%08x %08x            [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt );
1948  			FindErr_Des( eng, Des_Flag_OddNibble );
1949  		}
1950    #endif // End CheckOddNibble
1951  
1952    #ifdef CheckRxFIFOFull
1953  		if ( eng->dat.RxDes0DW & RXDES_EM_FIFO_FULL ) {
1954  			PRINTF( FP_LOG, "[%sRxDes] Error Rx FIFO Full %08x:%08x %08x            [Des:%d][loop[%d]:%d]\n", type, adr, eng->dat.RxDes0DW, eng->dat.RxDes3DW, desnum, eng->run.loop_of_cnt, eng->run.loop_cnt );
1955  			FindErr_Des( eng, Des_Flag_RxFIFOFull );
1956  		}
1957    #endif // End CheckRxFIFOFull
1958  	}
1959  
1960  #endif // End CheckRxOwn
1961  
1962  	if ( eng->flg.error )
1963  		return(1);
1964  	else
1965  		return(0);
1966  } // End char check_des_header_Rx (MAC_ENGINE *eng, char *type, uint32_t adr, int32_t desnum)
1967  
1968  //------------------------------------------------------------
check_des(MAC_ENGINE * eng,uint32_t bufnum,int checkpoint)1969  char check_des (MAC_ENGINE *eng, uint32_t bufnum, int checkpoint)
1970  {
1971  	int32_t       desnum;
1972  	int8_t       desnum_last;
1973  	uint32_t      H_rx_desadr;
1974  	uint32_t      H_tx_desadr;
1975  	uint32_t      H_tx_bufadr;
1976  	uint32_t      H_rx_bufadr;
1977  #ifdef Delay_DesGap
1978  	uint32_t      dly_cnt = 0;
1979  	uint32_t      dly_max = Delay_CntMaxIncVal;
1980  #endif
1981  	int ret;
1982  
1983  	nt_log_func_name();
1984  
1985  	/* Fire the engine to send and recvice */
1986  	mac_reg_write(eng, 0x1c, 0x00000001); // Rx Poll
1987  	mac_reg_write(eng, 0x18, 0x00000001); // Tx Poll
1988  
1989  #ifndef SelectSimpleDes
1990  	/* base of the descriptors */
1991  	H_tx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Tx);
1992  	H_rx_bufadr = AT_MEMRW_BUF(eng->dat.DMA_Base_Rx);
1993  #endif
1994  	H_rx_desadr = eng->run.rdes_base;
1995  	H_tx_desadr = eng->run.tdes_base;
1996  
1997  #ifdef Delay_DES
1998  	DELAY(Delay_DES);
1999  #endif
2000  
2001  	for (desnum = 0; desnum < eng->dat.Des_Num; desnum++) {
2002  		desnum_last = (desnum == (eng->dat.Des_Num - 1)) ? 1 : 0;
2003  		if ( DbgPrn_BufAdr ) {
2004  			if ( checkpoint )
2005  				printf("[loop[%d]:%4d][des:%4d][check_des  ] %08x %08x [%08x %08x]\n", eng->run.loop_of_cnt, eng->run.loop_cnt, desnum, ( H_tx_desadr ), ( H_rx_desadr ), Read_Mem_Des_DD( H_tx_desadr + 12 ), Read_Mem_Des_DD( H_rx_desadr + 12 ) );
2006  			else
2007  				printf("[loop[%d]:%4d][des:%4d][check_des  ] %08x %08x [%08x %08x]->[%08x %08x]\n", eng->run.loop_of_cnt, eng->run.loop_cnt, desnum, ( H_tx_desadr ), ( H_rx_desadr ), Read_Mem_Des_DD( H_tx_desadr + 12 ), Read_Mem_Des_DD( H_rx_desadr + 12 ), H_tx_bufadr, H_rx_bufadr );
2008  		}
2009  
2010  		//[Delay]--------------------
2011  #ifdef Delay_DesGap
2012  //		if ( dly_cnt++ > 3 ) {
2013  		if ( dly_cnt > Delay_CntMax ) {
2014  //			switch ( rand() % 12 ) {
2015  //				case 1 : dly_max = 00000; break;
2016  //				case 3 : dly_max = 20000; break;
2017  //				case 5 : dly_max = 40000; break;
2018  //				case 7 : dly_max = 60000; break;
2019  //				defaule: dly_max = 70000; break;
2020  //			}
2021  //
2022  //			dly_max += ( rand() % 4 ) * 14321;
2023  //
2024  //			while (dly_cnt < dly_max) {
2025  //				dly_cnt++;
2026  //			}
2027  			DELAY( Delay_DesGap );
2028  			dly_cnt = 0;
2029  		}
2030  		else {
2031  			dly_cnt++;
2032  //			timeout = 0;
2033  //			while (timeout < 50000) {timeout++;};
2034  		}
2035  #endif // End Delay_DesGap
2036  
2037  		//[Check Owner Bit]--------------------
2038  		eng->dat.FRAME_LEN_Cur = eng->dat.FRAME_LEN[desnum];
2039  		if (DbgPrn_FRAME_LEN)
2040  			PRINTF(FP_LOG,
2041  			       "[check_des      ] "
2042  			       "FRAME_LEN_Cur:%08x[Des:%d][loop[%d]:%d]%d\n",
2043  			       eng->dat.FRAME_LEN_Cur, desnum,
2044  			       eng->run.loop_of_cnt, eng->run.loop_cnt,
2045  			       checkpoint);
2046  
2047  		// Check the description of Tx and Rx
2048  		if (eng->run.TM_TxDataEn) {
2049  			ret = check_des_header_Tx(eng, "", H_tx_desadr, desnum);
2050  			if (ret) {
2051  				eng->flg.n_desc_fail = desnum;
2052  				return ret;
2053  			}
2054  		}
2055  		if (eng->run.TM_RxDataEn) {
2056  			ret = check_des_header_Rx(eng, "", H_rx_desadr, desnum);
2057  			if (ret) {
2058  				eng->flg.n_desc_fail = desnum;
2059  				return ret;
2060  
2061  			}
2062  		}
2063  
2064  #ifndef SelectSimpleDes
2065  		if (!checkpoint) {
2066  			// Setting buffer address to description of Tx and Rx on next stage
2067  			if ( eng->run.TM_RxDataEn ) {
2068  				Write_Mem_Des_DD( H_rx_desadr + 0x0C, H_rx_bufadr );
2069  				if ( desnum_last )
2070  					Write_Mem_Des_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal );
2071  				else
2072  					Write_Mem_Des_DD( H_rx_desadr, RDES_IniVal );
2073  
2074  				readl(H_rx_desadr);
2075  				mac_reg_write(eng, 0x1c, 0x00000000); //Rx Poll
2076  				H_rx_bufadr += DMA_PakSize;
2077  			}
2078  			if ( eng->run.TM_TxDataEn ) {
2079  				Write_Mem_Des_DD( H_tx_desadr + 0x0C, H_tx_bufadr );
2080  				if ( desnum_last )
2081  					Write_Mem_Des_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal );
2082  				else
2083  					Write_Mem_Des_DD( H_tx_desadr, TDES_IniVal );
2084  
2085  				readl(H_tx_desadr);
2086  				mac_reg_write(eng, 0x18, 0x00000000); //Tx Poll
2087  				H_tx_bufadr += DMA_PakSize;
2088  			}
2089  		}
2090  #endif // End SelectSimpleDes
2091  
2092  		H_rx_desadr += 16;
2093  		H_tx_desadr += 16;
2094  	} // End for (desnum = 0; desnum < eng->dat.Des_Num; desnum++)
2095  
2096  	return(0);
2097  } // End char check_des (MAC_ENGINE *eng, uint32_t bufnum, int checkpoint)
2098  //#endif
2099  
2100  //------------------------------------------------------------
2101  // Print
2102  //-----------------------------------------------------------
PrintIO_Header(MAC_ENGINE * eng,uint8_t option)2103  void PrintIO_Header (MAC_ENGINE *eng, uint8_t option)
2104  {
2105  	int32_t rx_d, step, tmp;
2106  
2107  	if (eng->run.TM_IOStrength) {
2108  		if (eng->io.drv_upper_bond > 1) {
2109  #ifdef CONFIG_ASPEED_AST2600
2110  			PRINTF(option, "<IO Strength register: [%08x] 0x%08x>",
2111  			       eng->io.mac34_drv_reg.addr,
2112  			       eng->io.mac34_drv_reg.value.w);
2113  #else
2114  			PRINTF(option, "<IO Strength register: [%08x] 0x%08x>",
2115  			       eng->io.mac12_drv_reg.addr,
2116  			       eng->io.mac12_drv_reg.value.w);
2117  #endif
2118  		}
2119  	}
2120  
2121  	if      ( eng->run.speed_sel[ 0 ] ) { PRINTF( option, "\n[1G  ]========================================>\n" ); }
2122  	else if ( eng->run.speed_sel[ 1 ] ) { PRINTF( option, "\n[100M]========================================>\n" ); }
2123  	else                                { PRINTF( option, "\n[10M ]========================================>\n" ); }
2124  
2125  	if ( !(option == FP_LOG) ) {
2126  		step = eng->io.rx_delay_scan.step;
2127  
2128  		PRINTF(option, "\n    ");
2129  		for (rx_d = eng->io.rx_delay_scan.begin; rx_d <= eng->io.rx_delay_scan.end; rx_d += step) {
2130  
2131  			if (rx_d < 0) {
2132  				PRINTF(option, "-" );
2133  			} else {
2134  				PRINTF(option, "+" );
2135  			}
2136  		}
2137  
2138  		PRINTF(option, "\n    ");
2139  		for (rx_d = eng->io.rx_delay_scan.begin; rx_d <= eng->io.rx_delay_scan.end; rx_d += step) {
2140  			tmp = (abs(rx_d) >> 4) & 0xf;
2141  			if (tmp == 0) {
2142  				PRINTF(option, "0" );
2143  			} else {
2144  				PRINTF(option, "%1x", tmp);
2145  			}
2146  		}
2147  
2148  		PRINTF(option, "\n    ");
2149  		for (rx_d = eng->io.rx_delay_scan.begin;
2150  		     rx_d <= eng->io.rx_delay_scan.end; rx_d += step) {
2151  			PRINTF(option, "%1x", (uint32_t)abs(rx_d) & 0xf);
2152  		}
2153  
2154  		PRINTF(option, "\n    ");
2155  		for (rx_d = eng->io.rx_delay_scan.begin; rx_d <= eng->io.rx_delay_scan.end; rx_d += step) {
2156  			if (eng->io.rx_delay_scan.orig == rx_d) {
2157  				PRINTF(option, "|" );
2158  			} else {
2159  				PRINTF(option, " " );
2160  			}
2161  		}
2162  		PRINTF( option, "\n");
2163  	}
2164  }
2165  
2166  //------------------------------------------------------------
PrintIO_LineS(MAC_ENGINE * p_eng,uint8_t option)2167  void PrintIO_LineS(MAC_ENGINE *p_eng, uint8_t option)
2168  {
2169  	if (p_eng->io.tx_delay_scan.orig == p_eng->io.Dly_out_selval) {
2170  		PRINTF( option, "%02x:-", p_eng->io.Dly_out_selval);
2171  	} else {
2172  		PRINTF( option, "%02x: ", p_eng->io.Dly_out_selval);
2173  	}
2174  } // End void PrintIO_LineS (MAC_ENGINE *eng, uint8_t option)
2175  
2176  //------------------------------------------------------------
PrintIO_Line(MAC_ENGINE * p_eng,uint8_t option)2177  void PrintIO_Line(MAC_ENGINE *p_eng, uint8_t option)
2178  {
2179  	if ((p_eng->io.Dly_in_selval == p_eng->io.rx_delay_scan.orig) &&
2180  	    (p_eng->io.Dly_out_selval == p_eng->io.tx_delay_scan.orig)) {
2181  		if (1 == p_eng->io.result) {
2182  			PRINTF(option, "X");
2183  		} else if (2 == p_eng->io.result) {
2184  			PRINTF(option, "*");
2185  		} else {
2186  			PRINTF(option, "O");
2187  		}
2188  	} else {
2189  		if (1 == p_eng->io.result) {
2190  			PRINTF(option, "x");
2191  		} else if (2 == p_eng->io.result) {
2192  			PRINTF(option, ".");
2193  		} else {
2194  			PRINTF(option, "o");
2195  		}
2196  	}
2197  }
2198  
2199  //------------------------------------------------------------
2200  // main
2201  //------------------------------------------------------------
2202  
2203  //------------------------------------------------------------
TestingSetup(MAC_ENGINE * eng)2204  void TestingSetup (MAC_ENGINE *eng)
2205  {
2206  	nt_log_func_name();
2207  
2208  	//[Setup]--------------------
2209  	setup_framesize( eng );
2210  	setup_buf( eng );
2211  }
2212  
2213  //------------------------------------------------------------
2214  // Return 1 ==> fail
2215  // Return 0 ==> PASS
2216  //------------------------------------------------------------
TestingLoop(MAC_ENGINE * eng,uint32_t loop_checknum)2217  char TestingLoop (MAC_ENGINE *eng, uint32_t loop_checknum)
2218  {
2219  	char       checkprd;
2220  	char       looplast;
2221  	char       checken;
2222  	int ret;
2223  
2224  	nt_log_func_name();
2225  
2226  	if (DbgPrn_DumpMACCnt)
2227  		dump_mac_ROreg(eng);
2228  
2229  	//[Setup]--------------------
2230  	eng->run.loop_cnt = 0;
2231  	checkprd = 0;
2232  	checken  = 0;
2233  	looplast = 0;
2234  
2235  
2236  	setup_des(eng, 0);
2237  
2238  	if ( eng->run.TM_WaitStart ) {
2239  		printf("Press any key to start...\n");
2240  		GET_CAHR();
2241  	}
2242  
2243  
2244  	while ( ( eng->run.loop_cnt < eng->run.loop_max ) || eng->arg.loop_inf ) {
2245  		looplast = !eng->arg.loop_inf && ( eng->run.loop_cnt == eng->run.loop_max - 1 );
2246  
2247  #ifdef CheckRxBuf
2248  		if (!eng->run.tm_tx_only)
2249  			checkprd = ((eng->run.loop_cnt % loop_checknum) == (loop_checknum - 1));
2250  		checken = looplast | checkprd;
2251  #endif
2252  
2253  		if (DbgPrn_BufAdr) {
2254  			printf("for start ======> [%d]%d/%d(%d) looplast:%d "
2255  			       "checkprd:%d checken:%d\n",
2256  			       eng->run.loop_of_cnt, eng->run.loop_cnt,
2257  			       eng->run.loop_max, eng->arg.loop_inf,
2258  			       looplast, checkprd, checken);
2259  			debug_pause();
2260  		}
2261  
2262  
2263  		if (eng->run.TM_RxDataEn)
2264  			eng->dat.DMA_Base_Tx = eng->dat.DMA_Base_Rx;
2265  
2266  		eng->dat.DMA_Base_Rx =
2267  		    ZeroCopy_OFFSET + GET_DMA_BASE(eng, eng->run.loop_cnt + 1);
2268  		//[Check DES]--------------------
2269  		ret = check_des(eng, eng->run.loop_cnt, checken);
2270  		if (ret) {
2271  			//descriptor error
2272  			eng->dat.Des_Num = eng->flg.n_desc_fail + 1;
2273  #ifdef CheckRxBuf
2274  			if (checkprd)
2275  				check_buf(eng, loop_checknum);
2276  			else
2277  				check_buf(eng, (eng->run.loop_max % loop_checknum));
2278  			eng->dat.Des_Num = eng->dat.Des_Num_Org;
2279  #endif
2280  
2281  			if (DbgPrn_DumpMACCnt)
2282  				dump_mac_ROreg(eng);
2283  
2284  			return ret;
2285  		}
2286  
2287  		//[Check Buf]--------------------
2288  		if (eng->run.TM_RxDataEn && checken) {
2289  			if (checkprd) {
2290  #ifdef Enable_ShowBW
2291  				printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused);
2292  				PRINTF( FP_LOG, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused );
2293  #endif
2294  
2295  #ifdef CheckRxBuf
2296  				if (check_buf(eng, loop_checknum))
2297  					return(1);
2298  #endif
2299  			} else {
2300  #ifdef Enable_ShowBW
2301  				printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (eng->run.loop_max % loop_checknum), ((double)(eng->run.loop_max % loop_checknum) * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused);
2302  				PRINTF( FP_LOG, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (eng->run.loop_max % loop_checknum), ((double)(eng->run.loop_max % loop_checknum) * (double)eng->dat.Total_frame_len * 8.0) / ((double)eng->timeused * 1000000.0), eng->timeused );
2303  #endif
2304  
2305  #ifdef CheckRxBuf
2306  				if (check_buf(eng, (eng->run.loop_max % loop_checknum)))
2307  					return(1);
2308  #endif
2309  			} // End if ( checkprd )
2310  
2311  #ifndef SelectSimpleDes
2312  			if (!looplast)
2313  				setup_des_loop(eng, eng->run.loop_cnt);
2314  #endif
2315  
2316  #ifdef Enable_ShowBW
2317  			timeold = clock();
2318  #endif
2319  		} // End if ( eng->run.TM_RxDataEn && checken )
2320  
2321  #ifdef SelectSimpleDes
2322  		if (!looplast)
2323  			setup_des_loop(eng, eng->run.loop_cnt);
2324  #endif
2325  
2326  		if ( eng->arg.loop_inf )
2327  			printf("===============> Loop[%d]: %d  \r", eng->run.loop_of_cnt, eng->run.loop_cnt);
2328  		else if ( eng->arg.test_mode == 0 ) {
2329  			if ( !( DbgPrn_BufAdr || eng->run.delay_margin ) )
2330  				printf(" [%d]%d                        \r", eng->run.loop_of_cnt, eng->run.loop_cnt);
2331  		}
2332  
2333  		if (DbgPrn_BufAdr) {
2334  			printf("for end   ======> [%d]%d/%d(%d)\n",
2335  			       eng->run.loop_of_cnt, eng->run.loop_cnt,
2336  			       eng->run.loop_max, eng->arg.loop_inf);
2337  			debug_pause();
2338  		}
2339  
2340  		if (eng->run.loop_cnt >= 0x7fffffff) {
2341  			debug("loop counter wrapped around\n");
2342  			eng->run.loop_cnt = 0;
2343  			eng->run.loop_of_cnt++;
2344  		} else
2345  			eng->run.loop_cnt++;
2346  	} // End while ( ( eng->run.loop_cnt < eng->run.loop_max ) || eng->arg.loop_inf )
2347  
2348  	eng->flg.all_fail = 0;
2349  	return(0);
2350  } // End char TestingLoop (MAC_ENGINE *eng, uint32_t loop_checknum)
2351