1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver
4 //
5 // Copyright (C) 2021 Renesas Electronics Corp.
6 // Copyright (C) 2019 Chris Brandt.
7 //
8
9 #include <linux/clk.h>
10 #include <linux/dmaengine.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16 #include <sound/soc.h>
17
18 /* REGISTER OFFSET */
19 #define SSICR 0x000
20 #define SSISR 0x004
21 #define SSIFCR 0x010
22 #define SSIFSR 0x014
23 #define SSIFTDR 0x018
24 #define SSIFRDR 0x01c
25 #define SSIOFR 0x020
26 #define SSISCR 0x024
27
28 /* SSI REGISTER BITS */
29 #define SSICR_DWL(x) (((x) & 0x7) << 19)
30 #define SSICR_SWL(x) (((x) & 0x7) << 16)
31
32 #define SSICR_CKS BIT(30)
33 #define SSICR_TUIEN BIT(29)
34 #define SSICR_TOIEN BIT(28)
35 #define SSICR_RUIEN BIT(27)
36 #define SSICR_ROIEN BIT(26)
37 #define SSICR_MST BIT(14)
38 #define SSICR_BCKP BIT(13)
39 #define SSICR_LRCKP BIT(12)
40 #define SSICR_CKDV(x) (((x) & 0xf) << 4)
41 #define SSICR_TEN BIT(1)
42 #define SSICR_REN BIT(0)
43
44 #define SSISR_TUIRQ BIT(29)
45 #define SSISR_TOIRQ BIT(28)
46 #define SSISR_RUIRQ BIT(27)
47 #define SSISR_ROIRQ BIT(26)
48 #define SSISR_IIRQ BIT(25)
49
50 #define SSIFCR_AUCKE BIT(31)
51 #define SSIFCR_SSIRST BIT(16)
52 #define SSIFCR_TIE BIT(3)
53 #define SSIFCR_RIE BIT(2)
54 #define SSIFCR_TFRST BIT(1)
55 #define SSIFCR_RFRST BIT(0)
56
57 #define SSIFSR_TDC_MASK 0x3f
58 #define SSIFSR_TDC_SHIFT 24
59 #define SSIFSR_RDC_MASK 0x3f
60 #define SSIFSR_RDC_SHIFT 8
61
62 #define SSIFSR_TDE BIT(16)
63 #define SSIFSR_RDF BIT(0)
64
65 #define SSIOFR_LRCONT BIT(8)
66
67 #define SSISCR_TDES(x) (((x) & 0x1f) << 8)
68 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0)
69
70 /* Pre allocated buffers sizes */
71 #define PREALLOC_BUFFER (SZ_32K)
72 #define PREALLOC_BUFFER_MAX (SZ_32K)
73
74 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-44.1kHz */
75 #define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE
76 #define SSI_CHAN_MIN 2
77 #define SSI_CHAN_MAX 2
78 #define SSI_FIFO_DEPTH 32
79
80 struct rz_ssi_priv;
81
82 struct rz_ssi_stream {
83 struct rz_ssi_priv *priv;
84 struct snd_pcm_substream *substream;
85 int fifo_sample_size; /* sample capacity of SSI FIFO */
86 int dma_buffer_pos; /* The address for the next DMA descriptor */
87 int period_counter; /* for keeping track of periods transferred */
88 int sample_width;
89 int buffer_pos; /* current frame position in the buffer */
90 int running; /* 0=stopped, 1=running */
91
92 int uerr_num;
93 int oerr_num;
94
95 struct dma_chan *dma_ch;
96
97 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm);
98 };
99
100 struct rz_ssi_priv {
101 void __iomem *base;
102 struct platform_device *pdev;
103 struct reset_control *rstc;
104 struct device *dev;
105 struct clk *sfr_clk;
106 struct clk *clk;
107
108 phys_addr_t phys;
109 int irq_int;
110 int irq_tx;
111 int irq_rx;
112 int irq_rt;
113
114 spinlock_t lock;
115
116 /*
117 * The SSI supports full-duplex transmission and reception.
118 * However, if an error occurs, channel reset (both transmission
119 * and reception reset) is required.
120 * So it is better to use as half-duplex (playing and recording
121 * should be done on separate channels).
122 */
123 struct rz_ssi_stream playback;
124 struct rz_ssi_stream capture;
125
126 /* clock */
127 unsigned long audio_mck;
128 unsigned long audio_clk_1;
129 unsigned long audio_clk_2;
130
131 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */
132 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */
133 bool dma_rt;
134 };
135
136 static void rz_ssi_dma_complete(void *data);
137
rz_ssi_reg_writel(struct rz_ssi_priv * priv,uint reg,u32 data)138 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data)
139 {
140 writel(data, (priv->base + reg));
141 }
142
rz_ssi_reg_readl(struct rz_ssi_priv * priv,uint reg)143 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg)
144 {
145 return readl(priv->base + reg);
146 }
147
rz_ssi_reg_mask_setl(struct rz_ssi_priv * priv,uint reg,u32 bclr,u32 bset)148 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg,
149 u32 bclr, u32 bset)
150 {
151 u32 val;
152
153 val = readl(priv->base + reg);
154 val = (val & ~bclr) | bset;
155 writel(val, (priv->base + reg));
156 }
157
158 static inline struct snd_soc_dai *
rz_ssi_get_dai(struct snd_pcm_substream * substream)159 rz_ssi_get_dai(struct snd_pcm_substream *substream)
160 {
161 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
162
163 return asoc_rtd_to_cpu(rtd, 0);
164 }
165
rz_ssi_stream_is_play(struct rz_ssi_priv * ssi,struct snd_pcm_substream * substream)166 static inline bool rz_ssi_stream_is_play(struct rz_ssi_priv *ssi,
167 struct snd_pcm_substream *substream)
168 {
169 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
170 }
171
172 static inline struct rz_ssi_stream *
rz_ssi_stream_get(struct rz_ssi_priv * ssi,struct snd_pcm_substream * substream)173 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream)
174 {
175 struct rz_ssi_stream *stream = &ssi->playback;
176
177 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
178 stream = &ssi->capture;
179
180 return stream;
181 }
182
rz_ssi_is_dma_enabled(struct rz_ssi_priv * ssi)183 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi)
184 {
185 return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch));
186 }
187
rz_ssi_set_substream(struct rz_ssi_stream * strm,struct snd_pcm_substream * substream)188 static void rz_ssi_set_substream(struct rz_ssi_stream *strm,
189 struct snd_pcm_substream *substream)
190 {
191 struct rz_ssi_priv *ssi = strm->priv;
192 unsigned long flags;
193
194 spin_lock_irqsave(&ssi->lock, flags);
195 strm->substream = substream;
196 spin_unlock_irqrestore(&ssi->lock, flags);
197 }
198
rz_ssi_stream_is_valid(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)199 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi,
200 struct rz_ssi_stream *strm)
201 {
202 unsigned long flags;
203 bool ret;
204
205 spin_lock_irqsave(&ssi->lock, flags);
206 ret = strm->substream && strm->substream->runtime;
207 spin_unlock_irqrestore(&ssi->lock, flags);
208
209 return ret;
210 }
211
rz_ssi_stream_init(struct rz_ssi_stream * strm,struct snd_pcm_substream * substream)212 static void rz_ssi_stream_init(struct rz_ssi_stream *strm,
213 struct snd_pcm_substream *substream)
214 {
215 struct snd_pcm_runtime *runtime = substream->runtime;
216
217 rz_ssi_set_substream(strm, substream);
218 strm->sample_width = samples_to_bytes(runtime, 1);
219 strm->dma_buffer_pos = 0;
220 strm->period_counter = 0;
221 strm->buffer_pos = 0;
222
223 strm->oerr_num = 0;
224 strm->uerr_num = 0;
225 strm->running = 0;
226
227 /* fifo init */
228 strm->fifo_sample_size = SSI_FIFO_DEPTH;
229 }
230
rz_ssi_stream_quit(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)231 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi,
232 struct rz_ssi_stream *strm)
233 {
234 struct snd_soc_dai *dai = rz_ssi_get_dai(strm->substream);
235
236 rz_ssi_set_substream(strm, NULL);
237
238 if (strm->oerr_num > 0)
239 dev_info(dai->dev, "overrun = %d\n", strm->oerr_num);
240
241 if (strm->uerr_num > 0)
242 dev_info(dai->dev, "underrun = %d\n", strm->uerr_num);
243 }
244
rz_ssi_clk_setup(struct rz_ssi_priv * ssi,unsigned int rate,unsigned int channels)245 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate,
246 unsigned int channels)
247 {
248 static u8 ckdv[] = { 1, 2, 4, 8, 16, 32, 64, 128, 6, 12, 24, 48, 96 };
249 unsigned int channel_bits = 32; /* System Word Length */
250 unsigned long bclk_rate = rate * channels * channel_bits;
251 unsigned int div;
252 unsigned int i;
253 u32 ssicr = 0;
254 u32 clk_ckdv;
255
256 /* Clear AUCKE so we can set MST */
257 rz_ssi_reg_writel(ssi, SSIFCR, 0);
258
259 /* Continue to output LRCK pin even when idle */
260 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT);
261 if (ssi->audio_clk_1 && ssi->audio_clk_2) {
262 if (ssi->audio_clk_1 % bclk_rate)
263 ssi->audio_mck = ssi->audio_clk_2;
264 else
265 ssi->audio_mck = ssi->audio_clk_1;
266 }
267
268 /* Clock setting */
269 ssicr |= SSICR_MST;
270 if (ssi->audio_mck == ssi->audio_clk_1)
271 ssicr |= SSICR_CKS;
272 if (ssi->bckp_rise)
273 ssicr |= SSICR_BCKP;
274 if (ssi->lrckp_fsync_fall)
275 ssicr |= SSICR_LRCKP;
276
277 /* Determine the clock divider */
278 clk_ckdv = 0;
279 div = ssi->audio_mck / bclk_rate;
280 /* try to find an match */
281 for (i = 0; i < ARRAY_SIZE(ckdv); i++) {
282 if (ckdv[i] == div) {
283 clk_ckdv = i;
284 break;
285 }
286 }
287
288 if (i == ARRAY_SIZE(ckdv)) {
289 dev_err(ssi->dev, "Rate not divisible by audio clock source\n");
290 return -EINVAL;
291 }
292
293 /*
294 * DWL: Data Word Length = 16 bits
295 * SWL: System Word Length = 32 bits
296 */
297 ssicr |= SSICR_CKDV(clk_ckdv);
298 ssicr |= SSICR_DWL(1) | SSICR_SWL(3);
299 rz_ssi_reg_writel(ssi, SSICR, ssicr);
300 rz_ssi_reg_writel(ssi, SSIFCR,
301 (SSIFCR_AUCKE | SSIFCR_TFRST | SSIFCR_RFRST));
302
303 return 0;
304 }
305
rz_ssi_start(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)306 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
307 {
308 bool is_play = rz_ssi_stream_is_play(ssi, strm->substream);
309 u32 ssicr, ssifcr;
310
311 ssicr = rz_ssi_reg_readl(ssi, SSICR);
312 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR) & ~0xF;
313
314 /* FIFO interrupt thresholds */
315 if (rz_ssi_is_dma_enabled(ssi))
316 rz_ssi_reg_writel(ssi, SSISCR, 0);
317 else
318 rz_ssi_reg_writel(ssi, SSISCR,
319 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) |
320 SSISCR_RDFS(0));
321
322 /* enable IRQ */
323 if (is_play) {
324 ssicr |= SSICR_TUIEN | SSICR_TOIEN;
325 ssifcr |= SSIFCR_TIE | SSIFCR_RFRST;
326 } else {
327 ssicr |= SSICR_RUIEN | SSICR_ROIEN;
328 ssifcr |= SSIFCR_RIE | SSIFCR_TFRST;
329 }
330
331 rz_ssi_reg_writel(ssi, SSICR, ssicr);
332 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr);
333
334 /* Clear all error flags */
335 rz_ssi_reg_mask_setl(ssi, SSISR,
336 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
337 SSISR_RUIRQ), 0);
338
339 strm->running = 1;
340 ssicr |= is_play ? SSICR_TEN : SSICR_REN;
341 rz_ssi_reg_writel(ssi, SSICR, ssicr);
342
343 return 0;
344 }
345
rz_ssi_stop(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)346 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
347 {
348 int timeout;
349
350 strm->running = 0;
351
352 /* Disable TX/RX */
353 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0);
354
355 /* Cancel all remaining DMA transactions */
356 if (rz_ssi_is_dma_enabled(ssi))
357 dmaengine_terminate_async(strm->dma_ch);
358
359 /* Disable irqs */
360 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN |
361 SSICR_RUIEN | SSICR_ROIEN, 0);
362 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0);
363
364 /* Clear all error flags */
365 rz_ssi_reg_mask_setl(ssi, SSISR,
366 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
367 SSISR_RUIRQ), 0);
368
369 /* Wait for idle */
370 timeout = 100;
371 while (--timeout) {
372 if (rz_ssi_reg_readl(ssi, SSISR) & SSISR_IIRQ)
373 break;
374 udelay(1);
375 }
376
377 if (!timeout)
378 dev_info(ssi->dev, "timeout waiting for SSI idle\n");
379
380 /* Hold FIFOs in reset */
381 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0,
382 SSIFCR_TFRST | SSIFCR_RFRST);
383
384 return 0;
385 }
386
rz_ssi_pointer_update(struct rz_ssi_stream * strm,int frames)387 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames)
388 {
389 struct snd_pcm_substream *substream = strm->substream;
390 struct snd_pcm_runtime *runtime;
391 int current_period;
392
393 if (!strm->running || !substream || !substream->runtime)
394 return;
395
396 runtime = substream->runtime;
397 strm->buffer_pos += frames;
398 WARN_ON(strm->buffer_pos > runtime->buffer_size);
399
400 /* ring buffer */
401 if (strm->buffer_pos == runtime->buffer_size)
402 strm->buffer_pos = 0;
403
404 current_period = strm->buffer_pos / runtime->period_size;
405 if (strm->period_counter != current_period) {
406 snd_pcm_period_elapsed(strm->substream);
407 strm->period_counter = current_period;
408 }
409 }
410
rz_ssi_pio_recv(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)411 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
412 {
413 struct snd_pcm_substream *substream = strm->substream;
414 struct snd_pcm_runtime *runtime;
415 u16 *buf;
416 int fifo_samples;
417 int frames_left;
418 int samples;
419 int i;
420
421 if (!rz_ssi_stream_is_valid(ssi, strm))
422 return -EINVAL;
423
424 runtime = substream->runtime;
425
426 do {
427 /* frames left in this period */
428 frames_left = runtime->period_size -
429 (strm->buffer_pos % runtime->period_size);
430 if (!frames_left)
431 frames_left = runtime->period_size;
432
433 /* Samples in RX FIFO */
434 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >>
435 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK;
436
437 /* Only read full frames at a time */
438 samples = 0;
439 while (frames_left && (fifo_samples >= runtime->channels)) {
440 samples += runtime->channels;
441 fifo_samples -= runtime->channels;
442 frames_left--;
443 }
444
445 /* not enough samples yet */
446 if (!samples)
447 break;
448
449 /* calculate new buffer index */
450 buf = (u16 *)runtime->dma_area;
451 buf += strm->buffer_pos * runtime->channels;
452
453 /* Note, only supports 16-bit samples */
454 for (i = 0; i < samples; i++)
455 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16);
456
457 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
458 rz_ssi_pointer_update(strm, samples / runtime->channels);
459 } while (!frames_left && fifo_samples >= runtime->channels);
460
461 return 0;
462 }
463
rz_ssi_pio_send(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)464 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
465 {
466 struct snd_pcm_substream *substream = strm->substream;
467 struct snd_pcm_runtime *runtime = substream->runtime;
468 int sample_space;
469 int samples = 0;
470 int frames_left;
471 int i;
472 u32 ssifsr;
473 u16 *buf;
474
475 if (!rz_ssi_stream_is_valid(ssi, strm))
476 return -EINVAL;
477
478 /* frames left in this period */
479 frames_left = runtime->period_size - (strm->buffer_pos %
480 runtime->period_size);
481 if (frames_left == 0)
482 frames_left = runtime->period_size;
483
484 sample_space = strm->fifo_sample_size;
485 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR);
486 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK;
487 if (sample_space < 0)
488 return -EINVAL;
489
490 /* Only add full frames at a time */
491 while (frames_left && (sample_space >= runtime->channels)) {
492 samples += runtime->channels;
493 sample_space -= runtime->channels;
494 frames_left--;
495 }
496
497 /* no space to send anything right now */
498 if (samples == 0)
499 return 0;
500
501 /* calculate new buffer index */
502 buf = (u16 *)(runtime->dma_area);
503 buf += strm->buffer_pos * runtime->channels;
504
505 /* Note, only supports 16-bit samples */
506 for (i = 0; i < samples; i++)
507 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16));
508
509 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0);
510 rz_ssi_pointer_update(strm, samples / runtime->channels);
511
512 return 0;
513 }
514
rz_ssi_interrupt(int irq,void * data)515 static irqreturn_t rz_ssi_interrupt(int irq, void *data)
516 {
517 struct rz_ssi_stream *strm = NULL;
518 struct rz_ssi_priv *ssi = data;
519 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR);
520
521 if (ssi->playback.substream)
522 strm = &ssi->playback;
523 else if (ssi->capture.substream)
524 strm = &ssi->capture;
525 else
526 return IRQ_HANDLED; /* Left over TX/RX interrupt */
527
528 if (irq == ssi->irq_int) { /* error or idle */
529 if (ssisr & SSISR_TUIRQ)
530 strm->uerr_num++;
531 if (ssisr & SSISR_TOIRQ)
532 strm->oerr_num++;
533 if (ssisr & SSISR_RUIRQ)
534 strm->uerr_num++;
535 if (ssisr & SSISR_ROIRQ)
536 strm->oerr_num++;
537
538 if (ssisr & (SSISR_TUIRQ | SSISR_TOIRQ | SSISR_RUIRQ |
539 SSISR_ROIRQ)) {
540 /* Error handling */
541 /* You must reset (stop/restart) after each interrupt */
542 rz_ssi_stop(ssi, strm);
543
544 /* Clear all flags */
545 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ |
546 SSISR_TUIRQ | SSISR_ROIRQ |
547 SSISR_RUIRQ, 0);
548
549 /* Add/remove more data */
550 strm->transfer(ssi, strm);
551
552 /* Resume */
553 rz_ssi_start(ssi, strm);
554 }
555 }
556
557 if (!strm->running)
558 return IRQ_HANDLED;
559
560 /* tx data empty */
561 if (irq == ssi->irq_tx)
562 strm->transfer(ssi, &ssi->playback);
563
564 /* rx data full */
565 if (irq == ssi->irq_rx) {
566 strm->transfer(ssi, &ssi->capture);
567 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
568 }
569
570 if (irq == ssi->irq_rt) {
571 struct snd_pcm_substream *substream = strm->substream;
572
573 if (rz_ssi_stream_is_play(ssi, substream)) {
574 strm->transfer(ssi, &ssi->playback);
575 } else {
576 strm->transfer(ssi, &ssi->capture);
577 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
578 }
579 }
580
581 return IRQ_HANDLED;
582 }
583
rz_ssi_dma_slave_config(struct rz_ssi_priv * ssi,struct dma_chan * dma_ch,bool is_play)584 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi,
585 struct dma_chan *dma_ch, bool is_play)
586 {
587 struct dma_slave_config cfg;
588
589 memset(&cfg, 0, sizeof(cfg));
590
591 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
592 cfg.dst_addr = ssi->phys + SSIFTDR;
593 cfg.src_addr = ssi->phys + SSIFRDR;
594 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
595 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
596
597 return dmaengine_slave_config(dma_ch, &cfg);
598 }
599
rz_ssi_dma_transfer(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)600 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi,
601 struct rz_ssi_stream *strm)
602 {
603 struct snd_pcm_substream *substream = strm->substream;
604 struct dma_async_tx_descriptor *desc;
605 struct snd_pcm_runtime *runtime;
606 enum dma_transfer_direction dir;
607 u32 dma_paddr, dma_size;
608 int amount;
609
610 if (!rz_ssi_stream_is_valid(ssi, strm))
611 return -EINVAL;
612
613 runtime = substream->runtime;
614 if (runtime->state == SNDRV_PCM_STATE_DRAINING)
615 /*
616 * Stream is ending, so do not queue up any more DMA
617 * transfers otherwise we play partial sound clips
618 * because we can't shut off the DMA quick enough.
619 */
620 return 0;
621
622 dir = rz_ssi_stream_is_play(ssi, substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
623
624 /* Always transfer 1 period */
625 amount = runtime->period_size;
626
627 /* DMA physical address and size */
628 dma_paddr = runtime->dma_addr + frames_to_bytes(runtime,
629 strm->dma_buffer_pos);
630 dma_size = frames_to_bytes(runtime, amount);
631 desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size,
632 dir,
633 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
634 if (!desc) {
635 dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n");
636 return -ENOMEM;
637 }
638
639 desc->callback = rz_ssi_dma_complete;
640 desc->callback_param = strm;
641
642 if (dmaengine_submit(desc) < 0) {
643 dev_err(ssi->dev, "dmaengine_submit() fail\n");
644 return -EIO;
645 }
646
647 /* Update DMA pointer */
648 strm->dma_buffer_pos += amount;
649 if (strm->dma_buffer_pos >= runtime->buffer_size)
650 strm->dma_buffer_pos = 0;
651
652 /* Start DMA */
653 dma_async_issue_pending(strm->dma_ch);
654
655 return 0;
656 }
657
rz_ssi_dma_complete(void * data)658 static void rz_ssi_dma_complete(void *data)
659 {
660 struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data;
661
662 if (!strm->running || !strm->substream || !strm->substream->runtime)
663 return;
664
665 /* Note that next DMA transaction has probably already started */
666 rz_ssi_pointer_update(strm, strm->substream->runtime->period_size);
667
668 /* Queue up another DMA transaction */
669 rz_ssi_dma_transfer(strm->priv, strm);
670 }
671
rz_ssi_release_dma_channels(struct rz_ssi_priv * ssi)672 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi)
673 {
674 if (ssi->playback.dma_ch) {
675 dma_release_channel(ssi->playback.dma_ch);
676 ssi->playback.dma_ch = NULL;
677 if (ssi->dma_rt)
678 ssi->dma_rt = false;
679 }
680
681 if (ssi->capture.dma_ch) {
682 dma_release_channel(ssi->capture.dma_ch);
683 ssi->capture.dma_ch = NULL;
684 }
685 }
686
rz_ssi_dma_request(struct rz_ssi_priv * ssi,struct device * dev)687 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev)
688 {
689 ssi->playback.dma_ch = dma_request_chan(dev, "tx");
690 if (IS_ERR(ssi->playback.dma_ch))
691 ssi->playback.dma_ch = NULL;
692
693 ssi->capture.dma_ch = dma_request_chan(dev, "rx");
694 if (IS_ERR(ssi->capture.dma_ch))
695 ssi->capture.dma_ch = NULL;
696
697 if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) {
698 ssi->playback.dma_ch = dma_request_chan(dev, "rt");
699 if (IS_ERR(ssi->playback.dma_ch)) {
700 ssi->playback.dma_ch = NULL;
701 goto no_dma;
702 }
703
704 ssi->dma_rt = true;
705 }
706
707 if (!rz_ssi_is_dma_enabled(ssi))
708 goto no_dma;
709
710 if (ssi->playback.dma_ch &&
711 (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0))
712 goto no_dma;
713
714 if (ssi->capture.dma_ch &&
715 (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0))
716 goto no_dma;
717
718 return 0;
719
720 no_dma:
721 rz_ssi_release_dma_channels(ssi);
722
723 return -ENODEV;
724 }
725
rz_ssi_dai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)726 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
727 struct snd_soc_dai *dai)
728 {
729 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
730 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
731 int ret = 0, i, num_transfer = 1;
732
733 switch (cmd) {
734 case SNDRV_PCM_TRIGGER_START:
735 /* Soft Reset */
736 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST);
737 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0);
738 udelay(5);
739
740 rz_ssi_stream_init(strm, substream);
741
742 if (ssi->dma_rt) {
743 bool is_playback;
744
745 is_playback = rz_ssi_stream_is_play(ssi, substream);
746 ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch,
747 is_playback);
748 /* Fallback to pio */
749 if (ret < 0) {
750 ssi->playback.transfer = rz_ssi_pio_send;
751 ssi->capture.transfer = rz_ssi_pio_recv;
752 rz_ssi_release_dma_channels(ssi);
753 }
754 }
755
756 /* For DMA, queue up multiple DMA descriptors */
757 if (rz_ssi_is_dma_enabled(ssi))
758 num_transfer = 4;
759
760 for (i = 0; i < num_transfer; i++) {
761 ret = strm->transfer(ssi, strm);
762 if (ret)
763 goto done;
764 }
765
766 ret = rz_ssi_start(ssi, strm);
767 break;
768 case SNDRV_PCM_TRIGGER_STOP:
769 rz_ssi_stop(ssi, strm);
770 rz_ssi_stream_quit(ssi, strm);
771 break;
772 }
773
774 done:
775 return ret;
776 }
777
rz_ssi_dai_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)778 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
779 {
780 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
781
782 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
783 case SND_SOC_DAIFMT_BP_FP:
784 break;
785 default:
786 dev_err(ssi->dev, "Codec should be clk and frame consumer\n");
787 return -EINVAL;
788 }
789
790 /*
791 * set clock polarity
792 *
793 * "normal" BCLK = Signal is available at rising edge of BCLK
794 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge
795 */
796 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
797 case SND_SOC_DAIFMT_NB_NF:
798 ssi->bckp_rise = false;
799 ssi->lrckp_fsync_fall = false;
800 break;
801 case SND_SOC_DAIFMT_NB_IF:
802 ssi->bckp_rise = false;
803 ssi->lrckp_fsync_fall = true;
804 break;
805 case SND_SOC_DAIFMT_IB_NF:
806 ssi->bckp_rise = true;
807 ssi->lrckp_fsync_fall = false;
808 break;
809 case SND_SOC_DAIFMT_IB_IF:
810 ssi->bckp_rise = true;
811 ssi->lrckp_fsync_fall = true;
812 break;
813 default:
814 return -EINVAL;
815 }
816
817 /* only i2s support */
818 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
819 case SND_SOC_DAIFMT_I2S:
820 break;
821 default:
822 dev_err(ssi->dev, "Only I2S mode is supported.\n");
823 return -EINVAL;
824 }
825
826 return 0;
827 }
828
rz_ssi_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)829 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream,
830 struct snd_pcm_hw_params *params,
831 struct snd_soc_dai *dai)
832 {
833 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
834 unsigned int sample_bits = hw_param_interval(params,
835 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
836 unsigned int channels = params_channels(params);
837
838 if (sample_bits != 16) {
839 dev_err(ssi->dev, "Unsupported sample width: %d\n",
840 sample_bits);
841 return -EINVAL;
842 }
843
844 if (channels != 2) {
845 dev_err(ssi->dev, "Number of channels not matched: %d\n",
846 channels);
847 return -EINVAL;
848 }
849
850 return rz_ssi_clk_setup(ssi, params_rate(params),
851 params_channels(params));
852 }
853
854 static const struct snd_soc_dai_ops rz_ssi_dai_ops = {
855 .trigger = rz_ssi_dai_trigger,
856 .set_fmt = rz_ssi_dai_set_fmt,
857 .hw_params = rz_ssi_dai_hw_params,
858 };
859
860 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = {
861 .info = SNDRV_PCM_INFO_INTERLEAVED |
862 SNDRV_PCM_INFO_MMAP |
863 SNDRV_PCM_INFO_MMAP_VALID,
864 .buffer_bytes_max = PREALLOC_BUFFER,
865 .period_bytes_min = 32,
866 .period_bytes_max = 8192,
867 .channels_min = SSI_CHAN_MIN,
868 .channels_max = SSI_CHAN_MAX,
869 .periods_min = 1,
870 .periods_max = 32,
871 .fifo_size = 32 * 2,
872 };
873
rz_ssi_pcm_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)874 static int rz_ssi_pcm_open(struct snd_soc_component *component,
875 struct snd_pcm_substream *substream)
876 {
877 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware);
878
879 return snd_pcm_hw_constraint_integer(substream->runtime,
880 SNDRV_PCM_HW_PARAM_PERIODS);
881 }
882
rz_ssi_pcm_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)883 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component,
884 struct snd_pcm_substream *substream)
885 {
886 struct snd_soc_dai *dai = rz_ssi_get_dai(substream);
887 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
888 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
889
890 return strm->buffer_pos;
891 }
892
rz_ssi_pcm_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)893 static int rz_ssi_pcm_new(struct snd_soc_component *component,
894 struct snd_soc_pcm_runtime *rtd)
895 {
896 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
897 rtd->card->snd_card->dev,
898 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
899 return 0;
900 }
901
902 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = {
903 {
904 .name = "rz-ssi-dai",
905 .playback = {
906 .rates = SSI_RATES,
907 .formats = SSI_FMTS,
908 .channels_min = SSI_CHAN_MIN,
909 .channels_max = SSI_CHAN_MAX,
910 },
911 .capture = {
912 .rates = SSI_RATES,
913 .formats = SSI_FMTS,
914 .channels_min = SSI_CHAN_MIN,
915 .channels_max = SSI_CHAN_MAX,
916 },
917 .ops = &rz_ssi_dai_ops,
918 },
919 };
920
921 static const struct snd_soc_component_driver rz_ssi_soc_component = {
922 .name = "rz-ssi",
923 .open = rz_ssi_pcm_open,
924 .pointer = rz_ssi_pcm_pointer,
925 .pcm_construct = rz_ssi_pcm_new,
926 .legacy_dai_naming = 1,
927 };
928
rz_ssi_probe(struct platform_device * pdev)929 static int rz_ssi_probe(struct platform_device *pdev)
930 {
931 struct rz_ssi_priv *ssi;
932 struct clk *audio_clk;
933 struct resource *res;
934 int ret;
935
936 ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
937 if (!ssi)
938 return -ENOMEM;
939
940 ssi->pdev = pdev;
941 ssi->dev = &pdev->dev;
942 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
943 if (IS_ERR(ssi->base))
944 return PTR_ERR(ssi->base);
945
946 ssi->phys = res->start;
947 ssi->clk = devm_clk_get(&pdev->dev, "ssi");
948 if (IS_ERR(ssi->clk))
949 return PTR_ERR(ssi->clk);
950
951 ssi->sfr_clk = devm_clk_get(&pdev->dev, "ssi_sfr");
952 if (IS_ERR(ssi->sfr_clk))
953 return PTR_ERR(ssi->sfr_clk);
954
955 audio_clk = devm_clk_get(&pdev->dev, "audio_clk1");
956 if (IS_ERR(audio_clk))
957 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk),
958 "no audio clk1");
959
960 ssi->audio_clk_1 = clk_get_rate(audio_clk);
961 audio_clk = devm_clk_get(&pdev->dev, "audio_clk2");
962 if (IS_ERR(audio_clk))
963 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk),
964 "no audio clk2");
965
966 ssi->audio_clk_2 = clk_get_rate(audio_clk);
967 if (!(ssi->audio_clk_1 || ssi->audio_clk_2))
968 return dev_err_probe(&pdev->dev, -EINVAL,
969 "no audio clk1 or audio clk2");
970
971 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2;
972
973 /* Detect DMA support */
974 ret = rz_ssi_dma_request(ssi, &pdev->dev);
975 if (ret < 0) {
976 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
977 ssi->playback.transfer = rz_ssi_pio_send;
978 ssi->capture.transfer = rz_ssi_pio_recv;
979 } else {
980 dev_info(&pdev->dev, "DMA enabled");
981 ssi->playback.transfer = rz_ssi_dma_transfer;
982 ssi->capture.transfer = rz_ssi_dma_transfer;
983 }
984
985 ssi->playback.priv = ssi;
986 ssi->capture.priv = ssi;
987
988 spin_lock_init(&ssi->lock);
989 dev_set_drvdata(&pdev->dev, ssi);
990
991 /* Error Interrupt */
992 ssi->irq_int = platform_get_irq_byname(pdev, "int_req");
993 if (ssi->irq_int < 0) {
994 rz_ssi_release_dma_channels(ssi);
995 return ssi->irq_int;
996 }
997
998 ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt,
999 0, dev_name(&pdev->dev), ssi);
1000 if (ret < 0) {
1001 rz_ssi_release_dma_channels(ssi);
1002 return dev_err_probe(&pdev->dev, ret,
1003 "irq request error (int_req)\n");
1004 }
1005
1006 if (!rz_ssi_is_dma_enabled(ssi)) {
1007 /* Tx and Rx interrupts (pio only) */
1008 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
1009 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
1010 if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) {
1011 ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt");
1012 if (ssi->irq_rt < 0)
1013 return ssi->irq_rt;
1014
1015 ret = devm_request_irq(&pdev->dev, ssi->irq_rt,
1016 &rz_ssi_interrupt, 0,
1017 dev_name(&pdev->dev), ssi);
1018 if (ret < 0)
1019 return dev_err_probe(&pdev->dev, ret,
1020 "irq request error (dma_rt)\n");
1021 } else {
1022 if (ssi->irq_tx < 0)
1023 return ssi->irq_tx;
1024
1025 if (ssi->irq_rx < 0)
1026 return ssi->irq_rx;
1027
1028 ret = devm_request_irq(&pdev->dev, ssi->irq_tx,
1029 &rz_ssi_interrupt, 0,
1030 dev_name(&pdev->dev), ssi);
1031 if (ret < 0)
1032 return dev_err_probe(&pdev->dev, ret,
1033 "irq request error (dma_tx)\n");
1034
1035 ret = devm_request_irq(&pdev->dev, ssi->irq_rx,
1036 &rz_ssi_interrupt, 0,
1037 dev_name(&pdev->dev), ssi);
1038 if (ret < 0)
1039 return dev_err_probe(&pdev->dev, ret,
1040 "irq request error (dma_rx)\n");
1041 }
1042 }
1043
1044 ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1045 if (IS_ERR(ssi->rstc)) {
1046 ret = PTR_ERR(ssi->rstc);
1047 goto err_reset;
1048 }
1049
1050 reset_control_deassert(ssi->rstc);
1051 pm_runtime_enable(&pdev->dev);
1052 ret = pm_runtime_resume_and_get(&pdev->dev);
1053 if (ret < 0) {
1054 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed\n");
1055 goto err_pm;
1056 }
1057
1058 ret = devm_snd_soc_register_component(&pdev->dev, &rz_ssi_soc_component,
1059 rz_ssi_soc_dai,
1060 ARRAY_SIZE(rz_ssi_soc_dai));
1061 if (ret < 0) {
1062 dev_err(&pdev->dev, "failed to register snd component\n");
1063 goto err_snd_soc;
1064 }
1065
1066 return 0;
1067
1068 err_snd_soc:
1069 pm_runtime_put(ssi->dev);
1070 err_pm:
1071 pm_runtime_disable(ssi->dev);
1072 reset_control_assert(ssi->rstc);
1073 err_reset:
1074 rz_ssi_release_dma_channels(ssi);
1075
1076 return ret;
1077 }
1078
rz_ssi_remove(struct platform_device * pdev)1079 static void rz_ssi_remove(struct platform_device *pdev)
1080 {
1081 struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev);
1082
1083 rz_ssi_release_dma_channels(ssi);
1084
1085 pm_runtime_put(ssi->dev);
1086 pm_runtime_disable(ssi->dev);
1087 reset_control_assert(ssi->rstc);
1088 }
1089
1090 static const struct of_device_id rz_ssi_of_match[] = {
1091 { .compatible = "renesas,rz-ssi", },
1092 {/* Sentinel */},
1093 };
1094 MODULE_DEVICE_TABLE(of, rz_ssi_of_match);
1095
1096 static struct platform_driver rz_ssi_driver = {
1097 .driver = {
1098 .name = "rz-ssi-pcm-audio",
1099 .of_match_table = rz_ssi_of_match,
1100 },
1101 .probe = rz_ssi_probe,
1102 .remove_new = rz_ssi_remove,
1103 };
1104
1105 module_platform_driver(rz_ssi_driver);
1106
1107 MODULE_LICENSE("GPL v2");
1108 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver");
1109 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
1110