1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/log2.h> 11 #include <linux/io.h> 12 13 /** 14 * DOC: cxl objects 15 * 16 * The CXL core objects like ports, decoders, and regions are shared 17 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 18 * (port-driver, region-driver, nvdimm object-drivers... etc). 19 */ 20 21 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 22 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 23 24 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 25 #define CXL_CM_OFFSET 0x1000 26 #define CXL_CM_CAP_HDR_OFFSET 0x0 27 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 28 #define CM_CAP_HDR_CAP_ID 1 29 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 30 #define CM_CAP_HDR_CAP_VERSION 1 31 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 32 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 33 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 34 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 35 36 #define CXL_CM_CAP_CAP_ID_RAS 0x2 37 #define CXL_CM_CAP_CAP_ID_HDM 0x5 38 #define CXL_CM_CAP_CAP_HDM_VERSION 1 39 40 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 41 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 42 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 43 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 44 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 45 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 46 #define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) 47 #define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) 48 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 49 #define CXL_HDM_DECODER_ENABLE BIT(1) 50 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 51 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 52 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 53 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 54 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 55 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 56 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 57 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 58 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 59 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 60 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 61 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12) 62 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 63 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 64 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 65 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 66 67 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 68 #define CXL_DECODER_MIN_GRANULARITY 256 69 #define CXL_DECODER_MAX_ENCODED_IG 6 70 cxl_hdm_decoder_count(u32 cap_hdr)71 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 72 { 73 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 74 75 return val ? val * 2 : 1; 76 } 77 78 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ eig_to_granularity(u16 eig,unsigned int * granularity)79 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 80 { 81 if (eig > CXL_DECODER_MAX_ENCODED_IG) 82 return -EINVAL; 83 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 84 return 0; 85 } 86 87 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ eiw_to_ways(u8 eiw,unsigned int * ways)88 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 89 { 90 switch (eiw) { 91 case 0 ... 4: 92 *ways = 1 << eiw; 93 break; 94 case 8 ... 10: 95 *ways = 3 << (eiw - 8); 96 break; 97 default: 98 return -EINVAL; 99 } 100 101 return 0; 102 } 103 granularity_to_eig(int granularity,u16 * eig)104 static inline int granularity_to_eig(int granularity, u16 *eig) 105 { 106 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 107 !is_power_of_2(granularity)) 108 return -EINVAL; 109 *eig = ilog2(granularity) - 8; 110 return 0; 111 } 112 ways_to_eiw(unsigned int ways,u8 * eiw)113 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 114 { 115 if (ways > 16) 116 return -EINVAL; 117 if (is_power_of_2(ways)) { 118 *eiw = ilog2(ways); 119 return 0; 120 } 121 if (ways % 3) 122 return -EINVAL; 123 ways /= 3; 124 if (!is_power_of_2(ways)) 125 return -EINVAL; 126 *eiw = ilog2(ways) + 8; 127 return 0; 128 } 129 130 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 131 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 132 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 133 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 134 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 135 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 136 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 137 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 138 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 139 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 140 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 141 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 142 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 143 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 144 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 145 #define CXL_RAS_CAPABILITY_LENGTH 0x58 146 #define CXL_HEADERLOG_SIZE SZ_512 147 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 148 149 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 150 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 151 #define CXLDEV_CAP_ARRAY_CAP_ID 0 152 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 153 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 154 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 155 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 156 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 157 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 158 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 159 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 160 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 161 162 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 163 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 164 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 165 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 166 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 167 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 168 169 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 170 CXLDEV_EVENT_STATUS_WARN | \ 171 CXLDEV_EVENT_STATUS_FAIL | \ 172 CXLDEV_EVENT_STATUS_FATAL) 173 174 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 175 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 176 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 177 178 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 179 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 180 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 181 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6) 182 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) 183 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 184 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 185 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2) 186 #define CXLDEV_MBOX_CMD_OFFSET 0x08 187 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 188 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 189 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 190 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0) 191 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 192 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 193 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 194 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16) 195 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32) 196 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48) 197 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 198 199 /* 200 * Using struct_group() allows for per register-block-type helper routines, 201 * without requiring block-type agnostic code to include the prefix. 202 */ 203 struct cxl_regs { 204 /* 205 * Common set of CXL Component register block base pointers 206 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 207 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 208 */ 209 struct_group_tagged(cxl_component_regs, component, 210 void __iomem *hdm_decoder; 211 void __iomem *ras; 212 ); 213 /* 214 * Common set of CXL Device register block base pointers 215 * @status: CXL 2.0 8.2.8.3 Device Status Registers 216 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 217 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 218 */ 219 struct_group_tagged(cxl_device_regs, device_regs, 220 void __iomem *status, *mbox, *memdev; 221 ); 222 223 struct_group_tagged(cxl_pmu_regs, pmu_regs, 224 void __iomem *pmu; 225 ); 226 }; 227 228 struct cxl_reg_map { 229 bool valid; 230 int id; 231 unsigned long offset; 232 unsigned long size; 233 }; 234 235 struct cxl_component_reg_map { 236 struct cxl_reg_map hdm_decoder; 237 struct cxl_reg_map ras; 238 }; 239 240 struct cxl_device_reg_map { 241 struct cxl_reg_map status; 242 struct cxl_reg_map mbox; 243 struct cxl_reg_map memdev; 244 }; 245 246 struct cxl_pmu_reg_map { 247 struct cxl_reg_map pmu; 248 }; 249 250 /** 251 * struct cxl_register_map - DVSEC harvested register block mapping parameters 252 * @host: device for devm operations and logging 253 * @base: virtual base of the register-block-BAR + @block_offset 254 * @resource: physical resource base of the register block 255 * @max_size: maximum mapping size to perform register search 256 * @reg_type: see enum cxl_regloc_type 257 * @component_map: cxl_reg_map for component registers 258 * @device_map: cxl_reg_maps for device registers 259 * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units 260 */ 261 struct cxl_register_map { 262 struct device *host; 263 void __iomem *base; 264 resource_size_t resource; 265 resource_size_t max_size; 266 u8 reg_type; 267 union { 268 struct cxl_component_reg_map component_map; 269 struct cxl_device_reg_map device_map; 270 struct cxl_pmu_reg_map pmu_map; 271 }; 272 }; 273 274 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 275 struct cxl_component_reg_map *map); 276 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 277 struct cxl_device_reg_map *map); 278 int cxl_map_component_regs(const struct cxl_register_map *map, 279 struct cxl_component_regs *regs, 280 unsigned long map_mask); 281 int cxl_map_device_regs(const struct cxl_register_map *map, 282 struct cxl_device_regs *regs); 283 int cxl_map_pmu_regs(struct pci_dev *pdev, struct cxl_pmu_regs *regs, 284 struct cxl_register_map *map); 285 286 enum cxl_regloc_type; 287 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); 288 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 289 struct cxl_register_map *map, int index); 290 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 291 struct cxl_register_map *map); 292 int cxl_setup_regs(struct cxl_register_map *map); 293 struct cxl_dport; 294 resource_size_t cxl_rcd_component_reg_phys(struct device *dev, 295 struct cxl_dport *dport); 296 297 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 298 #define CXL_TARGET_STRLEN 20 299 300 /* 301 * cxl_decoder flags that define the type of memory / devices this 302 * decoder supports as well as configuration lock status See "CXL 2.0 303 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 304 * Additionally indicate whether decoder settings were autodetected, 305 * user customized. 306 */ 307 #define CXL_DECODER_F_RAM BIT(0) 308 #define CXL_DECODER_F_PMEM BIT(1) 309 #define CXL_DECODER_F_TYPE2 BIT(2) 310 #define CXL_DECODER_F_TYPE3 BIT(3) 311 #define CXL_DECODER_F_LOCK BIT(4) 312 #define CXL_DECODER_F_ENABLE BIT(5) 313 #define CXL_DECODER_F_MASK GENMASK(5, 0) 314 315 enum cxl_decoder_type { 316 CXL_DECODER_DEVMEM = 2, 317 CXL_DECODER_HOSTONLYMEM = 3, 318 }; 319 320 /* 321 * Current specification goes up to 8, double that seems a reasonable 322 * software max for the foreseeable future 323 */ 324 #define CXL_DECODER_MAX_INTERLEAVE 16 325 326 327 /** 328 * struct cxl_decoder - Common CXL HDM Decoder Attributes 329 * @dev: this decoder's device 330 * @id: kernel device name id 331 * @hpa_range: Host physical address range mapped by this decoder 332 * @interleave_ways: number of cxl_dports in this decode 333 * @interleave_granularity: data stride per dport 334 * @target_type: accelerator vs expander (type2 vs type3) selector 335 * @region: currently assigned region for this decoder 336 * @flags: memory type capabilities and locking 337 * @commit: device/decoder-type specific callback to commit settings to hw 338 * @reset: device/decoder-type specific callback to reset hw settings 339 */ 340 struct cxl_decoder { 341 struct device dev; 342 int id; 343 struct range hpa_range; 344 int interleave_ways; 345 int interleave_granularity; 346 enum cxl_decoder_type target_type; 347 struct cxl_region *region; 348 unsigned long flags; 349 int (*commit)(struct cxl_decoder *cxld); 350 void (*reset)(struct cxl_decoder *cxld); 351 }; 352 353 /* 354 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions 355 * while cxld_unregister() is running 356 */ 357 enum cxl_decoder_mode { 358 CXL_DECODER_NONE, 359 CXL_DECODER_RAM, 360 CXL_DECODER_PMEM, 361 CXL_DECODER_MIXED, 362 CXL_DECODER_DEAD, 363 }; 364 cxl_decoder_mode_name(enum cxl_decoder_mode mode)365 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) 366 { 367 static const char * const names[] = { 368 [CXL_DECODER_NONE] = "none", 369 [CXL_DECODER_RAM] = "ram", 370 [CXL_DECODER_PMEM] = "pmem", 371 [CXL_DECODER_MIXED] = "mixed", 372 }; 373 374 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED) 375 return names[mode]; 376 return "mixed"; 377 } 378 379 /* 380 * Track whether this decoder is reserved for region autodiscovery, or 381 * free for userspace provisioning. 382 */ 383 enum cxl_decoder_state { 384 CXL_DECODER_STATE_MANUAL, 385 CXL_DECODER_STATE_AUTO, 386 }; 387 388 /** 389 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 390 * @cxld: base cxl_decoder_object 391 * @dpa_res: actively claimed DPA span of this decoder 392 * @skip: offset into @dpa_res where @cxld.hpa_range maps 393 * @mode: which memory type / access-mode-partition this decoder targets 394 * @state: autodiscovery state 395 * @pos: interleave position in @cxld.region 396 */ 397 struct cxl_endpoint_decoder { 398 struct cxl_decoder cxld; 399 struct resource *dpa_res; 400 resource_size_t skip; 401 enum cxl_decoder_mode mode; 402 enum cxl_decoder_state state; 403 int pos; 404 }; 405 406 /** 407 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 408 * @cxld: base cxl_decoder object 409 * @nr_targets: number of elements in @target 410 * @target: active ordered target list in current decoder configuration 411 * 412 * The 'switch' decoder type represents the decoder instances of cxl_port's that 413 * route from the root of a CXL memory decode topology to the endpoints. They 414 * come in two flavors, root-level decoders, statically defined by platform 415 * firmware, and mid-level decoders, where interleave-granularity, 416 * interleave-width, and the target list are mutable. 417 */ 418 struct cxl_switch_decoder { 419 struct cxl_decoder cxld; 420 int nr_targets; 421 struct cxl_dport *target[]; 422 }; 423 424 struct cxl_root_decoder; 425 typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, 426 int pos); 427 428 /** 429 * struct cxl_root_decoder - Static platform CXL address decoder 430 * @res: host / parent resource for region allocations 431 * @region_id: region id for next region provisioning event 432 * @calc_hb: which host bridge covers the n'th position by granularity 433 * @platform_data: platform specific configuration data 434 * @range_lock: sync region autodiscovery by address range 435 * @cxlsd: base cxl switch decoder 436 */ 437 struct cxl_root_decoder { 438 struct resource *res; 439 atomic_t region_id; 440 cxl_calc_hb_fn calc_hb; 441 void *platform_data; 442 struct mutex range_lock; 443 struct cxl_switch_decoder cxlsd; 444 }; 445 446 /* 447 * enum cxl_config_state - State machine for region configuration 448 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 449 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 450 * changes to interleave_ways or interleave_granularity 451 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 452 * active 453 * @CXL_CONFIG_RESET_PENDING: see commit_store() 454 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 455 */ 456 enum cxl_config_state { 457 CXL_CONFIG_IDLE, 458 CXL_CONFIG_INTERLEAVE_ACTIVE, 459 CXL_CONFIG_ACTIVE, 460 CXL_CONFIG_RESET_PENDING, 461 CXL_CONFIG_COMMIT, 462 }; 463 464 /** 465 * struct cxl_region_params - region settings 466 * @state: allow the driver to lockdown further parameter changes 467 * @uuid: unique id for persistent regions 468 * @interleave_ways: number of endpoints in the region 469 * @interleave_granularity: capacity each endpoint contributes to a stripe 470 * @res: allocated iomem capacity for this region 471 * @targets: active ordered targets in current decoder configuration 472 * @nr_targets: number of targets 473 * 474 * State transitions are protected by the cxl_region_rwsem 475 */ 476 struct cxl_region_params { 477 enum cxl_config_state state; 478 uuid_t uuid; 479 int interleave_ways; 480 int interleave_granularity; 481 struct resource *res; 482 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 483 int nr_targets; 484 }; 485 486 /* 487 * Indicate whether this region has been assembled by autodetection or 488 * userspace assembly. Prevent endpoint decoders outside of automatic 489 * detection from being added to the region. 490 */ 491 #define CXL_REGION_F_AUTO 0 492 493 /* 494 * Require that a committed region successfully complete a teardown once 495 * any of its associated decoders have been torn down. This maintains 496 * the commit state for the region since there are committed decoders, 497 * but blocks cxl_region_probe(). 498 */ 499 #define CXL_REGION_F_NEEDS_RESET 1 500 501 /** 502 * struct cxl_region - CXL region 503 * @dev: This region's device 504 * @id: This region's id. Id is globally unique across all regions 505 * @mode: Endpoint decoder allocation / access mode 506 * @type: Endpoint decoder target type 507 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 508 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 509 * @flags: Region state flags 510 * @params: active + config params for the region 511 */ 512 struct cxl_region { 513 struct device dev; 514 int id; 515 enum cxl_decoder_mode mode; 516 enum cxl_decoder_type type; 517 struct cxl_nvdimm_bridge *cxl_nvb; 518 struct cxl_pmem_region *cxlr_pmem; 519 unsigned long flags; 520 struct cxl_region_params params; 521 }; 522 523 struct cxl_nvdimm_bridge { 524 int id; 525 struct device dev; 526 struct cxl_port *port; 527 struct nvdimm_bus *nvdimm_bus; 528 struct nvdimm_bus_descriptor nd_desc; 529 }; 530 531 #define CXL_DEV_ID_LEN 19 532 533 struct cxl_nvdimm { 534 struct device dev; 535 struct cxl_memdev *cxlmd; 536 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 537 }; 538 539 struct cxl_pmem_region_mapping { 540 struct cxl_memdev *cxlmd; 541 struct cxl_nvdimm *cxl_nvd; 542 u64 start; 543 u64 size; 544 int position; 545 }; 546 547 struct cxl_pmem_region { 548 struct device dev; 549 struct cxl_region *cxlr; 550 struct nd_region *nd_region; 551 struct range hpa_range; 552 int nr_mappings; 553 struct cxl_pmem_region_mapping mapping[]; 554 }; 555 556 struct cxl_dax_region { 557 struct device dev; 558 struct cxl_region *cxlr; 559 struct range hpa_range; 560 }; 561 562 /** 563 * struct cxl_port - logical collection of upstream port devices and 564 * downstream port devices to construct a CXL memory 565 * decode hierarchy. 566 * @dev: this port's device 567 * @uport_dev: PCI or platform device implementing the upstream port capability 568 * @host_bridge: Shortcut to the platform attach point for this port 569 * @id: id for port device-name 570 * @dports: cxl_dport instances referenced by decoders 571 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 572 * @regions: cxl_region_ref instances, regions mapped by this port 573 * @parent_dport: dport that points to this port in the parent 574 * @decoder_ida: allocator for decoder ids 575 * @comp_map: component register capability mappings 576 * @nr_dports: number of entries in @dports 577 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 578 * @commit_end: cursor to track highest committed decoder for commit ordering 579 * @component_reg_phys: component register capability base address (optional) 580 * @dead: last ep has been removed, force port re-creation 581 * @depth: How deep this port is relative to the root. depth 0 is the root. 582 * @cdat: Cached CDAT data 583 * @cdat_available: Should a CDAT attribute be available in sysfs 584 */ 585 struct cxl_port { 586 struct device dev; 587 struct device *uport_dev; 588 struct device *host_bridge; 589 int id; 590 struct xarray dports; 591 struct xarray endpoints; 592 struct xarray regions; 593 struct cxl_dport *parent_dport; 594 struct ida decoder_ida; 595 struct cxl_register_map comp_map; 596 int nr_dports; 597 int hdm_end; 598 int commit_end; 599 resource_size_t component_reg_phys; 600 bool dead; 601 unsigned int depth; 602 struct cxl_cdat { 603 void *table; 604 size_t length; 605 } cdat; 606 bool cdat_available; 607 }; 608 609 static inline struct cxl_dport * cxl_find_dport_by_dev(struct cxl_port * port,const struct device * dport_dev)610 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 611 { 612 return xa_load(&port->dports, (unsigned long)dport_dev); 613 } 614 615 struct cxl_rcrb_info { 616 resource_size_t base; 617 u16 aer_cap; 618 }; 619 620 /** 621 * struct cxl_dport - CXL downstream port 622 * @dport_dev: PCI bridge or firmware device representing the downstream link 623 * @comp_map: component register capability mappings 624 * @port_id: unique hardware identifier for dport in decoder target list 625 * @rcrb: Data about the Root Complex Register Block layout 626 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 627 * @port: reference to cxl_port that contains this downstream port 628 */ 629 struct cxl_dport { 630 struct device *dport_dev; 631 struct cxl_register_map comp_map; 632 int port_id; 633 struct cxl_rcrb_info rcrb; 634 bool rch; 635 struct cxl_port *port; 636 }; 637 638 /** 639 * struct cxl_ep - track an endpoint's interest in a port 640 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 641 * @dport: which dport routes to this endpoint on @port 642 * @next: cxl switch port across the link attached to @dport NULL if 643 * attached to an endpoint 644 */ 645 struct cxl_ep { 646 struct device *ep; 647 struct cxl_dport *dport; 648 struct cxl_port *next; 649 }; 650 651 /** 652 * struct cxl_region_ref - track a region's interest in a port 653 * @port: point in topology to install this reference 654 * @decoder: decoder assigned for @region in @port 655 * @region: region for this reference 656 * @endpoints: cxl_ep references for region members beneath @port 657 * @nr_targets_set: track how many targets have been programmed during setup 658 * @nr_eps: number of endpoints beneath @port 659 * @nr_targets: number of distinct targets needed to reach @nr_eps 660 */ 661 struct cxl_region_ref { 662 struct cxl_port *port; 663 struct cxl_decoder *decoder; 664 struct cxl_region *region; 665 struct xarray endpoints; 666 int nr_targets_set; 667 int nr_eps; 668 int nr_targets; 669 }; 670 671 /* 672 * The platform firmware device hosting the root is also the top of the 673 * CXL port topology. All other CXL ports have another CXL port as their 674 * parent and their ->uport_dev / host device is out-of-line of the port 675 * ancestry. 676 */ is_cxl_root(struct cxl_port * port)677 static inline bool is_cxl_root(struct cxl_port *port) 678 { 679 return port->uport_dev == port->dev.parent; 680 } 681 682 int cxl_num_decoders_committed(struct cxl_port *port); 683 bool is_cxl_port(const struct device *dev); 684 struct cxl_port *to_cxl_port(const struct device *dev); 685 void cxl_port_commit_reap(struct cxl_decoder *cxld); 686 struct pci_bus; 687 int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, 688 struct pci_bus *bus); 689 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 690 struct cxl_port *devm_cxl_add_port(struct device *host, 691 struct device *uport_dev, 692 resource_size_t component_reg_phys, 693 struct cxl_dport *parent_dport); 694 struct cxl_port *find_cxl_root(struct cxl_port *port); 695 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 696 void cxl_bus_rescan(void); 697 void cxl_bus_drain(void); 698 struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, 699 struct cxl_dport **dport); 700 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 701 struct cxl_dport **dport); 702 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 703 704 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 705 struct device *dport, int port_id, 706 resource_size_t component_reg_phys); 707 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 708 struct device *dport_dev, int port_id, 709 resource_size_t rcrb); 710 711 struct cxl_decoder *to_cxl_decoder(struct device *dev); 712 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 713 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 714 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 715 bool is_root_decoder(struct device *dev); 716 bool is_switch_decoder(struct device *dev); 717 bool is_endpoint_decoder(struct device *dev); 718 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 719 unsigned int nr_targets, 720 cxl_calc_hb_fn calc_hb); 721 struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos); 722 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 723 unsigned int nr_targets); 724 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 725 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 726 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 727 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 728 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 729 730 /** 731 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 732 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 733 * @ranges: Number of active HDM ranges this device uses. 734 * @port: endpoint port associated with this info instance 735 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 736 */ 737 struct cxl_endpoint_dvsec_info { 738 bool mem_enabled; 739 int ranges; 740 struct cxl_port *port; 741 struct range dvsec_range[2]; 742 }; 743 744 struct cxl_hdm; 745 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 746 struct cxl_endpoint_dvsec_info *info); 747 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, 748 struct cxl_endpoint_dvsec_info *info); 749 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 750 int cxl_dvsec_rr_decode(struct device *dev, int dvsec, 751 struct cxl_endpoint_dvsec_info *info); 752 753 bool is_cxl_region(struct device *dev); 754 755 extern struct bus_type cxl_bus_type; 756 757 struct cxl_driver { 758 const char *name; 759 int (*probe)(struct device *dev); 760 void (*remove)(struct device *dev); 761 struct device_driver drv; 762 int id; 763 }; 764 to_cxl_drv(struct device_driver * drv)765 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv) 766 { 767 return container_of(drv, struct cxl_driver, drv); 768 } 769 770 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 771 const char *modname); 772 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 773 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 774 775 #define module_cxl_driver(__cxl_driver) \ 776 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 777 778 #define CXL_DEVICE_NVDIMM_BRIDGE 1 779 #define CXL_DEVICE_NVDIMM 2 780 #define CXL_DEVICE_PORT 3 781 #define CXL_DEVICE_ROOT 4 782 #define CXL_DEVICE_MEMORY_EXPANDER 5 783 #define CXL_DEVICE_REGION 6 784 #define CXL_DEVICE_PMEM_REGION 7 785 #define CXL_DEVICE_DAX_REGION 8 786 #define CXL_DEVICE_PMU 9 787 788 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 789 #define CXL_MODALIAS_FMT "cxl:t%d" 790 791 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 792 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 793 struct cxl_port *port); 794 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 795 bool is_cxl_nvdimm(struct device *dev); 796 bool is_cxl_nvdimm_bridge(struct device *dev); 797 int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); 798 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd); 799 800 #ifdef CONFIG_CXL_REGION 801 bool is_cxl_pmem_region(struct device *dev); 802 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 803 int cxl_add_to_region(struct cxl_port *root, 804 struct cxl_endpoint_decoder *cxled); 805 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 806 #else is_cxl_pmem_region(struct device * dev)807 static inline bool is_cxl_pmem_region(struct device *dev) 808 { 809 return false; 810 } to_cxl_pmem_region(struct device * dev)811 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 812 { 813 return NULL; 814 } cxl_add_to_region(struct cxl_port * root,struct cxl_endpoint_decoder * cxled)815 static inline int cxl_add_to_region(struct cxl_port *root, 816 struct cxl_endpoint_decoder *cxled) 817 { 818 return 0; 819 } to_cxl_dax_region(struct device * dev)820 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 821 { 822 return NULL; 823 } 824 #endif 825 826 /* 827 * Unit test builds overrides this to __weak, find the 'strong' version 828 * of these symbols in tools/testing/cxl/. 829 */ 830 #ifndef __mock 831 #define __mock static 832 #endif 833 834 #endif /* __CXL_H__ */ 835