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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c257 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); in gfx_v9_4_3_ring_test_ring()
524 u32 sh_num, u32 instance, int xcc_id) in gfx_v9_4_3_xcc_select_se_sh() argument
547 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); in gfx_v9_4_3_xcc_select_se_sh()
550 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t … in wave_read_ind() argument
552 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_ind()
557 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); in wave_read_ind()
560 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in wave_read_regs() argument
564 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_regs()
572 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); in wave_read_regs()
576 uint32_t xcc_id, uint32_t simd, uint32_t wave, in gfx_v9_4_3_read_wave_data() argument
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H A Damdgpu_gfx.h286 u32 sh_num, u32 instance, int xcc_id);
287 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
289 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
292 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
296 u32 queue, u32 vmid, u32 xcc_id);
458 …elect_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (… argument
459 …_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe)… argument
481 struct amdgpu_irq_src *irq, int xcc_id);
485 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id);
487 unsigned hpd_size, int xcc_id);
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H A Damdgpu_gfx.c67 int xcc_id, int mec, int pipe, int queue) in amdgpu_gfx_is_mec_queue_enabled() argument
70 adev->gfx.mec_bitmap[xcc_id].queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
272 struct amdgpu_ring *ring, int xcc_id) in amdgpu_gfx_kiq_acquire() argument
282 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap)) in amdgpu_gfx_kiq_acquire()
308 struct amdgpu_irq_src *irq, int xcc_id) in amdgpu_gfx_kiq_init_ring() argument
310 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; in amdgpu_gfx_kiq_init_ring()
318 ring->xcc_id = xcc_id; in amdgpu_gfx_kiq_init_ring()
319 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); in amdgpu_gfx_kiq_init_ring()
322 xcc_id * adev->doorbell_index.xcc_doorbell_range) in amdgpu_gfx_kiq_init_ring()
325 r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id); in amdgpu_gfx_kiq_init_ring()
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H A Damdgpu_rlc.h162 void (*set_safe_mode)(struct amdgpu_device *adev, int xcc_id);
163 void (*unset_safe_mode)(struct amdgpu_device *adev, int xcc_id);
265 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id);
266 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id);
H A Damdgpu_umr.h46 u32 xcc_id; member
50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
H A Daqua_vanjaram.c168 aqua_vanjaram_set_xcp_id(adev, ring->xcc_id, ring); in aqua_vanjaram_update_partition_sched_list()
547 int xcc_id, uint8_t *mem_id) in __aqua_vanjaram_get_xcp_mem_id() argument
550 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; in __aqua_vanjaram_get_xcp_mem_id()
562 int r, i, xcc_id; in aqua_vanjaram_get_xcp_mem_id() local
582 xcc_id = ffs(xcc_mask) - 1; in aqua_vanjaram_get_xcp_mem_id()
584 return __aqua_vanjaram_get_xcp_mem_id(adev, xcc_id, mem_id); in aqua_vanjaram_get_xcp_mem_id()
586 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); in aqua_vanjaram_get_xcp_mem_id()
H A Damdgpu_rlc.c38 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id) in amdgpu_gfx_rlc_enter_safe_mode() argument
40 if (adev->gfx.rlc.in_safe_mode[xcc_id]) in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_enter_safe_mode()
51 adev->gfx.rlc.in_safe_mode[xcc_id] = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id) in amdgpu_gfx_rlc_exit_safe_mode() argument
65 if (!(adev->gfx.rlc.in_safe_mode[xcc_id])) in amdgpu_gfx_rlc_exit_safe_mode()
75 adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_exit_safe_mode()
76 adev->gfx.rlc.in_safe_mode[xcc_id] = false; in amdgpu_gfx_rlc_exit_safe_mode()
H A Dgfx_v9_0.h30 u32 instance, int xcc_id);
H A Damdgpu_virt.c980 …ic u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) in amdgpu_virt_rlcg_reg_rw() argument
998 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_reg_rw()
1006 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; in amdgpu_virt_rlcg_reg_rw()
1077 u32 acc_flags, u32 hwip, u32 xcc_id) in amdgpu_sriov_wreg() argument
1086 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id); in amdgpu_sriov_wreg()
1097 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) in amdgpu_sriov_rreg() argument
1106 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id); in amdgpu_sriov_rreg()
H A Damdgpu_debugfs.c267 rd->id.grbm.instance, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
273 rd->id.srbm.queue, rd->id.srbm.vmid, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
286 amdgpu_mm_wreg_mmio_rlc(adev, offset >> 2, value, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
299 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
304 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
358 rd->id.xcc_id = 0; in amdgpu_debugfs_regs2_ioctl()
429 amdgpu_gfx_select_se_sh(adev, rd->id.se, rd->id.sh, rd->id.cu, rd->id.xcc_id); in amdgpu_debugfs_gprwave_read()
434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
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H A Damdgpu_virt.h360 u32 acc_flags, u32 hwip, u32 xcc_id);
362 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
H A Dsoc15.h103 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id);
H A Dgmc_v9_0.c559 int ret, xcc_id = 0; in gmc_v9_0_process_interrupt() local
576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, in gmc_v9_0_process_interrupt()
578 if (xcc_id < 0) in gmc_v9_0_process_interrupt()
579 xcc_id = 0; in gmc_v9_0_process_interrupt()
581 hub = &adev->vmhub[xcc_id]; in gmc_v9_0_process_interrupt()
1885 int num_xcc, xcc_id; in gmc_v9_0_init_acpi_mem_ranges() local
1892 for_each_inst(xcc_id, xcc_mask) { in gmc_v9_0_init_acpi_mem_ranges()
1893 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); in gmc_v9_0_init_acpi_mem_ranges()
H A Damdgpu.h1131 uint32_t reg, uint32_t v, uint32_t xcc_id);
1427 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1442 int xcc_id, in amdgpu_acpi_get_mem_info() argument
H A Damdgpu_acpi.c1165 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, in amdgpu_acpi_get_mem_info() argument
1181 if (xcc_info->phy_id == xcc_id) { in amdgpu_acpi_get_mem_info()
H A Dgfx_v11_0.c119 u32 sh_num, u32 instance, int xcc_id);
130 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
131 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
780 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, ui… in gfx_v11_0_read_wave_data() argument
806 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_sgprs() argument
817 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_vgprs() argument
828 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v11_0_select_me_pipe_q() argument
1532 u32 sh_num, u32 instance, int xcc_id) in gfx_v11_0_select_se_sh() argument
4690 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v11_0_set_safe_mode() argument
4709 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v11_0_unset_safe_mode() argument
H A Dsoc15.c340 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id) in soc15_grbm_select() argument
348 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); in soc15_grbm_select()
H A Damdgpu_ring.h258 u32 xcc_id; member
H A Dgfx_v7_0.c1554 int xcc_id) in gfx_v7_0_select_se_sh() argument
3362 static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v7_0_set_safe_mode() argument
3384 static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v7_0_unset_safe_mode() argument
4112 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v7_0_read_wave_data() argument
4137 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v7_0_read_wave_sgprs() argument
4147 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v7_0_select_me_pipe_q() argument
H A Dgfx_v6_0.c1288 u32 sh_num, u32 instance, int xcc_id) in gfx_v6_0_select_se_sh() argument
2971 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v6_0_read_wave_data() argument
2996 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v6_0_read_wave_sgprs() argument
3006 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v6_0_select_me_pipe_q() argument
H A Dgfx_v9_0.c1771 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v9_0_read_wave_data() argument
1792 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v9_0_read_wave_sgprs() argument
1801 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v9_0_read_wave_vgprs() argument
1812 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v9_0_select_me_pipe_q() argument
2224 u32 instance, int xcc_id) in gfx_v9_0_select_se_sh() argument
4617 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v9_0_set_safe_mode() argument
4634 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v9_0_unset_safe_mode() argument
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v9.c555 int xcc_id, err, inst = 0; in hiq_load_mqd_kiq_v9_4_3() local
559 for_each_inst(xcc_id, xcc_mask) { in hiq_load_mqd_kiq_v9_4_3()
563 p->doorbell_off, xcc_id); in hiq_load_mqd_kiq_v9_4_3()
579 int xcc_id, err, inst = 0; in destroy_hiq_mqd_v9_4_3() local
584 for_each_inst(xcc_id, xcc_mask) { in destroy_hiq_mqd_v9_4_3()
590 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, xcc_id); in destroy_hiq_mqd_v9_4_3()
716 int xcc_id, err, inst = 0; in destroy_mqd_v9_4_3() local
724 for_each_inst(xcc_id, xcc_mask) { in destroy_mqd_v9_4_3()
728 queue_id, xcc_id); in destroy_mqd_v9_4_3()
746 int xcc_id, err, inst = 0; in load_mqd_v9_4_3() local
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H A Dkfd_device_queue_manager.c144 int xcc_id; in program_sh_mem_settings() local
146 for_each_inst(xcc_id, xcc_mask) in program_sh_mem_settings()
150 qpd->sh_mem_bases, xcc_id); in program_sh_mem_settings()
449 int xcc_id; in program_trap_handler_settings() local
452 for_each_inst(xcc_id, xcc_mask) in program_trap_handler_settings()
455 qpd->tma_addr, xcc_id); in program_trap_handler_settings()
719 int xcc_id; in dbgdev_wave_reset_wavefronts() local
764 for_each_inst(xcc_id, xcc_mask) in dbgdev_wave_reset_wavefronts()
767 reg_sq_cmd.u32All, xcc_id); in dbgdev_wave_reset_wavefronts()
1380 int xcc_id, ret; in set_pasid_vmid_mapping() local
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H A Dkfd_debug.c465 int xcc_id, r = kfd_dbg_get_dev_watch_id(pdd, watch_id); in kfd_dbg_trap_set_dev_address_watch() local
480 for_each_inst(xcc_id, xcc_mask) in kfd_dbg_trap_set_dev_address_watch()
488 xcc_id); in kfd_dbg_trap_set_dev_address_watch()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_6_ppt.c683 int xcc_id; in smu_v13_0_6_get_smu_metrics_data() local
695 xcc_id = GET_INST(GC, 0); in smu_v13_0_6_get_smu_metrics_data()
696 *value = SMUQ10_TO_UINT(metrics->GfxclkFrequency[xcc_id]); in smu_v13_0_6_get_smu_metrics_data()

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