Home
last modified time | relevance | path

Searched refs:xT2 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_user.h18 #define xT2 7 macro
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvi.c.inc67 tcg_gen_extract_tl(tmp, get_gpr(ctx, xT2, EXT_NONE), 12, 20);
125 * branch are not tracked. rs1 == xT2 is a sw guarded branch.
127 if (a->rs1 != xRA && a->rs1 != xT0 && a->rs1 != xT2) {