| /openbmc/u-boot/board/renesas/blanche/ |
| H A D | qos.c | 72 writel(0x20082004, DBSC3_0_DBADJ2); in qos_init()
77 writel(0x1F0D0C0C, &s3c->s3crorr); in qos_init()
78 writel(0x1F1F0C0C, &s3c->s3cworr); in qos_init()
82 writel(0x00890089, &s3c_qos->s3cqos0); in qos_init()
83 writel(0x20960010, &s3c_qos->s3cqos1); in qos_init()
84 writel(0x20302030, &s3c_qos->s3cqos2); in qos_init()
85 writel(0x20AA2200, &s3c_qos->s3cqos3); in qos_init()
86 writel(0x00002032, &s3c_qos->s3cqos4); in qos_init()
87 writel(0x20960010, &s3c_qos->s3cqos5); in qos_init()
88 writel(0x20302030, &s3c_qos->s3cqos6); in qos_init()
[all …]
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| /openbmc/u-boot/board/renesas/stout/ |
| H A D | qos.c | 76 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init_es1()
80 writel(0x80FF1C1E, &s3c->s3cadsplcr); in qos_init_es1()
81 writel(0x1F060505, &s3c->s3crorr); in qos_init_es1()
82 writel(0x1F020100, &s3c->s3cworr); in qos_init_es1()
86 writel(0x00800080, &s3c_qos->s3cqos0); in qos_init_es1()
87 writel(0x22000010, &s3c_qos->s3cqos1); in qos_init_es1()
88 writel(0x22002200, &s3c_qos->s3cqos2); in qos_init_es1()
89 writel(0x2F002200, &s3c_qos->s3cqos3); in qos_init_es1()
90 writel(0x2F002F00, &s3c_qos->s3cqos4); in qos_init_es1()
91 writel(0x22000010, &s3c_qos->s3cqos5); in qos_init_es1()
[all …]
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| /openbmc/u-boot/board/renesas/lager/ |
| H A D | qos.c | 74 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init_es1()
78 writel(0x80FF1C1E, &s3c->s3cadsplcr); in qos_init_es1()
79 writel(0x1F060505, &s3c->s3crorr); in qos_init_es1()
80 writel(0x1F020100, &s3c->s3cworr); in qos_init_es1()
84 writel(0x00800080, &s3c_qos->s3cqos0); in qos_init_es1()
85 writel(0x22000010, &s3c_qos->s3cqos1); in qos_init_es1()
86 writel(0x22002200, &s3c_qos->s3cqos2); in qos_init_es1()
87 writel(0x2F002200, &s3c_qos->s3cqos3); in qos_init_es1()
88 writel(0x2F002F00, &s3c_qos->s3cqos4); in qos_init_es1()
89 writel(0x22000010, &s3c_qos->s3cqos5); in qos_init_es1()
[all …]
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| /openbmc/u-boot/board/renesas/gose/ |
| H A D | qos.c | 92 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init()
96 writel(0x00000000, &s3c->s3cadsplcr); in qos_init()
98 writel(0x1F0B0604, &s3c->s3crorr); in qos_init()
99 writel(0x1F0E0705, &s3c->s3cworr); in qos_init()
101 writel(0x1F0B0908, &s3c->s3crorr); in qos_init()
102 writel(0x1F0C0A08, &s3c->s3cworr); in qos_init()
104 writel(0x1F0B0B0B, &s3c->s3crorr); in qos_init()
105 writel(0x1F0E0C0C, &s3c->s3cworr); in qos_init()
109 writel(0x00890089, &s3c_qos->s3cqos0); in qos_init()
110 writel(0x20960010, &s3c_qos->s3cqos1); in qos_init()
[all …]
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| /openbmc/u-boot/board/renesas/koelsch/ |
| H A D | qos.c | 130 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init()
131 writel(0x20042004, DBSC3_1_DBADJ2); in qos_init()
139 writel(0x00BF1B0C, &s3c->s3cadsplcr); in qos_init()
146 writel(0x1F0B0604, &s3c->s3crorr); in qos_init()
147 writel(0x1F0E0705, &s3c->s3cworr); in qos_init()
149 writel(0x1F0B0908, &s3c->s3crorr); in qos_init()
150 writel(0x1F0E0A08, &s3c->s3cworr); in qos_init()
152 writel(0x1F0B0B0B, &s3c->s3crorr); in qos_init()
153 writel(0x1F0E0C0C, &s3c->s3cworr); in qos_init()
156 writel(0x00FF1B1D, &s3c->s3cadsplcr); in qos_init()
[all …]
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| /openbmc/u-boot/board/renesas/alt/ |
| H A D | qos.c | 93 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init()
98 writel(0x1F0B0604, &s3c->s3crorr); in qos_init()
99 writel(0x1F0E0705, &s3c->s3cworr); in qos_init()
101 writel(0x1F0B0908, &s3c->s3crorr); in qos_init()
102 writel(0x1F0E0A08, &s3c->s3cworr); in qos_init()
104 writel(0x1F0B0B0B, &s3c->s3crorr); in qos_init()
105 writel(0x1F0E0C0C, &s3c->s3cworr); in qos_init()
109 writel(0x00890089, &s3c_qos->s3cqos0); in qos_init()
110 writel(0x20960010, &s3c_qos->s3cqos1); in qos_init()
111 writel(0x20302030, &s3c_qos->s3cqos2); in qos_init()
[all …]
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| /openbmc/u-boot/board/renesas/porter/ |
| H A D | qos.c | 113 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init()
114 writel(0x20042004, DBSC3_1_DBADJ2); in qos_init()
122 writel(0x00BF1B0C, &s3c->s3cadsplcr); in qos_init()
127 writel(0x1F0B0908, &s3c->s3crorr); in qos_init()
128 writel(0x1F0C0A08, &s3c->s3cworr); in qos_init()
130 writel(0x00FF1B1D, &s3c->s3cadsplcr); in qos_init()
131 writel(0x1F0D0C0C, &s3c->s3crorr); in qos_init()
132 writel(0x1F0D0C0A, &s3c->s3cworr); in qos_init()
136 writel(0x00890089, &s3c_qos->s3cqos0); in qos_init()
137 writel(0x20960010, &s3c_qos->s3cqos1); in qos_init()
[all …]
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| /openbmc/u-boot/board/renesas/silk/ |
| H A D | qos.c | 76 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init()
80 writel(0x1F0D0B0A, &s3c->s3crorr); in qos_init()
81 writel(0x1F0D0B09, &s3c->s3cworr); in qos_init()
85 writel(0x00890089, &s3c_qos->s3cqos0); in qos_init()
86 writel(0x20960010, &s3c_qos->s3cqos1); in qos_init()
87 writel(0x20302030, &s3c_qos->s3cqos2); in qos_init()
88 writel(0x20AA2200, &s3c_qos->s3cqos3); in qos_init()
89 writel(0x00002032, &s3c_qos->s3cqos4); in qos_init()
90 writel(0x20960010, &s3c_qos->s3cqos5); in qos_init()
91 writel(0x20302030, &s3c_qos->s3cqos6); in qos_init()
[all …]
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| /openbmc/u-boot/drivers/ram/mediatek/ |
| H A D | ddr3-mt7629.c | 244 writel(WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE); in mtk_ddr3_rank_size_detect()
250 writel(~WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE + in mtk_ddr3_rank_size_detect()
276 writel(0x00003010, priv->emi + EMI_CONA); in mtk_ddr3_init()
277 writel(0x00000000, priv->emi + EMI_CONF); in mtk_ddr3_init()
278 writel(0x000006b8, priv->emi + EMI_CONM); in mtk_ddr3_init()
280 writel(0x20c00, priv->dramc_ao + DRAMC_SHU1_DRVING1); in mtk_ddr3_init()
282 writel(0x8320c83, priv->dramc_ao + DRAMC_SHU1_DRVING2); in mtk_ddr3_init()
285 writel(0x2201, priv->dramc_ao + DRAMC_DRAMCTRL); in mtk_ddr3_init()
286 writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL); in mtk_ddr3_init()
287 writel(0xe08, priv->ddrphy + DDRPHY_CA_CMD5); in mtk_ddr3_init()
[all …]
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| /openbmc/u-boot/arch/arm/mach-omap2/am33xx/ |
| H A D | ti816x_emif4.c | 29 writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS in ddr_init_settings()
30 writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS in ddr_init_settings()
31 writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS in ddr_init_settings()
32 writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS in ddr_init_settings()
37 writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */ in ddr_init_settings()
38 writel(0x1, DDRPHY_CONFIG_BASE + 0x104); in ddr_init_settings()
39 writel(0x1, DDRPHY_CONFIG_BASE + 0x19C); in ddr_init_settings()
40 writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8); in ddr_init_settings()
41 writel(0x1, DDRPHY_CONFIG_BASE + 0x240); in ddr_init_settings()
42 writel(0x1, DDRPHY_CONFIG_BASE + 0x24C); in ddr_init_settings()
[all …]
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| H A D | ddr.c | 43 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); in get_mr()
58 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); in set_mr()
59 writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data); in set_mr()
83 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); in config_sdram_emif4d5()
84 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); in config_sdram_emif4d5()
85 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); in config_sdram_emif4d5()
87 writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config); in config_sdram_emif4d5()
88 writel(regs->emif_rd_wr_lvl_rmp_win, in config_sdram_emif4d5()
90 writel(regs->emif_rd_wr_lvl_rmp_ctl, in config_sdram_emif4d5()
92 writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl); in config_sdram_emif4d5()
[all …]
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| /openbmc/u-boot/board/kmc/kzm9g/ |
| H A D | kzm9g.c | 57 writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0); in sbsc_init()
58 writel(0x5, &sbsc->sdgencnt); in sbsc_init()
61 writel(0xacc90159, &sbsc->sdcr0); in sbsc_init()
62 writel(0x00010059, &sbsc->sdcr1); in sbsc_init()
63 writel(0x50874114, &sbsc->sdwcrc0); in sbsc_init()
64 writel(0x33199b37, &sbsc->sdwcrc1); in sbsc_init()
65 writel(0x008f2313, &sbsc->sdwcrc2); in sbsc_init()
66 writel(0x31020707, &sbsc->sdwcr00); in sbsc_init()
67 writel(0x0017040a, &sbsc->sdwcr01); in sbsc_init()
68 writel(0x31020707, &sbsc->sdwcr10); in sbsc_init()
[all …]
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| /openbmc/u-boot/arch/arm/cpu/armv8/hisilicon/ |
| H A D | pinmux.c | 23 writel(MUX_M0, &pmx0->iomg[48]); /* UART0_RXD */ in hi6220_uart_config()
24 writel(MUX_M0, &pmx0->iomg[49]); /* UART0_TXD */ in hi6220_uart_config()
26 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[49]); /* UART0_RXD */ in hi6220_uart_config()
27 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[50]); /* UART0_TXD */ in hi6220_uart_config()
31 writel(MUX_M0, &pmx0->iomg[50]); /* UART1_CTS_N */ in hi6220_uart_config()
32 writel(MUX_M0, &pmx0->iomg[51]); /* UART1_RTS_N */ in hi6220_uart_config()
33 writel(MUX_M0, &pmx0->iomg[52]); /* UART1_RXD */ in hi6220_uart_config()
34 writel(MUX_M0, &pmx0->iomg[53]); /* UART1_TXD */ in hi6220_uart_config()
36 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[51]); /*UART1_CTS_N*/ in hi6220_uart_config()
37 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[53]); /* UART1_RXD */ in hi6220_uart_config()
[all …]
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| /openbmc/u-boot/board/atmark-techno/armadillo-800eva/ |
| H A D | armadillo-800eva.c | 55 writel(0xFF800080, &cpg->rmstpcr4); in s_init()
56 writel(0xFF800080, &cpg->smstpcr4); in s_init()
59 writel(0x00000080, &cpg->usbckcr); in s_init()
66 writel(0x00000000, &cpg->frqcrb); in s_init()
67 writel(0x62030533, &cpg->frqcra); in s_init()
68 writel(0x208A354E, &cpg->frqcrc); in s_init()
69 writel(0x80331050, &cpg->frqcrb); in s_init()
72 writel(0x00000000, &cpg->frqcrd); in s_init()
76 writel(0x0000010B, &cpg->subckcr); in s_init()
79 writel(0x00004004, &cpg->pllc01cr); in s_init()
[all …]
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| /openbmc/u-boot/arch/arm/mach-uniphier/dram/ |
| H A D | umc-pro4.c | 31 writel(0x00000000, ssif_base + 0x0000b004); in umc_start_ssif()
32 writel(0xffffffff, ssif_base + 0x0000c004); in umc_start_ssif()
33 writel(0x000fffcf, ssif_base + 0x0000c008); in umc_start_ssif()
34 writel(0x00000001, ssif_base + 0x0000b000); in umc_start_ssif()
35 writel(0x00000001, ssif_base + 0x0000c000); in umc_start_ssif()
37 writel(0x03010100, ssif_base + UMC_HDMCHSEL); in umc_start_ssif()
38 writel(0x03010101, ssif_base + UMC_MDMCHSEL); in umc_start_ssif()
39 writel(0x03010100, ssif_base + UMC_DVCCHSEL); in umc_start_ssif()
40 writel(0x03010100, ssif_base + UMC_DMDCHSEL); in umc_start_ssif()
42 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); in umc_start_ssif()
[all …]
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| H A D | umc-ld4.c | 48 writel(0x00000000, ssif_base + 0x0000b004); in umc_start_ssif()
49 writel(0xffffffff, ssif_base + 0x0000c004); in umc_start_ssif()
50 writel(0x000fffcf, ssif_base + 0x0000c008); in umc_start_ssif()
51 writel(0x00000001, ssif_base + 0x0000b000); in umc_start_ssif()
52 writel(0x00000001, ssif_base + 0x0000c000); in umc_start_ssif()
53 writel(0x03010101, ssif_base + UMC_MDMCHSEL); in umc_start_ssif()
54 writel(0x03010100, ssif_base + UMC_DMDCHSEL); in umc_start_ssif()
56 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); in umc_start_ssif()
57 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); in umc_start_ssif()
58 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); in umc_start_ssif()
[all …]
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| H A D | umc-sld8.c | 51 writel(0x00000000, ssif_base + 0x0000b004); in umc_start_ssif()
52 writel(0xffffffff, ssif_base + 0x0000c004); in umc_start_ssif()
53 writel(0x000fffcf, ssif_base + 0x0000c008); in umc_start_ssif()
54 writel(0x00000001, ssif_base + 0x0000b000); in umc_start_ssif()
55 writel(0x00000001, ssif_base + 0x0000c000); in umc_start_ssif()
56 writel(0x03010101, ssif_base + UMC_MDMCHSEL); in umc_start_ssif()
57 writel(0x03010100, ssif_base + UMC_DMDCHSEL); in umc_start_ssif()
59 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); in umc_start_ssif()
60 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); in umc_start_ssif()
61 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); in umc_start_ssif()
[all …]
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a23.c | 102 writel(0x40b, &mctl_phy->dcr); in mctl_init()
104 writel(0x1000040b, &mctl_phy->dcr); in mctl_init()
107 writel(0x5c000, &mctl_phy->dllgcr); in mctl_init()
109 writel(0xdc000, &mctl_phy->dllgcr); in mctl_init()
111 writel(0x0a003e3f, &mctl_phy->pgcr0); in mctl_init()
112 writel(0x03008421, &mctl_phy->pgcr1); in mctl_init()
114 writel(dram_para.mr0, &mctl_phy->mr0); in mctl_init()
115 writel(dram_para.mr1, &mctl_phy->mr1); in mctl_init()
116 writel(dram_para.mr2, &mctl_phy->mr2); in mctl_init()
117 writel(dram_para.mr3, &mctl_phy->mr3); in mctl_init()
[all …]
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| H A D | dram_sun6i.c | 42 writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg); in mctl_sys_init()
61 writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr); in mctl_dll_init()
62 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr); in mctl_dll_init()
63 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr); in mctl_dll_init()
65 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr); in mctl_dll_init()
66 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr); in mctl_dll_init()
71 writel(0, &mctl_phy->acdllcr); in mctl_dll_init()
72 writel(0, &mctl_phy->dx0dllcr); in mctl_dll_init()
73 writel(0, &mctl_phy->dx1dllcr); in mctl_dll_init()
75 writel(0, &mctl_phy->dx2dllcr); in mctl_dll_init()
[all …]
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| /openbmc/qemu/tests/qtest/ |
| H A D | npcm7xx_gpio-test.c | 59 writel(GPIO(n) + GP_N_TLOCK2, 0xc0de1248); in gpio_unlock()
60 writel(GPIO(n) + GP_N_TLOCK1, 0xc0defa73); in gpio_unlock()
69 writel(GPIO(n) + GP_N_EVEN, 0x00000000); in gpio_reset()
70 writel(GPIO(n) + GP_N_EVST, 0xffffffff); in gpio_reset()
71 writel(GPIO(n) + GP_N_POL, 0x00000000); in gpio_reset()
72 writel(GPIO(n) + GP_N_DOUT, 0x00000000); in gpio_reset()
73 writel(GPIO(n) + GP_N_OE, 0x00000000); in gpio_reset()
74 writel(GPIO(n) + GP_N_OTYP, 0x00000000); in gpio_reset()
75 writel(GPIO(n) + GP_N_PU, 0xffffffff); in gpio_reset()
76 writel(GPIO(n) + GP_N_PD, 0x00000000); in gpio_reset()
[all …]
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| /openbmc/linux/arch/arc/plat-hsdk/ |
| H A D | platform.c | 209 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
210 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
211 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
212 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
213 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
215 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
216 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
217 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
218 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
219 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
[all …]
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| /openbmc/u-boot/board/freescale/s32v234evb/ |
| H A D | lpddr2.c | 21 writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0)); in lpddr2_config_iomux()
23 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0)); in lpddr2_config_iomux()
24 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1)); in lpddr2_config_iomux()
26 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0)); in lpddr2_config_iomux()
27 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1)); in lpddr2_config_iomux()
30 writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
33 writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
36 writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
39 writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
42 writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0)); in lpddr2_config_iomux()
[all …]
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| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 44 writel(CLK_SRC_CPU_VAL, &clk->src_cpu); in system_clock_init()
48 writel(CLK_SRC_TOP0_VAL, &clk->src_top0); in system_clock_init()
49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
50 writel(CLK_SRC_DMC_VAL, &clk->src_dmc); in system_clock_init()
51 writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus); in system_clock_init()
52 writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus); in system_clock_init()
53 writel(CLK_SRC_FSYS_VAL, &clk->src_fsys); in system_clock_init()
54 writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0); in system_clock_init()
55 writel(CLK_SRC_CAM_VAL, &clk->src_cam); in system_clock_init()
56 writel(CLK_SRC_MFC_VAL, &clk->src_mfc); in system_clock_init()
[all …]
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| /openbmc/u-boot/drivers/video/sunxi/ |
| H A D | tve_common.c | 19 writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) | in tvencoder_mode_set()
22 writel(SUNXI_TVE_CFG0_VGA, &tve->cfg0); in tvencoder_mode_set()
23 writel(SUNXI_TVE_DAC_CFG0_VGA, &tve->dac_cfg0); in tvencoder_mode_set()
24 writel(SUNXI_TVE_UNKNOWN1_VGA, &tve->unknown1); in tvencoder_mode_set()
27 writel(SUNXI_TVE_CHROMA_FREQ_PAL_NC, &tve->chroma_freq); in tvencoder_mode_set()
30 writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) | in tvencoder_mode_set()
34 writel(SUNXI_TVE_CFG0_PAL, &tve->cfg0); in tvencoder_mode_set()
35 writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0); in tvencoder_mode_set()
36 writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter); in tvencoder_mode_set()
37 writel(SUNXI_TVE_PORCH_NUM_PAL, &tve->porch_num); in tvencoder_mode_set()
[all …]
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| /openbmc/u-boot/drivers/video/ |
| H A D | omap3_dss.c | 41 writel(venc_cfg->status, &venc->status); in omap3_dss_venc_config()
42 writel(venc_cfg->f_control, &venc->f_control); in omap3_dss_venc_config()
43 writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl); in omap3_dss_venc_config()
44 writel(venc_cfg->sync_ctrl, &venc->sync_ctrl); in omap3_dss_venc_config()
45 writel(venc_cfg->llen, &venc->llen); in omap3_dss_venc_config()
46 writel(venc_cfg->flens, &venc->flens); in omap3_dss_venc_config()
47 writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl); in omap3_dss_venc_config()
48 writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr); in omap3_dss_venc_config()
49 writel(venc_cfg->c_phase, &venc->c_phase); in omap3_dss_venc_config()
50 writel(venc_cfg->gain_u, &venc->gain_u); in omap3_dss_venc_config()
[all …]
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