| /openbmc/qemu/target/arm/ |
| H A D | hyp_gdbstub.c | 131 .wcr = R_DBGWCR_E_MASK, /* E=1, enable */ in insert_hw_watchpoint()
144 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, PAC, 3); in insert_hw_watchpoint()
148 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 1); in insert_hw_watchpoint()
152 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 2); in insert_hw_watchpoint()
156 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 3); in insert_hw_watchpoint()
167 wp.wcr = deposit32(wp.wcr, 5 + off, 8 - off, bas); in insert_hw_watchpoint()
174 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, MASK, bits); in insert_hw_watchpoint()
175 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff); in insert_hw_watchpoint()
189 int bas = extract32(wp->wcr, 5, 8); in check_watchpoint_in_range()
190 int mask = extract32(wp->wcr, 24, 4); in check_watchpoint_in_range()
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| H A D | debug_helper.c | 552 uint64_t wcr = env->cp15.dbgwcr[n]; in hw_watchpoint_update() local
561 if (!FIELD_EX64(wcr, DBGWCR, E)) { in hw_watchpoint_update()
566 switch (FIELD_EX64(wcr, DBGWCR, LSC)) { in hw_watchpoint_update()
586 mask = FIELD_EX64(wcr, DBGWCR, MASK); in hw_watchpoint_update()
605 int bas = FIELD_EX64(wcr, DBGWCR, BAS); in hw_watchpoint_update()
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| /openbmc/qemu/hw/watchdog/ |
| H A D | wdt_imx2.c | 41 if (s->wcr & IMX2_WDT_WCR_WDE) { in imx2_wdt_expired()
64 s->wcr = IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS; in imx2_wdt_reset()
78 value = s->wcr; in imx2_wdt_read()
101 bool running = (s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT); in imx_wdt2_update_itimer()
133 if ((s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT)) { in imx_wdt2_update_timer()
134 int count = (s->wcr & IMX2_WDT_WCR_WT) >> 8; in imx_wdt2_update_timer()
175 s->wcr = value; in imx2_wdt_write()
183 s->wcr |= IMX2_WDT_WCR_SRS; in imx2_wdt_write()
243 VMSTATE_UINT16(wcr, IMX2WdtState),
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| /openbmc/linux/arch/sh/boards/ |
| H A D | board-polaris.c | 96 u16 wcr, bcr_mask; in polaris_initialise() local
103 wcr = __raw_readw(WCR2); in polaris_initialise()
104 wcr &= (~AREA5_WAIT_CTRL); in polaris_initialise()
105 wcr |= (WAIT_STATES_10 << 10); in polaris_initialise()
106 __raw_writew(wcr, WCR2); in polaris_initialise()
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| /openbmc/u-boot/drivers/watchdog/ |
| H A D | imx_watchdog.c | 42 writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr); in hw_watchdog_init()
45 WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); in hw_watchdog_init()
55 clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE); in reset_cpu()
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/ |
| H A D | reset.c | 29 writew(0x0000, ®s->wcr); in reset_cpu()
36 writew(WCR_WDE, ®s->wcr); in reset_cpu()
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/mx25/ |
| H A D | reset.c | 29 writew(0, ®s->wcr); in reset_cpu()
36 writew(WCR_WDE, ®s->wcr); in reset_cpu()
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| /openbmc/linux/tools/testing/selftests/kvm/aarch64/ |
| H A D | debug-exceptions.c | 154 uint32_t wcr; in install_wp() local
156 wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E; in install_wp()
157 write_dbgwcr(wpn, wcr); in install_wp()
180 uint32_t wcr; in install_wp_ctx() local
190 wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E | in install_wp_ctx()
192 write_dbgwcr(addr_wp, wcr); in install_wp_ctx()
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| /openbmc/u-boot/arch/arm/mach-imx/mx7/ |
| H A D | soc.c | 345 u32 reg = readw(&wdog->wcr); in set_wdog_reset()
351 reg = readw(&wdog->wcr); in set_wdog_reset()
358 writew(reg, &wdog->wcr); in set_wdog_reset()
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| /openbmc/u-boot/arch/arm/mach-imx/imx8m/ |
| H A D | soc.c | 69 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); in set_wdog_reset()
235 writew((WCR_WDE | WCR_SRS), &wdog->wcr); in reset_cpu()
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| /openbmc/u-boot/include/ |
| H A D | fsl_wdog.h | 7 u16 wcr; /* Control */ member
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| /openbmc/linux/drivers/net/ethernet/davicom/ |
| H A D | dm9000.c | 700 u32 wcr = 0; in dm9000_set_wol() local
709 wcr |= WCR_MAGICEN; in dm9000_set_wol()
714 iow(dm, DM9000_WCR, wcr); in dm9000_set_wol()
1243 unsigned nsr, wcr; in dm9000_wol_interrupt() local
1248 wcr = ior(db, DM9000_WCR); in dm9000_wol_interrupt()
1250 dev_dbg(db->dev, "%s: NSR=0x%02x, WCR=0x%02x\n", __func__, nsr, wcr); in dm9000_wol_interrupt()
1256 if (wcr & WCR_LINKST) in dm9000_wol_interrupt()
1258 if (wcr & WCR_SAMPLEST) in dm9000_wol_interrupt()
1260 if (wcr & WCR_MAGICST) in dm9000_wol_interrupt()
1262 if (!(wcr & (WCR_LINKST | WCR_SAMPLEST | WCR_MAGICST))) in dm9000_wol_interrupt()
[all …]
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| /openbmc/u-boot/arch/m68k/cpu/mcf52x2/ |
| H A D | cpu.c | 306 out_be16(&wdt->wcr, 0); in watchdog_disable()
317 out_be16(&wdt->wcr, 0); in watchdog_init()
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| /openbmc/qemu/include/hw/watchdog/ |
| H A D | wdt_imx2.h | 80 uint16_t wcr; member
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| /openbmc/u-boot/arch/m68k/include/asm/ |
| H A D | immap_5445x.h | 66 u16 wcr; member
311 u8 wcr; /* 0x13 */ member
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| H A D | immap_5282.h | 96 ushort wcr; member
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| H A D | immap_520x.h | 63 u8 wcr; /* 0x13 */ member
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| H A D | immap_5227x.h | 212 u8 wcr; /* 0x03 wakeup control */ member
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| /openbmc/u-boot/board/warp7/ |
| H A D | warp7.c | 152 clrsetbits_le16(&wdog->wcr, 0, 0x10); in board_late_init()
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | hw_breakpoint.h | 96 #define AARCH64_DBG_REG_NAME_WCR wcr
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/armada100/ |
| H A D | timer.c | 34 u32 wcr; member
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| /openbmc/u-boot/arch/arm/include/asm/arch-mx25/ |
| H A D | imx-regs.h | 80 u16 wcr; /* Control */ member
224 u32 wcr; /* WEIM Configuration Register */ member
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| /openbmc/u-boot/board/compulab/cl-som-imx7/ |
| H A D | cl-som-imx7.c | 309 clrsetbits_le16(&wdog->wcr, 0, 0x10); in cl_som_imx7_setup_wdog()
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| /openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 374 clrbits_be16(&wdog->wcr, WCR_SRS); in reset_cpu()
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| /openbmc/u-boot/board/freescale/mx53ard/ |
| H A D | mx53ard.c | 278 writel(0x0, &weim_regs->wcr); in weim_cs1_settings()
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