Home
last modified time | relevance | path

Searched refs:wave (Results 1 – 25 of 25) sorted by relevance

/openbmc/linux/sound/pci/emu10k1/
H A Demu10k1.c75 struct snd_seq_device *wave = NULL; in snd_card_emu10k1_probe() local
150 sizeof(struct snd_emu10k1_synth_arg), &wave) < 0 || in snd_card_emu10k1_probe()
151 wave == NULL) { in snd_card_emu10k1_probe()
156 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in snd_card_emu10k1_probe()
157 strcpy(wave->name, "Emu-10k1 Synth"); in snd_card_emu10k1_probe()
/openbmc/linux/sound/pci/
H A Dad1889.c90 struct ad1889_register_state wave; member
190 chip->wave.reg = reg; in ad1889_channel_reset()
358 chip->wave.size = size; in snd_ad1889_playback_prepare()
359 chip->wave.reg = reg; in snd_ad1889_playback_prepare()
360 chip->wave.addr = rt->dma_addr; in snd_ad1889_playback_prepare()
362 ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg); in snd_ad1889_playback_prepare()
368 ad1889_load_wave_buffer_address(chip, chip->wave.addr); in snd_ad1889_playback_prepare()
379 chip->wave.addr, count, size, reg, rt->rate); in snd_ad1889_playback_prepare()
460 chip->wave.reg = wsmc; in snd_ad1889_playback_trigger()
516 if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN))) in snd_ad1889_playback_pointer()
[all …]
/openbmc/linux/sound/pci/au88x0/
H A Dau88x0.c267 sizeof(snd_vortex_synth_arg_t), &wave) < 0 in __snd_vortex_probe()
268 || wave == NULL) { in __snd_vortex_probe()
273 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in __snd_vortex_probe()
274 strcpy(wave->name, "Aureal Synth"); in __snd_vortex_probe()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_2.c422 uint32_t se, cu, simd, wave; in gfx_v9_4_2_log_wave_assignment() local
439 for (wave = 0; wave < WAVE_ID_MAX; wave++) { in gfx_v9_4_2_log_wave_assignment()
456 uint32_t se, cu, simd, wave; in gfx_v9_4_2_wait_for_waves_assigned() local
468 for (wave = 0; wave < WAVE_ID_MAX; wave++) { in gfx_v9_4_2_wait_for_waves_assigned()
469 if (((1 << wave) & mask) && in gfx_v9_4_2_wait_for_waves_assigned()
1806 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1809 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
1820 uint32_t i, simd, wave; in gfx_v9_4_2_log_cu_timeout_status() local
1832 wave = i % cu_info->max_waves_per_simd; in gfx_v9_4_2_log_cu_timeout_status()
1834 wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_2_log_cu_timeout_status()
[all …]
H A Dgfx_v9_4_3.c550 …ad_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) in wave_read_ind() argument
553 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
561 uint32_t wave, uint32_t thread, in wave_read_regs() argument
565 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
576 uint32_t xcc_id, uint32_t simd, uint32_t wave, in gfx_v9_4_3_read_wave_data() argument
581 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_3_read_wave_data()
582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_4_3_read_wave_data()
583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_4_3_read_wave_data()
584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_4_3_read_wave_data()
585 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_4_3_read_wave_data()
[all …]
H A Dgfx_v6_0.c2946 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2949 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
2957 uint32_t wave, uint32_t thread, in wave_read_regs() argument
2961 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
2971 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v6_0_read_wave_data() argument
2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
2976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
2977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
2978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v6_0_read_wave_data()
2979 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v6_0_read_wave_data()
[all …]
H A Dgfx_v7_0.c4087 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
4090 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
4098 uint32_t wave, uint32_t thread, in wave_read_regs() argument
4102 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
4112 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v7_0_read_wave_data() argument
4116 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4117 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4118 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4119 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v7_0_read_wave_data()
4120 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data()
[all …]
H A Damdgpu_umr.h50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
H A Damdgpu_debugfs.c434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
1054 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
1064 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; in amdgpu_debugfs_wave_read()
1085 adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
1146 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
1156 wave = (*pos & GENMASK_ULL(43, 36)) >> 36; in amdgpu_debugfs_gpr_read()
1179 adev->gfx.funcs->read_wave_vgprs(adev, 0, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
1182 adev->gfx.funcs->read_wave_sgprs(adev, 0, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
H A Damdgpu_gfx.h288 uint32_t wave, uint32_t *dst, int *no_fields);
290 uint32_t wave, uint32_t thread, uint32_t start,
293 uint32_t wave, uint32_t start, uint32_t size,
H A Dgfx_v11_0.c759 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument
762 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
767 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument
772 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
780 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v11_0_read_wave_data() argument
789 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v11_0_read_wave_data()
790 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v11_0_read_wave_data()
791 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v11_0_read_wave_data()
792 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); in gfx_v11_0_read_wave_data()
793 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v11_0_read_wave_data()
[all …]
H A Dgfx_v8_0.c5193 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
5196 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
5204 uint32_t wave, uint32_t thread, in wave_read_regs() argument
5208 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
5218 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v8_0_read_wave_data() argument
5222 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5223 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5224 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5225 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v8_0_read_wave_data()
5226 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data()
[all …]
H A Dgfx_v9_0.c1746 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1749 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
1757 uint32_t wave, uint32_t thread, in wave_read_regs() argument
1761 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
1771 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v9_0_read_wave_data() argument
1775 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
1776 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
1777 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
1778 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_0_read_wave_data()
1779 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data()
[all …]
H A Dgfx_v10_0.c4249 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument
4252 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
4257 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument
4262 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
4270 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v10_0_read_wave_data() argument
4280 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v10_0_read_wave_data()
4281 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v10_0_read_wave_data()
4282 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v10_0_read_wave_data()
4283 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); in gfx_v10_0_read_wave_data()
4284 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v10_0_read_wave_data()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt18 - ti,clkmode-square-wave: Indicates that the board is supplying a square
19 wave input on the OSCIN pin instead of using a crystal oscillator.
61 ti,clkmode-square-wave;
/openbmc/linux/drivers/gpu/ipu-v3/
H A Dipu-dc.c120 int map, int wave, int glue, int sync, int stop) in dc_write_tmpl() argument
129 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); in dc_write_tmpl()
132 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); in dc_write_tmpl()
/openbmc/qemu/hw/ssi/
H A Dimx_spi.c155 uint8_t wave = EXTRACT(s->regs[ECSPI_CONFIGREG], ECSPI_CONFIGREG_SS_CTL); in imx_spi_is_multiple_master_burst() local
159 ((wave & (1 << imx_spi_selected_channel(s))) ? true : false); in imx_spi_is_multiple_master_burst()
/openbmc/u-boot/drivers/video/
H A Dipu_disp.c261 int wave, int glue, int sync) in ipu_dc_write_tmpl() argument
268 reg |= (++wave << 11); in ipu_dc_write_tmpl()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dnvidia,tegra124-dfll.txt56 - nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
/openbmc/openbmc/poky/meta/recipes-support/boost/
H A Dboost.inc44 wave \
/openbmc/linux/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst103 This generates a high / low square wave. The count
112 which generates sine-like tones by low-pass filtering the square wave output.
253 bit 3 = Square wave interrupt enable
/openbmc/linux/Documentation/driver-api/media/drivers/
H A Dvidtv.rst34 Elementary Stream, which in turn contains a SMPTE 302m encoded sine-wave.
/openbmc/linux/drivers/media/rc/
H A DKconfig349 wave and pulses.
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-counter115 square wave mode:
/openbmc/qemu/
H A Dhmp-commands.hx771 .help = "capture audio to a wave file (default frequency=44100 bits=16 channels=2)",