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Searched refs:w0 (Results 1 – 25 of 144) sorted by relevance

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/openbmc/linux/drivers/ata/pata_parport/
H A Don26.c51 w0(1); P1; w0(r); P2; w0(0); P1; in on26_read_regr()
57 w0(1); P1; w0(r); P2; w0(0); P1; in on26_read_regr()
79 w0(1); P1; w0(r); P2; w0(0); P1; in on26_write_regr()
80 w0(val); P2; w0(val); P2; in on26_write_regr()
95 w0(0xfe); w0(0xaa); w0(0x55); w0(0); \
96 w0(0xff); w0(0x87); w0(0x78); w0(x); \
97 w2(4); w2(5); w2(4); w0(0xff); \
113 w0(2); P1; w0(8); P2; in on26_connect()
114 w0(2); P1; w0(x); P2; in on26_connect()
122 w0(4); P1; w0(4); P1; in on26_disconnect()
[all …]
H A Ddstr.c45 w0(0x81); P1; in dstr_read_regr()
47 w0(0x11); in dstr_read_regr()
49 w0(1); in dstr_read_regr()
50 P2; w0(r); P1; in dstr_read_regr()
57 w0(0); w2(0x26); a = r0(); w2(4); in dstr_read_regr()
73 w0(0x81); P1; in dstr_write_regr()
75 w0(0x11); in dstr_write_regr()
77 w0(1); in dstr_write_regr()
78 P2; w0(r); P1; in dstr_write_regr()
83 w0(val); w2(5); w2(7); w2(5); w2(4); in dstr_write_regr()
[all …]
H A Dkbic.c43 w0(regr | 0x18 | s); w2(4); w2(6); w2(4); w2(1); w0(8); in kbic_read_regr()
44 a = r1(); w0(0x28); b = r1(); w2(4); in kbic_read_regr()
47 w0(regr|0x38 | s); w2(4); w2(6); w2(4); w2(5); w0(8); in kbic_read_regr()
51 w0(regr | 0x08 | s); w2(4); w2(6); w2(4); w2(0xa5); w2(0xa1); in kbic_read_regr()
57 w0(0x20 | s); w2(4); w2(6); w2(4); w3(regr); in kbic_read_regr()
73 w0(regr | 0x10 | s); w2(4); w2(6); w2(4); in kbic_write_regr()
74 w0(val); w2(5); w2(4); in kbic_write_regr()
79 w0(0x20 | s); w2(4); w2(6); w2(4); w3(regr); in kbic_write_regr()
95 w0(pi->saved_r0); in k951_disconnect()
101 w2(0xc4); w0(0xaa); w0(0x55); \
[all …]
H A Dbpck.c46 w0(r & 0xf); w0(r); t2(2); t2(4); in bpck_read_regr()
52 w0(r & 0xf); w0(r); t2(2); in bpck_read_regr()
60 w0(r); w2(9); w2(0); w2(0x20); in bpck_read_regr()
77 case 1: w0(r); in bpck_write_regr()
79 w0(val); in bpck_write_regr()
84 case 4: w0(r); w2(9); w2(0); in bpck_write_regr()
85 w0(val); w2(1); w2(3); w2(0); in bpck_write_regr()
104 w0(0x40); t2(2); t2(1); in bpck_write_block()
106 w0(buf[i]); in bpck_write_block()
114 w0(0x40); t2(2); t2(1); in bpck_write_block()
[all …]
H A Depat.c45 w0(0x60+r); w2(1); w0(val); w2(4); in epat_write_regr()
64 w0(r); w2(1); w2(3); in epat_read_regr()
68 w0(0x40+r); w2(1); w2(4); in epat_read_regr()
69 a = r1(); b = r2(); w0(0xff); in epat_read_regr()
72 w0(0x20+r); w2(1); w2(0x25); in epat_read_regr()
92 w0(7); w2(1); w2(3); w0(0xff); in epat_read_block()
96 w0(0xfd); in epat_read_block()
106 w0(0); w2(4); in epat_read_block()
110 w0(0x47); w2(1); w2(5); w0(0xff); in epat_read_block()
114 w0(0xfd); in epat_read_block()
[all …]
H A Depia.c48 w0(r); w2(1); w2(3); w0(r); in epia_read_regr()
53 w0(r); w2(1); w0(r & 0x37); in epia_read_regr()
54 w2(3); w2(5); w0(r | 0xf0); in epia_read_regr()
59 w0(r); w2(1); w2(0X21); w2(0x23); in epia_read_regr()
83 w0(r); w2(1); w0(val); w2(3); w2(4); in epia_write_regr()
108 w2(4); w0(0xa0); w0(0x50); w0(0xc0); w0(0x30); w0(0xa0); w0(0); in epia_connect()
111 w0(0xa); w2(1); w2(4); w0(0x82); w2(4); w2(0xc); w2(4); in epia_connect()
120 w0(pi->saved_r0); in epia_disconnect()
122 w0(pi->saved_r0); in epia_disconnect()
133 w0(0x81); w2(1); w2(3); w0(0xc1); in epia_read_block()
[all …]
H A Dfit2.c40 w2(0xc); w0(regr); w2(4); w0(val); w2(5); w0(0); w2(4); in fit2_write_regr()
55 w2(0xc); w0(r); w2(4); w2(5); in fit2_read_regr()
56 w0(0); a = r1(); in fit2_read_regr()
57 w0(1); b = r1(); in fit2_read_regr()
67 w2(0xc); w0(0x10); in fit2_read_block()
71 w0(0); a = r1(); w0(1); b = r1(); in fit2_read_block()
72 w0(3); c = r1(); w0(2); d = r1(); in fit2_read_block()
77 a = r1(); w0(3); b = r1(); in fit2_read_block()
78 w0(1); c = r1(); w0(0); d = r1(); in fit2_read_block()
90 w2(0xc); w0(0); in fit2_write_block()
[all …]
H A Dcomm.c44 w0(r); P1; w0(0); in comm_read_regr()
45 w2(6); l = r1(); w0(0x80); h = r1(); w2(4); in comm_read_regr()
49 w0(r+0x20); P1; in comm_read_regr()
50 w0(0); w2(0x26); h = r0(); w2(4); in comm_read_regr()
71 w0(r); P1; w0(val); P2; in comm_write_regr()
85 w2(4); w0(0xff); w2(6); in comm_connect()
86 w2(4); w0(0xaa); w2(6); in comm_connect()
87 w2(4); w0(0x00); w2(6); in comm_connect()
88 w2(4); w0(0x87); w2(6); in comm_connect()
89 w2(4); w0(0xe0); w2(0xc); w2(0xc); w2(4); in comm_connect()
[all …]
H A Dfit3.c40 w2(0xc); w0(regr); w2(0x8); w2(0xc); in fit3_write_regr()
41 w0(val); w2(0xd); in fit3_write_regr()
42 w0(0); w2(0xc); in fit3_write_regr()
45 w2(0xc); w0(regr); w2(0x8); w2(0xc); in fit3_write_regr()
60 w2(0xc); w0(regr + 0x10); w2(0x8); w2(0xc); in fit3_read_regr()
66 w2(0xc); w0(regr + 0x90); w2(0x8); w2(0xc); in fit3_read_regr()
71 w2(0xc); w0(regr + 0x90); w2(0x8); w2(0xc); in fit3_read_regr()
87 w2(0xc); w0(0x10); w2(0x8); w2(0xc); in fit3_read_block()
99 w2(0xc); w0(0x90); w2(0x8); w2(0xc); in fit3_read_block()
111 w2(0xc); w0(0x90); w2(0x8); w2(0xc); in fit3_read_block()
[all …]
H A Daten.c32 w0(r); w2(0xe); w2(6); w0(val); w2(7); w2(6); w2(0xc); in aten_write_regr()
44 w0(r); w2(0xe); w2(6); in aten_read_regr()
46 a = r1(); w0(0x10); b = r1(); w2(0xc); in aten_read_regr()
51 w0(r); w2(0xe); w2(6); w0(0xff); in aten_read_regr()
67 w0(0x48); w2(0xe); w2(6); in aten_read_block()
70 a = r1(); w0(0x58); b = r1(); in aten_read_block()
71 w2(0); d = r1(); w0(0x48); c = r1(); in aten_read_block()
79 w0(0x58); w2(0xe); w2(6); in aten_read_block()
95 w0(0x88); w2(0xe); w2(6); in aten_write_block()
97 w0(buf[2 * k + 1]); w2(0xe); w2(6); in aten_write_block()
[all …]
H A Dfrpw.c39 w0(r); cec4; in frpw_read_regr()
51 w2(4); w0(r); cec4; in frpw_write_regr()
52 w0(val); in frpw_write_regr()
63 w2(4); w0(regr); cec4; in frpw_read_block_int()
74 w2(4); w0(regr + 0xc0); cec4; in frpw_read_block_int()
75 w0(0xff); in frpw_read_block_int()
85 w2(4); w0(regr + 0x80); cec4; in frpw_read_block_int()
93 w2(4); w0(regr + 0x80); cec4; in frpw_read_block_int()
103 w2(4); w0(regr + 0x80); cec4; in frpw_read_block_int()
113 w2(4); w0(regr + 0x80); cec4; in frpw_read_block_int()
[all …]
H A Dfriq.c33 w2(4); w0(0xff); w0(0xff); w0(0x73); w0(0x73); \
34 w0(0xc9); w0(0xc9); w0(0x26); \
35 w0(0x26); w0(x); w0(x); \
65 w0(val); in friq_write_regr()
86 w0(0xff); in friq_read_block_int()
140 w0(buf[k]); in friq_write_block()
176 w0(pi->saved_r0); in friq_disconnect()
187 w0(0xff); udelay(20); CMD(0x3d); /* turn the power on */ in friq_test_proto()
189 w0(pi->saved_r0); in friq_test_proto()
H A Dktti.c32 w0(r); w2(0xb); w2(0xa); w2(3); w2(6); in ktti_write_regr()
33 w0(val); w2(3); w0(0); w2(6); w2(0xb); in ktti_write_regr()
42 w0(r); w2(0xb); w2(0xa); w2(9); w2(0xc); w2(9); in ktti_read_regr()
52 w0(0x10); w2(0xb); w2(0xa); w2(9); w2(0xc); w2(9); in ktti_read_block()
65 w0(0x10); w2(0xb); w2(0xa); w2(3); w2(6); in ktti_write_block()
66 w0(buf[2 * k]); w2(3); in ktti_write_block()
67 w0(buf[2 * k + 1]); w2(6); in ktti_write_block()
76 w2(0xb); w2(0xa); w0(0); w2(3); w2(6); in ktti_connect()
81 w2(0xb); w2(0xa); w0(0xa0); w2(3); w2(4); in ktti_disconnect()
82 w0(pi->saved_r0); in ktti_disconnect()
/openbmc/linux/arch/arm64/lib/
H A Dcrc32.S51 bitorder w0, \be
74 crc32\c\()x w8, w0, x3
76 csel w0, w0, w8, eq
79 crc32\c\()w w8, w0, w3
81 csel w0, w0, w8, eq
84 crc32\c\()h w8, w0, w3
86 csel w0, w0, w8, eq
88 crc32\c\()b w8, w0, w3
89 csel w0, w0, w8, eq
91 crc32\c\()x w8, w0, x5
[all …]
/openbmc/linux/tools/testing/selftests/arm64/fp/
H A Dasm-utils.S37 1: mov w0, #1 // STDOUT_FILENO
57 add w0, w0, #'0'
58 strb w0, [x1, #-1]!
62 ldrb w0, [x1]
63 cbnz w0, 1f
64 mov w0, #'0' // Print "0" for 0, not ""
65 strb w0, [x1, #-1]!
92 mov w3, w0
93 lsr w0, w0, #4
95 mov w0, w3
[all …]
H A Dzt-test.S43 bfi w3, w0, #8, #16 // PID
149 mov w21, w0
153 mov w0, w21
174 mov w4, w0
182 mov w0, w4
191 cbz w0, 1f
205 mov w0, #SIGINT
210 mov w0, #SIGTERM
215 mov w0, #SIGUSR1
221 mov w0, #SIGUSR2
/openbmc/linux/arch/powerpc/crypto/
H A Dsha1-spe-asm.S106 #define R_00_15(a, b, c, d, e, w0, w1, k, off) \ argument
107 LOAD_DATA(w0, off) /* 1: W */ \
115 add e,e,w0; /* 1: E = E + W */ \
127 evmergelo w1,w1,w0; /* mix W[0]/W[1] */ \
130 #define R_16_19(a, b, c, d, e, w0, w1, w4, w6, w7, k) \ argument
134 evxor w0,w0,rT0; /* W = W[-16] xor W[-3] */ \
136 evxor w0,w0,w4; /* W = W xor W[-8] */ \
138 evxor w0,w0,w1; /* W = W xor W[-14] */ \
140 evrlwi w0,w0,1; /* W = W rotl 1 */ \
142 evaddw rT0,w0,rK; /* WK = W + K */ \
[all …]
H A Dmd5-asm.S61 #define R_00_15(a, b, c, d, w0, w1, p, q, off, k0h, k0l, k1h, k1l) \ argument
62 LOAD_DATA(w0, off) /* W */ \
68 addi w0,w0,k0l; /* 1: wk = w + k */ \
70 addis w0,w0,k0h; /* 1: wk = w + k' */ \
72 add a,a,w0; /* 1: a = a + wk */ \
85 #define R_16_31(a, b, c, d, w0, w1, p, q, k0h, k0l, k1h, k1l) \ argument
88 addi w0,w0,k0l; /* 1: wk = w + k */ \
90 addis w0,w0,k0h; /* 1: wk = w + k' */ \
93 add a,a,w0; /* 1: a = a + wk */ \
105 #define R_32_47(a, b, c, d, w0, w1, p, q, k0h, k0l, k1h, k1l) \ argument
[all …]
/openbmc/linux/Documentation/translations/zh_CN/core-api/
H A Dworkqueue.rst213 工作项w0、w1、w2被排到同一个CPU上的一个绑定的wq q0上。w0
220 0 w0 starts and burns CPU
221 5 w0 sleeps
222 15 w0 wakes up and burns CPU
223 20 w0 finishes
234 0 w0 starts and burns CPU
235 5 w0 sleeps
240 15 w0 wakes up and burns CPU
241 20 w0 finishes
248 0 w0 starts and burns CPU
[all …]
/openbmc/qemu/include/hw/ppc/
H A Dxive2_regs.h60 uint32_t w0; member
112 #define xive2_end_is_valid(end) (be32_to_cpu((end)->w0) & END2_W0_VALID)
113 #define xive2_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END2_W0_ENQUEUE)
115 (be32_to_cpu((end)->w0) & END2_W0_UCOND_NOTIFY)
116 #define xive2_end_is_backlog(end) (be32_to_cpu((end)->w0) & END2_W0_BACKLOG)
118 (be32_to_cpu((end)->w0) & END2_W0_PRECL_ESC_CTL)
120 (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_CTL)
122 (be32_to_cpu((end)->w0) & END2_W0_UNCOND_ESCALATE)
124 (be32_to_cpu((end)->w0) & END2_W0_SILENT_ESCALATE)
126 (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_END)
[all …]
H A Dxive_regs.h213 uint32_t w0; member
259 #define xive_end_is_valid(end) (be32_to_cpu((end)->w0) & END_W0_VALID)
260 #define xive_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END_W0_ENQUEUE)
261 #define xive_end_is_notify(end) (be32_to_cpu((end)->w0) & END_W0_UCOND_NOTIFY)
262 #define xive_end_is_backlog(end) (be32_to_cpu((end)->w0) & END_W0_BACKLOG)
263 #define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL)
265 (be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE)
267 (be32_to_cpu((end)->w0) & END_W0_SILENT_ESCALATE)
269 (be32_to_cpu((end)->w0) & END_W0_FIRMWARE)
283 uint32_t w0; member
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S101 lsr w0, w0, #16
103 cmp w0, w1
186 ldr w0, [x1, #0x10]
187 orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
188 str w0, [x1, #0x10]
220 orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
221 str w0, [x1]
233 lsr w0, w0, #16
235 cmp w0, w1
255 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
[all …]
/openbmc/linux/crypto/
H A Daria_generic.c31 u32 w0[4], w1[4], w2[4], w3[4]; in aria_set_encrypt_key() local
38 w0[0] = be32_to_cpu(key[0]); in aria_set_encrypt_key()
39 w0[1] = be32_to_cpu(key[1]); in aria_set_encrypt_key()
40 w0[2] = be32_to_cpu(key[2]); in aria_set_encrypt_key()
41 w0[3] = be32_to_cpu(key[3]); in aria_set_encrypt_key()
43 reg0 = w0[0] ^ ck[0]; in aria_set_encrypt_key()
44 reg1 = w0[1] ^ ck[1]; in aria_set_encrypt_key()
45 reg2 = w0[2] ^ ck[2]; in aria_set_encrypt_key()
46 reg3 = w0[3] ^ ck[3]; in aria_set_encrypt_key()
84 reg0 ^= w0[0]; in aria_set_encrypt_key()
[all …]
H A Dcamellia_generic.c319 #define ROLDQ(ll, lr, rl, rr, w0, w1, bits) ({ \ argument
320 w0 = ll; \
324 rr = (rr << bits) + (w0 >> (32 - bits)); \
327 #define ROLDQo32(ll, lr, rl, rr, w0, w1, bits) ({ \ argument
328 w0 = ll; \
332 rl = (rr << (bits - 32)) + (w0 >> (64 - bits)); \
333 rr = (w0 << (bits - 32)) + (w1 >> (64 - bits)); \
540 u32 il, ir, t0, t1, w0, w1; in camellia_setup128() local
558 ROLDQ(kll, klr, krl, krr, w0, w1, 15); in camellia_setup128()
564 ROLDQ(kll, klr, krl, krr, w0, w1, 30); in camellia_setup128()
[all …]
/openbmc/qemu/tests/qtest/
H A Dpnv-xive2-common.c102 nvp.w0 = xive_set_field32(NVP2_W0_VALID, 0, 1); in set_nvp()
103 nvp.w0 = xive_set_field32(NVP2_W0_PGOFIRST, nvp.w0, first); in set_nvp()
138 nvg.w0 = xive_set_field32(NVGC2_W0_VALID, 0, 1); in set_nvg()
139 nvg.w0 = xive_set_field32(NVGC2_W0_PGONEXT, nvg.w0, next); in set_nvg()
172 end.w0 = xive_set_field32(END2_W0_VALID, 0, 1); in set_end()
173 end.w0 = xive_set_field32(END2_W0_ENQUEUE, end.w0, 1); in set_end()
174 end.w0 = xive_set_field32(END2_W0_UCOND_NOTIFY, end.w0, 1); in set_end()
175 end.w0 = xive_set_field32(END2_W0_BACKLOG, end.w0, 1); in set_end()

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