| /openbmc/qemu/target/riscv/ |
| H A D | vcrypto_helper.c | 218 void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
229 round_key.d[0] = *((uint64_t *)vs2 + H8(i * 2 + 0)); \
230 round_key.d[1] = *((uint64_t *)vs2 + H8(i * 2 + 1)); \
244 void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
255 round_key.d[0] = *((uint64_t *)vs2 + H8(0)); \
256 round_key.d[1] = *((uint64_t *)vs2 + H8(1)); \
307 uint32_t *vs2 = vs2_vptr; local
326 rk[0] = vs2[i * 4 + H4(0)];
327 rk[1] = vs2[i * 4 + H4(1)];
328 rk[2] = vs2[i * 4 + H4(2)];
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| H A D | vector_internals.h | 143 static void do_##NAME(void *vd, void *vs2, int i) \
145 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
150 void HELPER(NAME)(void *vd, void *v0, void *vs2, \
170 do_##NAME(vd, vs2, i); \
179 typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
182 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
185 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
189 void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
196 void *vs2, CPURISCVState *env, \
199 do_vext_vv(vd, v0, vs1, vs2, env, desc, \
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| H A D | vector_internals.c | 58 void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, in do_vext_vv() argument
77 fn(vd, vs1, vs2, i); in do_vext_vv()
84 void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, in do_vext_vx() argument
103 fn(vd, s1, vs2, i); in do_vext_vx()
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| H A D | vector_helper.c | 508 uint32_t idx, void *vs2);
512 uint32_t idx, void *vs2) \
514 return (base + *((ETYPE *)vs2 + H(idx))); \
524 void *vs2, CPURISCVState *env, uint32_t desc, in GEN_VEXT_GET_INDEX_ADDR()
549 abi_ptr addr = get_index_addr(base, i, vs2) + (k << log2_esz); in GEN_VEXT_GET_INDEX_ADDR()
561 void *vs2, CPURISCVState *env, uint32_t desc) \
563 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
586 void *vs2, CPURISCVState *env, uint32_t desc) \ in GEN_VEXT_LD_INDEX()
588 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ in GEN_VEXT_LD_INDEX()
1085 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ in RVVCALL()
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| /openbmc/qemu/target/riscv/insn_trans/ |
| H A D | trans_rvv.c.inc | 289 static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
294 require_align(vs2, emul) &&
320 * register (vs2) group.
323 * the source vector register (vs2) group for
326 static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
331 bool ret = vext_check_st_index(s, vd, vs2, nf, eew) &&
339 if (seg_vd != vs2) {
340 ret &= require_noover(seg_vd, s->lmul, vs2, emul);
343 ret &= require_noover(seg_vd, s->lmul, vs2, emul);
348 * the source vector register (vs2) group for
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| H A D | trans_rvvk.c.inc | 287 static bool vaes_check_overlap(DisasContext *s, int vd, int vs2)
290 return !is_overlapped(vd, op_size, vs2, 1);
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| /openbmc/linux/arch/arm/boot/dts/qcom/ |
| H A D | pm8941.dtsi | 224 interrupt-names = "ocp-5vs1", "ocp-5vs2";
243 pm8941_5vs2: 5vs2 {
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| /openbmc/qemu/tcg/riscv/ |
| H A D | tcg-target.c.inc | 535 TCGReg vs2, bool vm)
538 (vs2 & 0x1f) << 20 | (vm << 25);
689 * With RVV 1.0, vs2 is the first operand, while rs1/imm is the
693 TCGReg vd, TCGReg vs2, TCGReg vs1)
695 tcg_out32(s, encode_v(opc, vd, vs1, vs2, true));
699 TCGReg vd, TCGReg vs2, TCGReg rs1)
701 tcg_out32(s, encode_v(opc, vd, rs1, vs2, true));
705 TCGReg vd, TCGReg vs2, int32_t imm)
707 tcg_out32(s, encode_vi(opc, vd, imm, vs2, true));
711 TCGReg vd, TCGReg vs2, TCGArg vi1, int c_vi1)
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| /openbmc/linux/arch/powerpc/crypto/ |
| H A D | poly1305-p10le_64.S | 32 # vs2 = [r2,.....]
331 # vs2 = [r2,...]
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| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt6359.dtsi | 60 regulator-name = "vs2";
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| H A D | mt6358.dtsi | 87 regulator-name = "vs2";
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| /openbmc/linux/Documentation/devicetree/bindings/regulator/ |
| H A D | mt6358-regulator.txt | 82 regulator-name = "vs2";
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| /openbmc/linux/tools/testing/selftests/powerpc/primitives/asm/ |
| H A D | ppc_asm.h | 694 #define vs2 2
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | ppc_asm.h | 694 #define vs2 2
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