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Searched refs:vlv (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Di9xx_wm.c235 dev_priv->display.wm.vlv.cxsr = enable; in intel_set_memory_cxsr()
266 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_get_fifo_size()
1448 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; in vlv_compute_fifo()
1449 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_compute_fifo()
1562 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_set()
1586 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_compute()
1605 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], in vlv_raw_plane_wm_compute()
1606 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], in vlv_raw_plane_wm_compute()
1607 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); in vlv_raw_plane_wm_compute()
1616 &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_is_valid()
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H A Dintel_display_power_map.c204 .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
211 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01),
213 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23),
215 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01),
217 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23),
223 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
291 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
294 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
H A Dintel_display_power_well.h73 } vlv; member
H A Dintel_display_core.h253 struct vlv_wm_values vlv; member
H A Dintel_display_types.h954 } vlv; member
1467 struct vlv_wm_state vlv; member
H A Dintel_display_power_well.c1077 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; in vlv_set_power_well()
1126 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; in vlv_power_well_enabled()
/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_clock_gating.c815 CG_FUNCS(vlv);