| /openbmc/linux/arch/alpha/lib/ |
| H A D | fpreg.c | 14 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); argument
16 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); argument
22 unsigned long val; in alpha_read_fp_reg() local
28 val = current_thread_info()->fp[reg]; in alpha_read_fp_reg()
30 case 0: STT( 0, val); break; in alpha_read_fp_reg()
31 case 1: STT( 1, val); break; in alpha_read_fp_reg()
32 case 2: STT( 2, val); break; in alpha_read_fp_reg()
33 case 3: STT( 3, val); break; in alpha_read_fp_reg()
34 case 4: STT( 4, val); break; in alpha_read_fp_reg()
35 case 5: STT( 5, val); break; in alpha_read_fp_reg()
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| /openbmc/linux/drivers/media/tuners/ |
| H A D | tda18271-maps.c | 19 u8 val; member
190 { .rfmax = 62000, .val = 0x00 },
191 { .rfmax = 84000, .val = 0x01 },
192 { .rfmax = 100000, .val = 0x02 },
193 { .rfmax = 140000, .val = 0x03 },
194 { .rfmax = 170000, .val = 0x04 },
195 { .rfmax = 180000, .val = 0x05 },
196 { .rfmax = 865000, .val = 0x06 },
197 { .rfmax = 0, .val = 0x00 }, /* end */
201 { .rfmax = 61100, .val = 0x74 },
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| /openbmc/u-boot/include/bedbug/ |
| H A D | regs.h | 169 #define SET_REGISTER( str, val ) \ argument
170 ({ unsigned long __value = (val); \
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val ) argument
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val ) argument
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val ) argument
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val ) argument
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val ) argument
190 #define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val ) argument
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val ) argument
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val ) argument
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| /openbmc/linux/drivers/hwtracing/coresight/ |
| H A D | coresight-etm-cp14.c | 15 int etm_readl_cp14(u32 reg, unsigned int *val) in etm_readl_cp14() argument
19 *val = etm_read(ETMCR); in etm_readl_cp14()
22 *val = etm_read(ETMCCR); in etm_readl_cp14()
25 *val = etm_read(ETMTRIGGER); in etm_readl_cp14()
28 *val = etm_read(ETMSR); in etm_readl_cp14()
31 *val = etm_read(ETMSCR); in etm_readl_cp14()
34 *val = etm_read(ETMTSSCR); in etm_readl_cp14()
37 *val = etm_read(ETMTEEVR); in etm_readl_cp14()
40 *val = etm_read(ETMTECR1); in etm_readl_cp14()
43 *val = etm_read(ETMFFLR); in etm_readl_cp14()
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| H A D | coresight-etm4x.h | 243 #define WRITE_ETM4x_REG(val, reg) \ argument
244 write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg)))
249 #define write_etm4x_sysreg_const_offset(val, offset) \ argument
250 WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset))
255 #define CASE_WRITE(val, x) \ argument
256 case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; }
261 #define ETE_ONLY_SYSREG_LIST(op, val) \ argument
262 CASE_##op((val), TRCRSR) \
263 CASE_##op((val), TRCEXTINSELRn(1)) \
264 CASE_##op((val), TRCEXTINSELRn(2)) \
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| /openbmc/linux/arch/arm/include/asm/hardware/ |
| H A D | cp14.h | 12 #define dbg_write(val, reg) WCP14_##reg(val) argument
14 #define etm_write(val, reg) WCP14_##reg(val) argument
19 u32 val; \
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
21 val; \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) argument
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) argument
154 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) argument
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| /openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| H A D | types.h | 133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
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| /openbmc/linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a6xx.xml.h | 1123 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_MRB_START() argument
1125 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_ST… in A6XX_CP_ROQ_THRESHOLDS_1_MRB_START()
1129 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_VSD_START() argument
1131 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_ST… in A6XX_CP_ROQ_THRESHOLDS_1_VSD_START()
1135 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START() argument
1137 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_ST… in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START()
1141 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START() argument
1143 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_ST… in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START()
1149 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START() argument
1151 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_ST… in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START()
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| H A D | adreno_pm4.xml.h | 526 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF() argument
528 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; in CP_LOAD_STATE_0_DST_OFF()
532 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC() argument
534 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; in CP_LOAD_STATE_0_STATE_SRC()
538 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK() argument
540 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; in CP_LOAD_STATE_0_STATE_BLOCK()
544 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT() argument
546 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; in CP_LOAD_STATE_0_NUM_UNIT()
552 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE() argument
554 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; in CP_LOAD_STATE_1_STATE_TYPE()
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| H A D | a3xx.xml.h | 947 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES() argument
949 …return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_… in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES()
955 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument
957 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
961 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument
963 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
969 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET() argument
971 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; in A3XX_GRAS_CL_VPORT_XOFFSET()
977 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE() argument
979 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; in A3XX_GRAS_CL_VPORT_XSCALE()
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| H A D | a4xx.xml.h | 845 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC() argument
847 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; in A4XX_CGC_HLSQ_EARLY_CYC()
902 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument
904 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WID… in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
908 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument
910 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HE… in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
924 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH() argument
926 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; in A4XX_RB_MODE_CONTROL_WIDTH()
930 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT() argument
932 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; in A4XX_RB_MODE_CONTROL_HEIGHT()
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| H A D | a5xx.xml.h | 1043 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A5XX_CP_PROTECT_REG_BASE_ADDR() argument
1045 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; in A5XX_CP_PROTECT_REG_BASE_ADDR()
1049 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A5XX_CP_PROTECT_REG_MASK_LEN() argument
1051 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; in A5XX_CP_PROTECT_REG_MASK_LEN()
1055 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_WRITE() argument
1057 return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK; in A5XX_CP_PROTECT_REG_TRAP_WRITE()
1061 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_READ() argument
1063 return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK; in A5XX_CP_PROTECT_REG_TRAP_READ()
1838 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val) in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB() argument
1840 …return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MA… in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB()
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| H A D | a2xx.xml.h | 1172 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR() argument
1174 …return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR()
1178 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR() argument
1180 …return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR()
1184 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR() argument
1186 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR()
1190 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR() argument
1192 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR()
1196 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR() argument
1198 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR()
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| H A D | adreno_common.xml.h | 230 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) in AXXX_CP_RB_CNTL_BUFSZ() argument
232 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; in AXXX_CP_RB_CNTL_BUFSZ()
236 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) in AXXX_CP_RB_CNTL_BLKSZ() argument
238 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; in AXXX_CP_RB_CNTL_BLKSZ()
242 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) in AXXX_CP_RB_CNTL_BUF_SWAP() argument
244 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; in AXXX_CP_RB_CNTL_BUF_SWAP()
253 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) in AXXX_CP_RB_RPTR_ADDR_SWAP() argument
255 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; in AXXX_CP_RB_RPTR_ADDR_SWAP()
259 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) in AXXX_CP_RB_RPTR_ADDR_ADDR() argument
261 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; in AXXX_CP_RB_RPTR_ADDR_ADDR()
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| /openbmc/qemu/target/hppa/ |
| H A D | gdbstub.c | 33 uint32_t val; in hppa_cpu_gdb_read_register() local
37 val = cpu_hppa_get_psw(env); in hppa_cpu_gdb_read_register()
40 val = env->gr[n]; in hppa_cpu_gdb_read_register()
43 val = env->cr[CR_SAR]; in hppa_cpu_gdb_read_register()
46 val = env->iaoq_f; in hppa_cpu_gdb_read_register()
49 val = env->iasq_f >> 32; in hppa_cpu_gdb_read_register()
52 val = env->iaoq_b; in hppa_cpu_gdb_read_register()
55 val = env->iasq_b >> 32; in hppa_cpu_gdb_read_register()
58 val = env->cr[CR_EIEM]; in hppa_cpu_gdb_read_register()
61 val = env->cr[CR_IIR]; in hppa_cpu_gdb_read_register()
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| /openbmc/linux/drivers/phy/ |
| H A D | phy-xgene.c | 555 u32 val; in sds_wr() local
565 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
566 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr()
568 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr()
577 u32 val; in sds_rd() local
585 val = readl(csr_base + indirect_cmd_reg); in sds_rd()
586 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd()
589 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd()
598 u32 val; in cmu_wr() local
607 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr()
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| /openbmc/u-boot/drivers/net/phy/ |
| H A D | mv88e61xx.c | 224 int val; in mv88e61xx_smi_wait() local
228 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG); in mv88e61xx_smi_wait()
229 if (val >= 0 && (val & SMI_BUSY) == 0) in mv88e61xx_smi_wait()
292 u16 val) in mv88e61xx_reg_write() argument
302 val); in mv88e61xx_reg_write()
312 SMI_DATA_REG, val); in mv88e61xx_reg_write()
332 int val; in mv88e61xx_phy_wait() local
336 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, in mv88e61xx_phy_wait()
338 if (val >= 0 && (val & SMI_BUSY) == 0) in mv88e61xx_phy_wait()
403 int reg, u16 val) in mv88e61xx_phy_write() argument
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| /openbmc/linux/drivers/net/wireless/realtek/rtw89/ |
| H A D | fw.h | 341 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_IDX() argument
343 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_SEC_IDX()
346 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_OFFSET() argument
348 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_SEC_OFFSET()
351 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_LEN() argument
353 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); in RTW89_SET_FWCMD_SEC_LEN()
356 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_TYPE() argument
358 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); in RTW89_SET_FWCMD_SEC_TYPE()
361 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_EXT_KEY() argument
363 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); in RTW89_SET_FWCMD_SEC_EXT_KEY()
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| /openbmc/linux/drivers/gpu/drm/msm/dsi/ |
| H A D | dsi.xml.h | 146 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) in DSI_6G_HW_VERSION_MAJOR() argument
148 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; in DSI_6G_HW_VERSION_MAJOR()
152 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) in DSI_6G_HW_VERSION_MINOR() argument
154 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; in DSI_6G_HW_VERSION_MINOR()
158 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) in DSI_6G_HW_VERSION_STEP() argument
160 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; in DSI_6G_HW_VERSION_STEP()
213 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) in DSI_VID_CFG0_VIRT_CHANNEL() argument
215 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; in DSI_VID_CFG0_VIRT_CHANNEL()
219 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) in DSI_VID_CFG0_DST_FORMAT() argument
221 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; in DSI_VID_CFG0_DST_FORMAT()
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| /openbmc/u-boot/arch/mips/include/asm/ |
| H A D | mipsregs.h | 880 #define write_r10k_perf_cntr(counter,val) \ argument
885 : "r" (val), "i" (counter)); \
899 #define write_r10k_perf_cntl(counter,val) \ argument
904 : "r" (val), "i" (counter)); \
983 #define __write_ulong_c0_register(reg, sel, val) \ argument
986 __write_32bit_c0_register(reg, sel, val); \
988 __write_64bit_c0_register(reg, sel, val); \
1039 #define __write_64bit_c0_split(source, sel, val) \ argument
1050 : : "r" (val)); \
1060 : : "r" (val)); \
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| /openbmc/linux/arch/mips/include/asm/ |
| H A D | mipsregs.h | 1383 #define write_r10k_perf_cntr(counter,val) \ argument
1388 : "r" (val), "i" (counter)); \
1402 #define write_r10k_perf_cntl(counter,val) \ argument
1407 : "r" (val), "i" (counter)); \
1509 #define __write_ulong_c0_register(reg, sel, val) \ argument
1512 __write_32bit_c0_register(reg, sel, val); \
1514 __write_64bit_c0_register(reg, sel, val); \
1568 #define __write_64bit_c0_split(source, sel, val) \ argument
1570 unsigned long long __tmp = (val); \
1655 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) argument
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| /openbmc/linux/tools/perf/util/ |
| H A D | expr.y | 38 double val;
74 static bool is_const(double val)
76 return isfinite(val);
82 .val = BOTTOM,
100 result.val = NAN;
102 result.val = source_count
113 result.val = BOTTOM;
129 if (!compute_ids || (is_const(LHS.val) && is_const(RHS.val))) { \
132 if (isnan(LHS.val) || isnan(RHS.val)) { \
133 RESULT.val = NAN; \
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| /openbmc/linux/arch/mips/pci/ |
| H A D | pci-bcm63xx.c | 109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg) in bcm63xx_int_cfg_writel() argument
116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG); in bcm63xx_int_cfg_writel()
123 u32 val; in bcm63xx_reset_pcie() local
132 val = bcm_misc_readl(reg); in bcm63xx_reset_pcie()
133 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; in bcm63xx_reset_pcie()
134 bcm_misc_writel(val, reg); in bcm63xx_reset_pcie()
152 u32 val; in bcm63xx_register_pcie() local
164 val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); in bcm63xx_register_pcie()
165 val |= OPT1_RD_BE_OPT_EN; in bcm63xx_register_pcie()
166 val |= OPT1_RD_REPLY_BE_FIX_EN; in bcm63xx_register_pcie()
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| /openbmc/linux/drivers/net/ethernet/chelsio/cxgb4/ |
| H A D | cxgb4_tc_u32_parse.h | 41 int (*val)(struct ch_filter_specification *f, __be32 val, __be32 mask); member
46 __be32 val, __be32 mask) in cxgb4_fill_ipv4_tos() argument
48 f->val.tos = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
55 __be32 val, __be32 mask) in cxgb4_fill_ipv4_frag() argument
60 frag_val = (ntohl(val) >> 13) & 0x00000007; in cxgb4_fill_ipv4_frag()
64 f->val.frag = 1; in cxgb4_fill_ipv4_frag()
67 f->val.frag = 0; in cxgb4_fill_ipv4_frag()
77 __be32 val, __be32 mask) in cxgb4_fill_ipv4_proto() argument
79 f->val.proto = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_proto()
86 __be32 val, __be32 mask) in cxgb4_fill_ipv4_src_ip() argument
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| /openbmc/qemu/util/ |
| H A D | lockcnt.c | 57 static bool qemu_lockcnt_cmpxchg_or_wait(QemuLockCnt *lockcnt, int *val, in qemu_lockcnt_cmpxchg_or_wait() argument
61 if ((*val & QEMU_LOCKCNT_STATE_MASK) == QEMU_LOCKCNT_STATE_FREE) { in qemu_lockcnt_cmpxchg_or_wait()
62 int expected = *val; in qemu_lockcnt_cmpxchg_or_wait()
65 *val = qatomic_cmpxchg(&lockcnt->count, expected, new_if_free); in qemu_lockcnt_cmpxchg_or_wait()
66 if (*val == expected) { in qemu_lockcnt_cmpxchg_or_wait()
68 *val = new_if_free; in qemu_lockcnt_cmpxchg_or_wait()
79 while ((*val & QEMU_LOCKCNT_STATE_MASK) != QEMU_LOCKCNT_STATE_FREE) { in qemu_lockcnt_cmpxchg_or_wait()
80 if ((*val & QEMU_LOCKCNT_STATE_MASK) == QEMU_LOCKCNT_STATE_LOCKED) { in qemu_lockcnt_cmpxchg_or_wait()
81 int expected = *val; in qemu_lockcnt_cmpxchg_or_wait()
85 *val = qatomic_cmpxchg(&lockcnt->count, expected, new); in qemu_lockcnt_cmpxchg_or_wait()
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