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Searched refs:use_mips32r6_instructions (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/tcg/mips/
H A Dtcg-target.h112 #define use_mips32r6_instructions 1 macro
114 #define use_mips32r6_instructions 0 macro
126 #define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions)
127 #define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions)
147 #define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions)
148 #define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions)
H A Dtcg-target.c.inc344 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
350 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
1053 if (use_mips32r6_instructions && v1 == 0) {
1063 if (use_mips32r6_instructions) {
1311 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
1324 if (use_mips32r6_instructions) {
1461 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
1548 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
1581 if (use_mips32r6_instructions) {
1813 if (use_mips32r6_instructions) {
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